DE2129676A1 - Halbleiter-Einrichtung und Verfahren zu ihrer Herstellung - Google Patents

Halbleiter-Einrichtung und Verfahren zu ihrer Herstellung

Info

Publication number
DE2129676A1
DE2129676A1 DE19712129676 DE2129676A DE2129676A1 DE 2129676 A1 DE2129676 A1 DE 2129676A1 DE 19712129676 DE19712129676 DE 19712129676 DE 2129676 A DE2129676 A DE 2129676A DE 2129676 A1 DE2129676 A1 DE 2129676A1
Authority
DE
Germany
Prior art keywords
semiconductor
layer
conductivity type
substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19712129676
Other languages
German (de)
English (en)
Inventor
Hiroto Kawagoe
Seiichi Tachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2129676A1 publication Critical patent/DE2129676A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
DE19712129676 1970-06-15 1971-06-15 Halbleiter-Einrichtung und Verfahren zu ihrer Herstellung Pending DE2129676A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5100070 1970-06-15

Publications (1)

Publication Number Publication Date
DE2129676A1 true DE2129676A1 (de) 1972-02-10

Family

ID=12874501

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19712129676 Pending DE2129676A1 (de) 1970-06-15 1971-06-15 Halbleiter-Einrichtung und Verfahren zu ihrer Herstellung

Country Status (4)

Country Link
DE (1) DE2129676A1 (https=)
FR (1) FR2095258B1 (https=)
GB (2) GB1362512A (https=)
NL (1) NL7108101A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19643143A1 (de) * 1996-10-18 1998-04-23 Inventa Ag Haftvermittler für Polyamid-Verbunde

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1086607A (en) * 1965-06-03 1967-10-11 Ncr Co Method of electrically isolating components in solid-state electronic circuits
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19643143A1 (de) * 1996-10-18 1998-04-23 Inventa Ag Haftvermittler für Polyamid-Verbunde
DE19643143C2 (de) * 1996-10-18 2002-06-20 Inventa Ag Haftvermittler für Polyamid-Verbunde, Verfahren zu deren Herstellung sowie deren Verwendung

Also Published As

Publication number Publication date
FR2095258B1 (https=) 1977-04-22
GB1362512A (en) 1974-08-07
FR2095258A1 (https=) 1972-02-11
GB1360996A (en) 1974-07-24
NL7108101A (https=) 1971-12-17

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