DE19882853T1 - Verfahren und Einrichtungen zum automatischen Korrigieren von in einem Speichersubsystem erfaßten Fehlern - Google Patents

Verfahren und Einrichtungen zum automatischen Korrigieren von in einem Speichersubsystem erfaßten Fehlern

Info

Publication number
DE19882853T1
DE19882853T1 DE19882853T DE19882853T DE19882853T1 DE 19882853 T1 DE19882853 T1 DE 19882853T1 DE 19882853 T DE19882853 T DE 19882853T DE 19882853 T DE19882853 T DE 19882853T DE 19882853 T1 DE19882853 T1 DE 19882853T1
Authority
DE
Germany
Prior art keywords
methods
devices
storage subsystem
correcting errors
automatically correcting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19882853T
Other languages
English (en)
Other versions
DE19882853B3 (de
Inventor
Vincent Von Bokern
Zohar Bogin
David Freker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19882853T1 publication Critical patent/DE19882853T1/de
Application granted granted Critical
Publication of DE19882853B3 publication Critical patent/DE19882853B3/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
DE19882853.5T 1997-11-26 1998-10-22 Verfahren und Steuereinrichtung zum automatischen Korrigieren von in einem Speichersubsystem erfassten Fehlern und Computersystem, das eine solche Steuereinrichtung aufweist Expired - Fee Related DE19882853B3 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/978,807 1997-11-26
US08/978,807 US5987628A (en) 1997-11-26 1997-11-26 Method and apparatus for automatically correcting errors detected in a memory subsystem
PCT/US1998/022417 WO1999027449A1 (en) 1997-11-26 1998-10-22 Method and apparatus for automatically correcting errors detected in a memory subsystem

Publications (2)

Publication Number Publication Date
DE19882853T1 true DE19882853T1 (de) 2001-06-21
DE19882853B3 DE19882853B3 (de) 2014-02-20

Family

ID=25526405

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19882853.5T Expired - Fee Related DE19882853B3 (de) 1997-11-26 1998-10-22 Verfahren und Steuereinrichtung zum automatischen Korrigieren von in einem Speichersubsystem erfassten Fehlern und Computersystem, das eine solche Steuereinrichtung aufweist

Country Status (5)

Country Link
US (1) US5987628A (de)
AU (1) AU1273999A (de)
DE (1) DE19882853B3 (de)
TW (1) TW413755B (de)
WO (1) WO1999027449A1 (de)

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DE102004059392A1 (de) * 2004-12-09 2006-06-14 Infineon Technologies Ag Verfahren zur Neubelegung eines Speichers eines Subsystems und Subsystem
DE102007047150A1 (de) * 2006-12-28 2008-07-03 Mitsubishi Electric Corp. Elektroniksteuerung

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US7590750B2 (en) * 2004-09-10 2009-09-15 Microsoft Corporation Systems and methods for multimedia remoting over terminal server connections
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US9459960B2 (en) * 2005-06-03 2016-10-04 Rambus Inc. Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004059392A1 (de) * 2004-12-09 2006-06-14 Infineon Technologies Ag Verfahren zur Neubelegung eines Speichers eines Subsystems und Subsystem
US7475212B2 (en) 2004-12-09 2009-01-06 Infineon Technologies Ag Method for reallocation of a memory of a subsystem, and subsystem
DE102004059392B4 (de) * 2004-12-09 2015-09-10 Infineon Technologies Ag Verfahren zur Neubelegung eines Befehlsspeichers, Subsystem zur Durchführung eines derartigen Verfahrens, sowie Mikrokontroller
DE102007047150A1 (de) * 2006-12-28 2008-07-03 Mitsubishi Electric Corp. Elektroniksteuerung
DE102007063638B4 (de) * 2006-12-28 2014-09-25 Mitsubishi Electric Corp. Elektroniksteuerung
DE102007047150B4 (de) * 2006-12-28 2016-10-06 Mitsubishi Electric Corp. Elektroniksteuerung

Also Published As

Publication number Publication date
DE19882853B3 (de) 2014-02-20
US5987628A (en) 1999-11-16
WO1999027449A1 (en) 1999-06-03
AU1273999A (en) 1999-06-15
TW413755B (en) 2000-12-01

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: G11C 29/00

R016 Response to examination communication
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R020 Patent grant now final
R020 Patent grant now final

Effective date: 20141121

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee