DE19728183B4 - Manufacturing method of conductive wires of a chip-size semiconductor package - Google Patents
Manufacturing method of conductive wires of a chip-size semiconductor package Download PDFInfo
- Publication number
- DE19728183B4 DE19728183B4 DE19728183A DE19728183A DE19728183B4 DE 19728183 B4 DE19728183 B4 DE 19728183B4 DE 19728183 A DE19728183 A DE 19728183A DE 19728183 A DE19728183 A DE 19728183A DE 19728183 B4 DE19728183 B4 DE 19728183B4
- Authority
- DE
- Germany
- Prior art keywords
- conductive wires
- conductive
- electrolyzer
- electrode
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45644—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45655—Nickel (Ni) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48647—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
Herstellungsverfahren
für leitende Drähte eines
Halbleitergehäuses
in Chipgröße oder
eines CSP, das umfaßt:
Bonden
leitender Drähte
(45) auf Bondinseln (43), die auf einer oberen Oberfläche eines
Halbleiterchips (41) geformt sind;
Einbringen des Halbleiterchips
(41) mit den so gebondeten leitenden Drähten (45) in einen Elektrolyseur
(55), der eine Elektrolytlösung
(50) enthält,
auf eine Art und Weise, daß ein
Ende jedes der leitenden Drähte
(45) außerhalb
der Elektrolytlösung
(50) liegt;
Anbringen einer Galvanisierelektrode (60) an einer
Innenwand des Elektrolyseurs (55), wobei die Galvanisierungselektrode
(60) vollständig
in die Elektrolytlösung
(50) eingetaucht ist;
Anbringen einer leitenden Platte (65),
die als gemeinsame Elektrode dient, an dem freiliegenden einen Ende
jedes der leitenden Drähte
(45); und
Verbinden der leitenden Platte (65) und der Außenwand des
Elektrolyseurs (55) mit einer elektrischen Stromquelle (70) zur
Durchführung
einer Galvanisierung auf der Oberfläche der leitenden Drähte (45).A conductive wire manufacturing method of a chip-size semiconductor package or a CSP, comprising:
Bonding conductive wires (45) to bonding pads (43) formed on an upper surface of a semiconductor chip (41);
Inserting the semiconductor chip (41) with the conductive wires (45) thus bonded into an electrolyzer (55) containing an electrolytic solution (50) in a manner such that one end of each of the conductive wires (45) is external to the electrolytic solution (50) 50);
Attaching a plating electrode (60) to an inner wall of the electrolyzer (55), wherein the plating electrode (60) is completely immersed in the electrolytic solution (50);
Attaching a conductive plate (65) serving as a common electrode to the exposed one end of each of the conductive wires (45); and
Bonding the conductive plate (65) and the outer wall of the electrolyzer (55) to an electrical power source (70) for performing electroplating on the surface of the conductive wires (45).
Description
HINTERGRUND DER ERFINDUNGBACKGROUND OF THE INVENTION
1. Bereich der Erfindung1. Field of the invention
Die vorliegende Erfindung betrifft ein Herstellungsverfahren für leitende Drähte eines Halbleitergehäuses in Chipgröße (im Folgenden als CSP bezeichnet) und besonders ein verbessertes Herstellungsverfahren für leitende Drähte eines CSP, bei dem leitende Drähte direkt auf Bondinseln, die auf einem Halbleiterchip geformt sind, gebondet werden.The The present invention relates to a manufacturing method for conductive wires a semiconductor package in chip size (hereafter referred to as CSP) and especially an improved manufacturing process for senior wires a CSP, where conductive wires directly on bonding pads formed on a semiconductor chip, be bonded.
Das
Herstellungsverfahren für
CSP nach dem Stand der Technik wird nun mit Bezug auf
Als
erstes wird, wie in
Das
in Zusammenhang mit den
Das
herkömmliche
Herstellungsverfahren für CSP
erfordert ungünstigerweise
einen sehr schwierigen und kostspieligen Prozeß wie Sputtern, Aufbringen
von Fotolack und Ätzen,
um die Stärke
des leitenden Drahts (
ZUSAMMENFASSUNG DER ERFINDUNGSUMMARY THE INVENTION
Es ist folglich ein Ziel der vorliegenden Erfindung, durch Verbessern eines Beschichtungsverfahrens eines leitenden Drahts des CSP ein einfacheres und kostengünstigeres Herstellungsverfahren für leitende Drähte eines Halbleitergehäuses in Chipgröße (CSP) bereitzustellen.It is therefore an object of the present invention, by improving a method of coating a conductive wire of the CSP simpler and cheaper Manufacturing process for conductive wires a semiconductor package in chip size (CSP) provide.
Um das obige Ziel zu erreichen, wird ein verbessertes Herstellungsverfahren für leitende Drähte eines CSP bereitgestellt, das enthält: Bonden leitender Drähte auf Bondinseln, die auf der oberen Oberfläche eines Halbleiterchips geformt sind, Einbringen der gesamten Struktur in einen Elektrolyseur, der eine Elektrolytlösung enthält, auf eine Art und Weise, daß ein Ende jedes leitenden Drahts außerhalb der Elektrolytlösung liegt, Anbringen einer Galvanisierelektrode an der inneren Wand des Elektrolyseurs, wobei die Galvanisierungselektrode vollständig in die Elektrolytlösung eingetaucht ist, Anbringen ei ner leitenden Platte, die dem freigelegten einen Ende jedes leitenden Drahts als gemeinsame Elektrode dient, und Verbinden der leitenden Platte und der Außenwand des Elektrolyseurs mit einer Stromquelle zur Durchführung einer Galvanisierung auf der Oberfläche der leitenden Drähte.Around Achieving the above object will be an improved manufacturing process for senior Wires one CSP provided that includes: Bonding of conductive wires on bond pads formed on the top surface of a semiconductor chip are, introducing the entire structure into an electrolyzer, the one electrolyte solution contains in a way that one End of each wire outside the electrolyte solution attaching a plating electrode to the inner wall the electrolyzer, wherein the electroplating electrode completely in the electrolyte solution immersed, attaching a conductive plate to the exposed one one end of each conductive wire serves as a common electrode, and Connecting the conductive plate and the outer wall of the electrolyzer with a power source for carrying a galvanization on the surface of the conductive wires.
KURZE BESCHREIBUNG DER ZEICHNUNGENSHORT DESCRIPTION THE DRAWINGS
Die vorliegende Erfindung wird aus der unten gegebenen ausführlichen Beschreibung und den beigefügten Zeichnungen, die nur der Darstellung dienen und somit die vorliegende Erfindung nicht beschränken, besser verständlich.The The present invention will become apparent from the detailed below Description and attached Drawings, which serve only the representation and thus the present one Not limit the invention better understandable.
AUSFÜHRLICHE BESCHREIBUNG DER ERFINDUNGDETAILED DESCRIPTION OF THE INVENTION
Das Herstellungsverfahren für leitende Drähte eines Halbleitergehäuses in Chipgröße (CSP) gemäß der vorliegenden Erfindung wird nun mit Bezug auf die beigefügten Zeichnungen ausführlich beschrieben.The Manufacturing process for conductive wires a semiconductor package in chip size (CSP) according to the present The invention will now be described in detail with reference to the accompanying drawings.
Zuerst
werden, wie in
Dann
wird der sich ergebende Halbleiterchip (
Dann
wird, wie in
Dann
wird, wie in
Als
nächstes
werden, wie in
Wie oben ausführlich beschrieben, kann gemäß dem Herstellungsverfahren für CSP gemäß der vorliegenden Erfindung durch Durchführung einer Galvanisierung auf der Oberfläche des Leiters unter Verwendung eines einfachen Systems aus Elektrolyseur, im Elektrolyseur enthaltener Elektrolytlösung und einer Elektrode, ein einfacherer und kostengünstigerer Galvanisierprozeß verwirklicht werden, um eine gewünschte CSP-Herstellung zu erhalten.As above in detail described according to the manufacturing process for CSP according to the present Invention by implementation a galvanization on the surface of the conductor using a simple system of electrolyzer, contained in the electrolyser Electrolytic solution and an electrode, a simpler and cheaper electroplating process realized be to a desired one CSP production to obtain.
Obwohl die bevorzugten Ausführungsformen der vorliegenden Erfindung zum Zweck der Darstellung beschrieben wurden, werden Fachleute erkennen, daß verschiedene Modifikationen, Zusätze und Ersetzungen möglich sind, ohne vom Bereich und vom Geist der Erfindung abzuweichen, wie sie in den beigefügten Ansprüchen dargestellt ist.Even though the preferred embodiments of have been described for purposes of illustration, Professionals will recognize that different Modifications, accessories and substitutions possible are without departing from the scope and spirit of the invention, as they are in the attached claims is shown.
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960075052A KR100214545B1 (en) | 1996-12-28 | 1996-12-28 | Making method of chip size semicomductor package |
KR75052/96 | 1996-12-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19728183A1 DE19728183A1 (en) | 1998-07-02 |
DE19728183B4 true DE19728183B4 (en) | 2007-03-01 |
Family
ID=19491764
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19728183A Expired - Fee Related DE19728183B4 (en) | 1996-12-28 | 1997-07-02 | Manufacturing method of conductive wires of a chip-size semiconductor package |
Country Status (4)
Country | Link |
---|---|
US (1) | US5863816A (en) |
JP (1) | JP2873954B2 (en) |
KR (1) | KR100214545B1 (en) |
DE (1) | DE19728183B4 (en) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG75841A1 (en) | 1998-05-02 | 2000-10-24 | Eriston Invest Pte Ltd | Flip chip assembly with via interconnection |
US6406939B1 (en) | 1998-05-02 | 2002-06-18 | Charles W. C. Lin | Flip chip assembly with via interconnection |
SG82590A1 (en) | 1998-12-17 | 2001-08-21 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with strips and via-fill |
TW522536B (en) | 1998-12-17 | 2003-03-01 | Wen-Chiang Lin | Bumpless flip chip assembly with strips-in-via and plating |
SG82591A1 (en) | 1998-12-17 | 2001-08-21 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with solder via |
US6322903B1 (en) | 1999-12-06 | 2001-11-27 | Tru-Si Technologies, Inc. | Package of integrated circuits and vertical integration |
KR100338945B1 (en) * | 1999-12-13 | 2002-05-31 | 박종섭 | Wafer scale package and the manufacturing method |
KR20010068590A (en) * | 2000-01-07 | 2001-07-23 | 이수남 | Wafer level package |
US6350633B1 (en) | 2000-08-22 | 2002-02-26 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint |
US6402970B1 (en) | 2000-08-22 | 2002-06-11 | Charles W. C. Lin | Method of making a support circuit for a semiconductor chip assembly |
US6562657B1 (en) | 2000-08-22 | 2003-05-13 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
US6551861B1 (en) | 2000-08-22 | 2003-04-22 | Charles W. C. Lin | Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive |
US6660626B1 (en) | 2000-08-22 | 2003-12-09 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
US6403460B1 (en) | 2000-08-22 | 2002-06-11 | Charles W. C. Lin | Method of making a semiconductor chip assembly |
US6436734B1 (en) | 2000-08-22 | 2002-08-20 | Charles W. C. Lin | Method of making a support circuit for a semiconductor chip assembly |
US6562709B1 (en) | 2000-08-22 | 2003-05-13 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint |
US6511865B1 (en) | 2000-09-20 | 2003-01-28 | Charles W. C. Lin | Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly |
US6350386B1 (en) | 2000-09-20 | 2002-02-26 | Charles W. C. Lin | Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly |
US6350632B1 (en) | 2000-09-20 | 2002-02-26 | Charles W. C. Lin | Semiconductor chip assembly with ball bond connection joint |
US6544813B1 (en) | 2000-10-02 | 2003-04-08 | Charles W. C. Lin | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment |
US6448108B1 (en) | 2000-10-02 | 2002-09-10 | Charles W. C. Lin | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment |
US6576493B1 (en) | 2000-10-13 | 2003-06-10 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps |
US6492252B1 (en) | 2000-10-13 | 2002-12-10 | Bridge Semiconductor Corporation | Method of connecting a bumped conductive trace to a semiconductor chip |
US6537851B1 (en) | 2000-10-13 | 2003-03-25 | Bridge Semiconductor Corporation | Method of connecting a bumped compliant conductive trace to a semiconductor chip |
US6667229B1 (en) | 2000-10-13 | 2003-12-23 | Bridge Semiconductor Corporation | Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip |
US7414319B2 (en) * | 2000-10-13 | 2008-08-19 | Bridge Semiconductor Corporation | Semiconductor chip assembly with metal containment wall and solder terminal |
US6673710B1 (en) | 2000-10-13 | 2004-01-06 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip |
US6576539B1 (en) | 2000-10-13 | 2003-06-10 | Charles W.C. Lin | Semiconductor chip assembly with interlocked conductive trace |
US6699780B1 (en) | 2000-10-13 | 2004-03-02 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching |
US6440835B1 (en) | 2000-10-13 | 2002-08-27 | Charles W. C. Lin | Method of connecting a conductive trace to a semiconductor chip |
US6740576B1 (en) | 2000-10-13 | 2004-05-25 | Bridge Semiconductor Corporation | Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly |
US6548393B1 (en) | 2000-10-13 | 2003-04-15 | Charles W. C. Lin | Semiconductor chip assembly with hardened connection joint |
US6444489B1 (en) | 2000-12-15 | 2002-09-03 | Charles W. C. Lin | Semiconductor chip assembly with bumped molded substrate |
US6653170B1 (en) | 2001-02-06 | 2003-11-25 | Charles W. C. Lin | Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit |
US7993983B1 (en) | 2003-11-17 | 2011-08-09 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with chip and encapsulant grinding |
US7538415B1 (en) | 2003-11-20 | 2009-05-26 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal, filler and insulative base |
US7425759B1 (en) | 2003-11-20 | 2008-09-16 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal and filler |
JP4369348B2 (en) * | 2004-11-08 | 2009-11-18 | 新光電気工業株式会社 | Substrate and manufacturing method thereof |
US7750483B1 (en) | 2004-11-10 | 2010-07-06 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal |
US7811863B1 (en) | 2006-10-26 | 2010-10-12 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment |
CN107946201B (en) * | 2017-12-19 | 2020-03-31 | 哈尔滨工业大学 | Preparation method of lead bonding welding spot structure based on local electrodeposition |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5459102A (en) * | 1993-02-19 | 1995-10-17 | Ngk Spark Plug Co., Ltd. | Method of electroplating lead pins of integrated circuit package |
US5476211A (en) * | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
WO1996015459A1 (en) * | 1994-11-15 | 1996-05-23 | Formfactor, Inc. | Mounting spring elements on semiconductor devices, and wafer-level testing methodology |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3901785A (en) * | 1972-05-09 | 1975-08-26 | Antonina Vladimiro Buzhinskaya | Apparatus for producing a metal band |
EP0689241A2 (en) * | 1991-10-17 | 1995-12-27 | Fujitsu Limited | Carrier for carrying semiconductor device |
US5541447A (en) * | 1992-04-22 | 1996-07-30 | Yamaha Corporation | Lead frame |
US5529682A (en) * | 1995-06-26 | 1996-06-25 | Motorola, Inc. | Method for making semiconductor devices having electroplated leads |
-
1996
- 1996-12-28 KR KR1019960075052A patent/KR100214545B1/en not_active IP Right Cessation
-
1997
- 1997-07-02 DE DE19728183A patent/DE19728183B4/en not_active Expired - Fee Related
- 1997-09-25 US US08/937,511 patent/US5863816A/en not_active Expired - Fee Related
- 1997-12-03 JP JP9332916A patent/JP2873954B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5459102A (en) * | 1993-02-19 | 1995-10-17 | Ngk Spark Plug Co., Ltd. | Method of electroplating lead pins of integrated circuit package |
US5476211A (en) * | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
WO1996015459A1 (en) * | 1994-11-15 | 1996-05-23 | Formfactor, Inc. | Mounting spring elements on semiconductor devices, and wafer-level testing methodology |
Also Published As
Publication number | Publication date |
---|---|
KR19980055816A (en) | 1998-09-25 |
JPH10284533A (en) | 1998-10-23 |
JP2873954B2 (en) | 1999-03-24 |
US5863816A (en) | 1999-01-26 |
KR100214545B1 (en) | 1999-08-02 |
DE19728183A1 (en) | 1998-07-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE19728183B4 (en) | Manufacturing method of conductive wires of a chip-size semiconductor package | |
DE60033901T2 (en) | Package for semiconductor device and its manufacturing method | |
DE102005028951B4 (en) | Arrangement for the electrical connection of a semiconductor circuit arrangement with an external contact device | |
DE69133497T2 (en) | Leadframe for a semiconductor device and its manufacturing method | |
DE69632591T2 (en) | FLEXIBLE CONTINUOUS CATHODE CIRCUIT FOR THE ELECTROLYTIC COATING OF C4, TAB MICROBUMP AND CIRCUITS IN THE ULTRAGROSSMASSSTAB | |
DE10148042B4 (en) | Electronic component with a plastic housing and components of a height-structured metallic system carrier and method for their production | |
DE69915299T2 (en) | METHOD FOR TRANSLATING SOLDERING ON AN ARRANGEMENT AND / OR TESTING THE ARRANGEMENT | |
DE4230187B4 (en) | Assembly with memory IC, and method for producing such a unit | |
DE10148120B4 (en) | Electronic components with semiconductor chips and a system carrier with component positions and method for producing a system carrier | |
DE19743767B4 (en) | A method of manufacturing a semiconductor die package having a surface mount semiconductor die and a semiconductor die package having a semiconductor die fabricated therefrom | |
DE69910955T2 (en) | Metal foil with stool contacts, circuit substrate with the metal foil, and semiconductor device with the circuit substrate | |
DE10101948B4 (en) | A method of arranging a semiconductor chip on a substrate and semiconductor device mountable on a substrate | |
DE19745575A1 (en) | Terminal electrode structure with substrate containing several terminal points | |
DE4207198C2 (en) | Lead frame and its use in a semiconductor device | |
DE102006012322A1 (en) | Substrate for an electronic unit and method for its production, electronic unit and method for its production | |
DE10301512A1 (en) | Reduced chip package and process for its manufacture | |
DE10031204A1 (en) | System carrier for semiconductor chips and electronic components and manufacturing method for a system carrier and for electronic components | |
DE4424962A1 (en) | Method for producing a chip contact | |
DE19817128A1 (en) | Conductive base plate for semiconductor component lead frame | |
DE102009044561A1 (en) | A method of manufacturing a semiconductor package using a carrier | |
DE102008064373B4 (en) | Semiconductor arrangement and method for producing a semiconductor device | |
DE4230030A1 (en) | Chip housing with thin inner leads - has reduced vol. of housing body esp. composed of cast epoxide] material | |
DE102019105610A1 (en) | Semiconductor device | |
DE10146353B4 (en) | Method for producing a solder bump and solder bump structure | |
DE2217647B2 (en) | Interconnection arrangement for connecting an integrated circuit and method for its manufacture - US Pat |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee | ||
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |
Effective date: 20110201 |