DE19512745A1 - Cache memory device for storing data - Google Patents

Abstract

In a virtually indexed cache memory with a real label, the colour assigned to a cache input during colour allocation of the virtual and real pages can be altered by assigning colour information to each cache input. This ensures that, after a first unsuccessful cache address operation, a second cache address operation takes place. If there is still no cache hit, a further cache address operation is attempted by colour correction, i.e., by indexing of the cache memory with the aid of, among other things, the real colour. If this cache address operation also fails, a cache miss is registered.

Description

The invention relates to a cache memory device with a cache memory that is indexed virtually and its cache entries with physical (real) Addresses are marked.

Modern processors need cache memory in order to Gap between fast processors and slow ones Main memory to balance.

Real and virtually indexed caches are known. In the real indexed cache ( FIG. 7), the virtual address supplied by the processor is first converted into a real address by the translation lookaside buffer (TLB). Then the cache is addressed with this real address.

In the case of the virtually indexed cache ( FIG. 8), the cache is addressed directly with the virtual address. A conversion to the corresponding real address only takes place in the event of a cache miss. The advantage of a virtually indexed cache is the higher speed, since the conversion step by the TLB is not necessary. Its disadvantage occurs with synonyms or aliasing.

In direct-mapped caches (as shown in FIGS . 7 and 8), a cache index is calculated from the real or virtual address a with the aid of a map function and a row of the cache is thus selected. Then a is compared to the address of the memory area currently associated with that cache cell (the cache entry marker). If there is a match, there is a hit (and the cache line is used instead of the main memory), otherwise a miss.

Mostly (a mod cache size) / line size is used as map- Function used. It doesn't need the full cache permanent virtual address to be stored, son because a / cache size is enough.

Direct-mapped caches are simpler, but they do higher miss rates than n-way caches. These exist principally from n correspondingly smaller direct mapped Cache blocks. This ensures that each main storage element in at most one block located. Because the map function has n cache cells each indexed, up to n elements with map- equivalent addresses in the cache. This n- fold associativity reduces the probability by Clashes and increases the hits accordingly rate.

The cache type favored today is virtually in marked and real (physically) marked. It is the same as fast as a virtually indexed and virtually mar cache, but avoids most of its after  parts, especially problems with multiprocessor systems men, synonyms, sharing and coherence.

A real indexed cache does not have these disadvantages either, but requires a complete address conversion step (virtual → real) of the TLB before the cache access can be initiated. In contrast, a virtually indexed and real marked cache allows ALB and cache access to run in parallel (see FIG. 9). The instruction pipeline of the processor is therefore shorter, so that the latency of an instruction is usually reduced by one clock and the processor line increases accordingly.

The mechanism remains simple as long as that for the Indexing the cache required address bits (i) all in Area of the address offset (address within a screen te). Since this address section through the implementation of the virtual into the real address is not changed, the cache can also do this before the conversion step of the TLB are addressed (indexed). Only at the end of cache access and parallel TLB conversion step checked whether the real associated with the cache entry address (the marking) with the one supplied by the TLB Real address matches. Only those need following the index part (i) higher Bits of the address to be compared because the by (i) indexed cache entry only associated with addresses whose index bits have the value (i). The accordingly only the higher ones need in the cache significant bits as a marker (real address) saves being.

An n-way associative cache of this type can be as small as n × 2 ^p , with 2 ^{p being} the page size. The cache can be enlarged by larger pages or increased associativity.

An interesting technique for cache addressing is page coloring. This describes the method of always creating pages in real memory in such a way that the low-order address bits of the virtual and real page address are identical (see FIG. 10). The virtual page number (vpn) and cache index (i) overlap. The overlapping part is shown in black in FIG. 10. The corresponding part of the virtual address is called virtual color c, the real address is called real color c '. In the case of color-true allocation, ie if virtual and real color match, the size limit n × 2 ^p mentioned above is removed.

If, as shown in Fig. 11, virtual and real color are additionally compared, the marking (real address) does not require the storage of the corresponding color bits and only the higher-order bits (r ') of the real page number are required the mark to be compared.

The invention has for its object a cache storage device with a virtually indexed and to create real marked cache memory that too a fast one for pages that are not color-correct allocated Cache access allowed. Synonyms should be without alignment Restriction may be permitted, although only the Addressing via an address (main address) be quick got to. Access via other addresses (synonyms) is allowed to be slowed down; however, each of the synonymous addresses can be the main address, in particular  the virtual color of the main address of the real color can distinguish.

A cache memory is provided to solve this task direction proposed with the features of claim 1 gene, the features of advantageous developments this cache memory device each in the sub claims are specified.

As already explained above, the so-called called Page Coloring the virtual address space in ver different groups of pages (called "colors") under allocates, allocating virtual pages to real pages is basically true to color. I.e. a red virtual page changes to a red real page pictured. Just like the virtual color in the virtual len address is included, the real color is in the Real address included. The cache according to the invention storage device now solves the problem of a vir current address that leads to a virtual page with a the first color belongs in a cache entry, that to a real page with a different one than that heard first color.

• 1) With cache addressing in the case of the invent The cache memory according to the invention is initially by means of the cache index part of the virtual addresses se and their group information (virtual color), which represent part of the virtual page number tating page number address part is indexed and thus per way (the cache memory can be neither be one-way or multi-way associative) Addressed cache entry. Per addressed cache The entry will then mark the match with the remaining real address part of the real pages  number of the real address, which results from the virtual Address has been implemented (for example done by a TLB). Per way of So there is a marker memory in the cache same. Exists per path of the cache memory but also a group information comparator that the group information of the real address (real Color) with the group information of each way addressed cache entry compares. Furthermore Each cache entry has a status flag on. If this status flag is set, act the cache entry is a main on lazy while the flag is not set about the group information of this cache entry to a main entry. Vote for an addressed cache entry with the rest of the real address and the group information tion with the group information of the real pages number of the real address and is additional if the status flag is set, there is a cache hit before, with which the cache addressing is ended and Data in the specified by the marking Write data field of the relevant cache entry cash or can be read from it. In this case So you came across a main entry.
• 2) On the other hand, it is correct for one of the addressed cache Entries are marked with the rest real address part matches, however, is the state flag not set and also applies that the virtual Group information (group information of the vir current address) is the same as the real group information tion (group information of the real address) is so there is color-accurate access to a reference Entry of the cache memory before, the Grup  peninformation of this reference entry to the Main entry points. To add to this main entry of the cache memory, the cache Memory indexed again using the Cache index part of the virtual address and Group information of the reference entry. To Ab group information can be saved per Certain bit positions are provided in the cache entry the; alternatively, it is also possible to use the Store group information in the data field itself, since this data field in the case where the be matching cache entry is a reference entry is not needed for writing or reading. After this cache re-indexing will be like the addressed cache entries match matching your markings with the rest real address part and on correspondence of the real group peninformation with the group information of addressed cache entries compared. In each Case exists among the now addressed cache Entries one that set a state flag and its marking with the rest real address part and its group information with the real group information matches. In order to there is a cache hit.
• 3) Has no cache hit occurred so far and under the virtual group information differs the real group information, so a "color correction "attempted in the cache by means of the cache index part of the virtual addresses se and the group information of the real address (Real color) and those addressed in this way Cache entries matching their markie with the rest of the real address part and over  agreeing your group information with the Group information of the real address examined. After that, according to the above mechanism proceed (see above from 1) and if necessary with 2)). If even this cache access does not become a cache hit addressing is canceled altogether and signals a cache miss.

By means of the cache memory device according to the invention the cache memory can be dynamically adjusted, what the coloring of the virtual and real pages or concerns the color allocation. As a result of this dynamic Adaptation are different cache entries of a ge common real page under different "colors" (group information) can be addressed quickly and always about a single color, but freely selectable and ins is particularly customizable.

An execution is based on the drawing example of the invention explained in more detail. In detail demonstrate:

Fig. 1 shows the preparation step for a Falschfar ben cache according to the invention,

Fig. 2 shows the accessing step to the false-color cache,

Fig. 3 shows the detour / reference step of Falschfar ben cache,

Fig. 4 shows the color correction step,

Fig. 5 shows the general color correction step in a cache memory,

Fig. 6 shows the access step and color corrected to handle step in a cache memory,

Fig. 7 shows the structure of a real-indexed cache memory,

Fig. 8 shows the construction of a virtually indexed and vir TULLE labeled cache memory,

Fig. 9 shows the construction of a virtually indexed and physically tagged cache memory,

Fig. 10 shows the structure of a system based on color fidelity allocation cache memory and

Fig. 11 shows the step of testing for color fidelity in a cache memory of Fig. 10.

The following terms apply to the following description drawings (see also the figures):

v virtual address
vpn virtual page number
c virtual color
rpn real page number
real color
higher part of rpn (without)
Index color
least significant part of the cache entry number

Each cache entry (line) contains a field r _i and c _i , a 1-bit field main _i , a data field d _i and other status fields not listed.

A current cache line is indicated by an In dex i selected, its more significant bits as an index color. Virtual, real and index color each have the same number of bits.

A distinction is made between main entries and reference entries in the cache. In the case of main entries (identified by a set main _i ), d _i contains the current data, c _i the real color and r _i the higher-order part of the real address of the data assigned to the cache entry. Main entries are quickly addressed via the virtual main address mentioned above. In contrast, reference entries (marked by _i ) do not hold any data, but in c _i a reference to the associated main entry, namely its index color. However, r _i also contains the higher-order part of the real address for assigned data for reference entries.

Regardless of this, color fidelity and false color on lazily differentiated. Correct for color-true entries Index and real color match, for false color entries not enough.

There are color-true main entries, false color main entries lazy and color-accurate reference entries. False color ver wise entries do not occur.

The following invariants apply:

• 1. If the cache contains a color-accurate reference entry, it also contains the corresponding false color Main entry, at the point at which ver will be shown.  
• 2. There are exact details for each false color main entry a color-accurate reference entry that ver points.

Referring to Figs. 1 to 4 which will be described below Adressie tion of a direct-mapped cache.

• 1. At the beginning of a cache access, the index port (,) is loaded from the virtual address (see Fig. 1). At the same time, the TLB starts address conversion with vpn as input.
• 2. The cache entry addressed by (,) is read out. c _i is compared with and r _i with ( FIG. 2). If it is a main entry, ie main _{i is} set, and both comparisons result in equality, it is a cache hit, i.e. the cache data is accepted (read access) or the new data is written to the cache (write access ). This ends the cache access.
• 3. If a color-accurate reference entry was read out in step 2. ie _i , and the higher-order parts of the real address match the marking (r _i =) and the access is true to color (index color = real color, =), then the read c _{i is used for} loading ( FIG. 3). Then step 2 is carried out again (redirection step). (Variant (a) or in the event that not only the reference index but also the reference path, for example, is stored in the data field - only with direct-mapped cache -: In this redirection step, no checks (from real address, color and for main entry Variant (b): The reference is not read from c _i but d _i .)
• 4. If a main entry was read out in step 2, ie main _i , but the real address is incorrect (r _i ≠ or c _i ≠) and it is a false color access (≠), then a color correction is attempted ( Fig. 4) : is loaded with the real color and step 2 is carried out again.
• 5. In any other case, cache access is denied broken and signaled miss.

The above process can be transferred to a multi-way associative (n-way associative) cache accordingly. With n-way associative cache, n entries are selected at the same time. The individual entries are distinguished in the following description by the additional index j, z. B. c _{i, j} .

The following are the requirements to the left of → for the operations described on the right guided. To select an alternative, everyone must do so listed requirements must be met (logical and link). All operations separated by commas take place in parallel. Sweep (how) be draws the negation of a signal or a bit and "!" (like step2!) setting a signal or one Bits. The resetting of a signal or bit will by "!" applied to the negated signal (like !) written down. D denotes the data bus.

The following then becomes parallel for all j from 1 to n carried out:

In summary, all n blocks are switched:

Here, the completion of the cache handling means. Then there is a hit (hit) or not (). If no alternative is selected, start with closes, the next bar follows the same procedure continued to work.

If the n-way associative cache in the first measure for an entry of a way in the above under B be written step a "hit" is signaled, ge one reaches after the first in diagram A above Step to the position marked with "(*)". On is then closed according to the first line of the Move diagram B and identify it with "(**)" is the cache access (successful) completed. So when you first address the Cache immediately found the main entry.

One comes across when addressing the cache memory for the first time however, to a reference entry (see above under Step 3), you get up to after the first bar  the position marked with "(***)" and then drives for all paths of the cache memory again with the diagram A away. If after addressing the Cache memory according to diagram A above the hit Signal has not yet been set, the Cache access canceled.

If after addressing the cache memory ent speaking of method A above, the hit signal and that Step2 signal are both not set, so if the index color matches the real color that Missed cache access (see those with "(****)" marked place). Votes against Index color and real color do not match, so a Color correction carried out (see "(*****)" in the lower one Row of diagram B). After that, the access runs Start of diagram A again.

For reasons of clarity, only the end read and write entire cache entries. Taking into account low-order address bits, you can naturally by the usual and known method read or wrote only parts of an entry become. Effects on the tax described here Logic of the false color cache does not occur.

There is an expansion of the cache described above in it, also false color reference entries and several Allow reference entries per main entry. At least one of the reference entries then holds a list of all related entries in its data field (the not required for data in a reference entry becomes).  

Alternatively or additionally, a reference entry can also be made contain the data so that it can be read directly without Redirection step can be delivered. At Write access must then either be the other Entry also updated or its data field as be marked invalid.

The above page coloring procedure for cache addressing should of course also work if the allocation is not perfectly true to color. Invention is in the event that the first cache access by means of cache index part and group information of the virtual address has led to a cache miss and the real color c 'supplied by the TLB differs from the virtual color c, a color-corrected cache Access attempted (see Fig. 5). The new (color-corrected) cache indexing takes place by means of the cache index part of the virtual address and the group information assigned to the real address. Incorrectly colored pages can therefore be used, but require an additional step in cache access (see FIG. 6).

Under certain circumstances, an Allo is not true to color cation absolutely necessary, e.g. B. if two virtual Pages of different colors on the same real page must be mapped. With that, it can keep going not color-accurate page allocations come from the Cache memory need to be processed.

According to a first variant, the cache Addressing first using the cache index part and the group information of the virtual address of the Cache memory indexed and per way of cache Memory addressed a cache entry. The marking  against all now addressed cache entries to examine for correspondence with the rest real address part of the real page number from the virtual len address converted real address read out. Further the group information of the virtual address the group information of the real address is compared. are these two group information the same, so examines which of the marks of the addressed Cache entries with the remaining real address part from the virtual address converted real address true, whereby for the cache entry with the rest- Real address part matching mark a cache Hit is present, so that the cache addressing is finished and data in the data field of this cache entry are writable or readable from this. Exists no addressed cache entry with one with the remaining Realadressteil matching marking, so the Cache addressing ended and there is a cache miss in front. However, the two groups differ formations of each other (what with the comparison above is determined), the cache memory is indi adorned, namely by means of the cache index part of the vir current address and the group information of the Real address. Now it is examined which of the markings of the now addressed cache entries with the remaining Real address part of the from the virtual address set real address matches, whereby for the cache Match entry with the rest of the real address part there is a cache hit in the marker so that the Cache addressing is finished and data in the data field of this cache entry is writable or from this are readable. However, none exists now Cache entry with a marker that matches the remaining Realadressteil matches, so the cache address ended and there is a cache miss.  

In the second alternative of cache access with the Possibility of color-corrected cache indexing first the cache address (without color correction) by means of the cache index part and the group information mation of the virtual address tried, being per way a cache entry is addressed in the cache memory. The markings of all now addressed cache Entries are used to check for match with the remaining real address part of the real page number of real address converted from the virtual address read. Furthermore, the group information is all now addressed cache entries for examination according to the group information from real address converted from the virtual address read. Then it is examined which of the addressed Cache entries one with the rest of the real address part of the rea len page number from the virtual address set real address matching mark and a matches the group information of the real address has group information, for this Cache entry there is a cache hit so that the cache Addressing is finished and data in the data field of this cache entry writable or from this are readable. If there is no cache entry, its marking with the remaining real address part and its Group information with the group information of the real If the address matches, the group information the virtual address with the group information of the Real address compared. Both groups agree information matches, so is the cache addressing ended and there is a cache miss. Differentiate however, the two group information differ from each other, so the cache is indexed again by means of the cache index part of the virtual address and the group information of the real address. The marking  gen and the group information of all addresses now cached entries are used for examination Agreement with the remaining real address part or Group information of the real address read out. After that it is again examined which of the addressed Cache entries one with the rest of the real address part of the rea len page number from the virtual address set real address matching mark and a matches the group information of the real address has group information, for this Cache entry there is a cache hit so that the cache Addressing is finished and data in the data field of this cache entry is writable or from this are legible. If there is no cache entry, its marking with the remaining real address part and its Group information with the group information of the real address matches, so the cache addressing ended and there is a cache miss.

Claims (4)

1. cache memory device for storing data, with

• - A one-way or multi-way associative cache, which can be indicated by a virtual address which comprises a cache index part and a virtual page number representing page number address part with group information indicating one of several groups which belongs to the virtual page represented by the page number address part of the virtual address,
  • - Wherein the virtual address can be converted into a real address, which has a real page number representing page number address part, which comprises a group information and a remaining real address part, the group information indicating one of several groups to which the by the page number -Address part of the real address belongs to the real page,
  • and the cache memory has a plurality of cache entries which can be indexed by the cache index part and the group information of the virtual address, each of which comprises at least one marker, group information, a settable and resettable status flag and at least one data field,
• - where cache addressing is attempted according to the following steps:
  • a) the cache memory is indexed by means of the cache index part and the group information of the virtual address, one cache entry being addressed per path of the cache memory,
  • b) the markings of all now addressed cache entries are read out for examination for correspondence with the remaining real address part of the real page number of the real address converted from the virtual address,
  • c) the group information of all now addressed cache entries are read out for examination for agreement with the group information of the real address converted from the virtual address,
  • d) it is examined which of the cache entries read in steps b) and c) has a set status flag,
  • e) If there is a cache entry in step d), the status flag of which is set and the marking of which corresponds to the remaining real address part of the real address and the group information of which corresponds to the group information of the real address, then there is a cache hit and the cache addressing has ended , data in the data field of the cache entry concerned being writable or readable therefrom, otherwise
  • f) it is examined whether the group information of the virtual address is equal to the group information of the real address and whether one of the addressed cache entries has a marking which corresponds to the remaining real address part of the real page number and an unset status flag,
  • g) if the conditions in step f) are given for a cache entry, the cache memory is indexed by means of the cache index part and the group information of this cache entry, one cache entry being addressed per path of the cache memory , and steps b), c) and d) are carried out,
  • h) for those of the now addressed cache entries whose status flag is set and whose marking matches the rest of the real address part of the real address and whose group information matches the group information of the real address, there is a cache hit, and the cache addressing ends and data can be written to or read from the data field of the cache entry in question,
  • i) if at least one of the conditions in step f) does not exist, then a check is made as to whether the group information of the virtual address is different from the group information of the real address,
  • j) if the condition in step i) is given, the cache is indexed by means of the cache index part and the group information of the real address, one cache entry being addressed per path of the cache, and the steps become b) to h), the cache addressing having ended and a cache miss present, if step f) is carried out and at least one of the conditions of step f) is not met,
  • k) If the condition in step i) is not met or if there is no cache hit in step h), the cache addressing is ended and there is a cache miss.

2. Cache memory device according to claim 1, characterized characterized in that with a direct-mapped cache Memory with a single path in step h) the Examination of the state flag, the marking and the group information of the single address th cache entry was not made and for this only addressed cache entry a cache hit is present. 3. cache storage device for storing data, with

• - A one-way or multi-way associative cache, which can be indicated by a virtual address which comprises a cache index part and a virtual page number representing page number address part with group information indicating one of several groups which belongs to the virtual page represented by the page number address part of the virtual address,
  • - Wherein the virtual address can be converted into a real address, which has a real page number representing page number address part, which comprises a group information and a remaining real address part, the group information indicating one of several groups to which the by the page number -Address part of the real address belongs to the real page,
  • the cache memory has a plurality of cache entries which can be indexed by the cache index part and group information of the virtual address, each of which comprises at least one marker and at least one data field,
• - where cache addressing is attempted according to the following steps:
  • a) the cache memory is indexed by means of the cache index part and the group information of the virtual address, one cache entry being addressed per path of the cache memory,
  • b) the markings of all now addressed cache entries are read out for examination for correspondence with the remaining real address part of the real page number of the real address converted from the virtual address,
  • c) the group information of the virtual address is compared with the group information of the real address,
  • d) in step c) both group information are identical, it is examined which of the markings of the addressed cache entries corresponds to the remaining real address part of the real address converted from the virtual address, whereby for the cache entry with the remaining There is a cache hit in the real address part of the corresponding marking, so that the cache addressing is ended and data can be written to or read from the data field of this cache entry,
  • e) if there is no match in step d), the cache addressing is ended and there is a cache miss,
  • f) in step c) the two group information differ from one another, the cache memory is indexed, specifically by means of the cache index part of the virtual address and the group information of the real address,
  • g) it is examined which of the markings of the addressed cache entries matches the remaining real address part of the real address converted from the virtual address, with a cache hit being present for the cache entry with the marking matching the remaining real address part, so that the cache addressing has ended and data can be written to or read from the data field of this cache entry,
  • h) there is again no agreement in step g), the cache addressing is ended and there is a cache miss.

4. cache storage device for storing data, with

• - A one-way or multi-way associative cache, which can be indicated by a virtual address which comprises a cache index part and a virtual page number representing page number address part with group information indicating one of several groups which belongs to the virtual page represented by the page number address part of the virtual address,
  • - Wherein the virtual address can be converted into a real address, which has a real page number representing page number address part, which comprises a group information and a remaining real address part, the group information indicating one of several groups to which the by the page number -Address part of the real address belongs to the real page,
  • the cache memory has a plurality of cache entries which can be indexed by the cache index part and group information of the virtual address, each of which comprises at least one marker, group information and at least one data field,
• - where cache addressing is attempted according to the following steps:
  • a) the cache memory is indexed by means of the cache index part and the group information of the virtual address, one cache entry being addressed per path of the cache memory,
  • b) the markings of all now addressed cache entries are read out for examination for correspondence with the remaining real address part of the real page number of the real address converted from the virtual address,
  • c) the group information of all now addressed cache entries are read out for the examination for agreement with the group information of the real address converted from the virtual address,
  • d) it is examined which of the addressed cache entries has a marking which corresponds to the remaining real address part of the real page number of the real address converted from the virtual address and has group information which corresponds to the group information of the real address, with a for this cache entry There is a cache hit, so that the cache addressing has ended and data can be written to or read from the data field of this cache entry,
  • e) if there is no match in step d), the group information of the virtual address is compared with the group information of the real address,
  • f) if the two group information match, the cache addressing is ended and there is a cache miss,
  • g) if the two group information differ from one another, the cache memory is indexed again, specifically by means of the cache index part of the virtual address and the group information of the real address,
  • h) a step d) is carried out for the cache memory indexed according to step g),
  • i) if there is again no match in step d) carried out according to step h), the cache addressing is ended and there is a cache miss.