DE1774158A1 - Circuit arrangement for finding information in which the access time depends on the frequency of use - Google Patents

Description

Dipl.-Ing. Heinz Ciaessen I 7 74 I Oo

Patent attorney

7 Stuttgart-Feuerbach

Short street 8

loE / Reg. 5879
JMRobins -1

INTERNATIONAL Sl ¹ MDARD ELECTRIC CORPOiLTION, NEW YORIi

Circuit arrangement for finding information, where the access time depends on the frequency of use

The priority of application no. 19773/67 of April 28, 1967 in the UK is claimed.

The invention relates to a circuit arrangement for finding information, in which the access time depends on the frequency of use depends, with memories working sequentially according to the search principle, each one register for the search address and a comparison / output device which determines the location of the address that matches the search address and outputs the associated information.

Both motorized and static memories are known from the technology of digital information storage those looking for the desired information not on the basis of a location, but on the basis of a certain meaning he follows. In the case of motorized memories, one speaks of the coordinate method on the one hand and the index method on the other hand. The query is generally carried out serially. Associative memories are also from the prior art known. They work in a similar way to the index procedure described, but the query takes place in parallel Associative memories are relatively complex in terms of their control electronics. Is the total amount of information available very large and only becomes a relatively small one all the time

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If part of the overall information is required, then the use of an associative or content-addressed memory is uneconomical. The invention provides a more economical solution to the problem mentioned.

The invention is characterized in that at least two memories are provided and that when interrogating the first memory is activated first and that the second memory is activated only when the search address is not contained in it and that the second memory is activated at each address contains additional memory locations in which the number of queries is stored and that, depending on a specific value of the marking in the additional memory locations, this address is transferred together with the associated information into the first memory and that the first memory is also designed so that each time if an address match is found, the address and the associated information to the front of it in the search direction address and associated information we swapped d ^ J the invention is illustrated by the attached block diagram, for example.

The data pairs to be processed consist of address and Information (e.g. customer name and address or Customer name and account number) are stored individually in the memory cells of a first or main memory MS. It is assumed that this has a ferrite core matrix, each row of which represents a memory cell. Each memory cell contains a data pair consisting of an address and * information. The data pairs that are frequently required by the processing unit are located in this first memory

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There is also another memory 7S- is provided in which Memory cells differ in comparison to the data pairs in the Main memory less used .data pairs..be located.

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ISE / Äeg. 3879 - 3 -

Each memory cell of this second memory has an additional one Section E, which will be explained later.

If the information on a specific address is required, the address is entered in the register ST1 of the first memory, then the addresses of all memory cells in the memory MS are compared with the address in the register ST1 by means of a comparison device AC1, until the address sought is found is. A signal from the comparison device AC1 then opens gate circuits labeled G1. This has the effect that the desired information is output to the assigned processing device, us is read either non-destructively or destructively with rewriting. %

If the searched address is not found after a complete search of the memory MS, the comparison device AE1 emits a disagreement signal which opens the gate circuit G2, whereby the search address located in the register ST1 is passed on to a second register ST2. The search address now in register ST2 is then compared with all addresses, in general the second memory VS, and if the comparison device determines that the address sought is not there either, it generates a signal on the line OP which informs the operator that searches for an address m is neither in MS nor in VS.

The address in register ST2 is made visible to the operator by means of a display device. The operator then looks for the relevant information in a list and feel this to be. The information is output to the processing device and stored in the memory VS. The new data pair is in the first ^ eIIe of the memory VS saved. This means that all data p & are around one

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Position downwards and that the last pair will be deleted. Instead of moving all data pairs, you can also replace the oldest data pair with the new one. ° edesmal _t if a data pair is used in the section E ,, each memory cell is noted that the pair in question has been used "

Each time the information in the memory YS is read, it is then rewritten, with the number im. Section E, which specifies the number of calls, is increased by one. With each reading process, the content of section B is checked by the device k and if this determines that a certain value of the number of use has been exceeded in a given time unit, then it causes the gate circuits G4- and G |? opened herden _$ so that the data pair is transferred to the main memory MS.

For example, if the number of use is 2, then the Section JS of the memory cells and the device M are omitted, since the mere fact that the search address is in VS indicates that this address has been called twice. In this Trap open the gates G4, G5 for the transmission of the data pair from VS to MS simultaneously with the output of the information which is effected by the comparison device AC2. In this case, as in the first-mentioned case, an inspection by the operator can also be provided, for example, whether the information associated with the address is correct.

A data pair that comes from VS to LiS is stored in the main memory MS entered at a certain point. All data pairs behind this position in the search sequence are moved by one position shifted downwards, with the lowest pair; is lost ■ ,. In order to optimize the search process in the LIS memory, i.e. to accelerate it, every time a data

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pair is used, this one with the one in the search order upstream data pairs aar swapped. As a result "move see the frequently used pairs at the beginning and the less used pairs at the end of the search order. The search· always begins at the beginning and the more often an address is used the faster it will be found.

The arrangement according to the invention can also be used for bidirectional operation be interpreted. Operation in one direction · has already been described · When operation in the other direction if the information is known and the associated address is searched for, with the designations address and information to would be swapped.

1 claim
1 sheet of drawing, .1 jig.

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Claims (1)

ISE / Reg. 3879 - 6 - . Claim Circuit arrangement for finding information, in which the access time depends on the frequency of use with memories operating sequentially according to the search principle, each having a register for the search address and a comparison / output device that determines the location of the address that matches the search address and the outputs associated information, characterized in that at least two memories (MS, VS) are provided and that when interrogating, the first memory (MS) is activated first and then, if this does not contain the search address, the second memory (VS) is activated and that the second memory contains additional memory locations (E) at each address, in which the number of interrogations is stored and that, depending on a certain value of the marking in the additional memory locations, this address together with the associated information in a predetermined time first ' is transferred into the / memory and that the first memory is also designed so that every time a Address match was found, this address and the associated information with that in the search direction previous address and the associated information is swapped. Ne / Sd
22.4.68 109837/1314 BATH ORIGINAL.