DE1562010C1 - Method and device for forming key bit sequences - Google Patents

Description

The invention relates to a method and a direction for forming key bit sequences using of random generators, especially for locking and unlocking telex messages, for example by addition mod. 26, 27, 28, 29, 30, 31, 32 using basic and saying key with a quasi-random key bit sequence.

An encryption device has become known (DAS 11 88 123, Swiss Patent 433 437), at which for the formation of check digits one of AND- and OR- Gates formed mixing circuit is used. At the Sem known method must for each key time a key character alphabet is formed. Of the the time required for this is especially for "on line" - Operation unfavorable and disruptive. In addition, the well-known Ver drive the property that for quasi-random formation the key character of the plain text is used where is increased by the key depth, but the Danger of the formation of towed towers that must.  

Teletype encryption is widely used Encryption carried out in such a way that the secret text contains only letters - usually 26. This procedure is common when operating "off line" is encrypted and decrypted, so not at the moment of Transmission.

This is in contrast to the usual Ver and Ent encryption in "on line" mode, whereby entered time immediately encrypted and transmitted and transmitted genes can be decrypted immediately. In this mode it is common for 32-character codes with 5 characters, thus the entire character content of the telegraph alphabet CCITT # 2 to use. In special cases, 31 ver key characters worked excluding the characters combination 32 or combination 4 (for D and "who there?") or even at 30 to the exclusion of both.

It is planned for a universal key device partial to implement an encryption procedure that alternatively switch between 26 and 32 encrypted characters bar and is therefore suitable for all operating modes of the "on line" - and "off line" encryption.

The invention is based, to a method ren of the type mentioned with a minimum of effort to achieve the highest possible cryptological security. The method according to the invention is intended to provide the possibility of a Ease of operation through largely automatic Operating procedure and usability of punched tape for one give basic key, saying key and encryption key Include text.

This is achieved according to the invention by a method which is characterized in that the outputs of a more  number of random generators controlled by another Random generator in quasi-random order with the ons gears of a mixer gate circuit can be linked.

According to a special embodiment of the Ver driving there is a quasi-random mix of the off gears of three or more odd numbers of zu if generators occur bits in such a way that the off gears of these random generators in quasi-random order and quasi-random kind of variety scrambled and with the inputs of a mixer gate circuit are connected, that in this mixer gate circuit of n inputs two each Inputs with the inputs of a common AND gate one of these inputs and another Circuit input (each) with the inputs of a common OR gates are connected and the outputs (each) of two AND and OR gate with the inputs of a half adder mod 2 - if necessary with the interposition of further pairs of AND- and OR gates - are connected and that a common Output of this mixer circuit to generate the key bit Episode serves.

According to a further special embodiment of the fiction According to the method, a quasi-random mixture of the the outputs of four or more even numbers number of randomly generated bits by alternating Selective routing of the bits from the outputs of two random numbers alternators via an AND or an OR gate, alternating Management of the bits occurring at the outputs of these gates via a further AND and an OR gate, respectively if - with more than four random generators - repetition this kind of reshuffling, and the bits in the last Mixing stage subsequent sign multiplication of the the outputs of the AND and OR gates of the penultimate mixer  stage occurring bits or line of these bits on a half adder mod 2 each in quasi-random time Sequence and quasi-random nature of the change to the generation key bit sequence.

The facility to carry out the aforementioned procedures is characterized according to a development of the invention records that the at the binary output of the mixer circuit in such a number of bits occurring bit sequence that in  a memory the binary value in the code frame of the prep correct teletype codes are created, in parallel is fed to a decoder, depending on the club this on one of 26 to 32 decoding outputs occurring bits to the adders mod 26 and 27, respectively. . . 32 for the encryption or decryption is supplied while when a pulse occurs on one or one of several predetermined outputs the mixer circuit is switched, according to a quasi-random Bit sequence of another random generator.

In a device with addition mod 26 last-mentioned type is preferred according to embodiment of the invention on one of 26 predetermined Outputs of the decoder impulse each Adder mod 26 supplied for encryption or decryption, while when a pulse occurs on one of the rest Lichen six outputs switching the mixed circuit is initiated and a further cycle for Control of the adder mod 26 is initiated. Will ever worked with 32, 31 or 30 encrypted characters, the same can be used to switch the mixing circuit Outputs 26 to 32 of the decoder can be used or any other.

According to another development of the invention, one determines at the binary output of an additional random generator  sequence of several bits by their binary value the type of mixture used in the above-mentioned process.

According to another development of the invention are as individual random generators feedback shift registers used, the number of digits depending on different prime numbers correspond, or are relatively prime to each other and where the saying key in the entirety of the shift registers is entered while the basic key is the position of the individual switching means in the feedback circuits certainly.

Further advantageous embodiments of the invention are in the other subclaims described. The invention is described in the following described embodiment explained in more detail. It shows:

Fig. 1, the entire circuit,

Fig. 2 shows a circuit for the basic key feed,

Fig. 3 shows a circuit for the message key feed,

Fig. 4 is a schematic diagram of the mixer gate circuit for bits to be mixed taken from four random generators simultaneously.

For an off line encryption process, in which the encrypted information with 26 letters, usually especially in groups of 5 letters  the following arrangement is intended:

A key procedure is used, which works with a fixed basic key (inner key) for an agreed period of time, and a spell key (outer key) that changes for each spell (crypto telegram). A number of feedback ring shift registers are used in the circuit shown in FIGS. 1 to 3. 4 shift registers RS I to RS IV are provided, of which the register RS I has 13 positions, the register RS II 17 positions, the register RS III 19 positions and the register RS IV 11 positions, that is a total of 60 positions. In it a saying key consisting of 60 bits is fed in via a keyboard Ta or a punched strip reader Le. The circuit according to FIG. 1 can serve this purpose. A bridge changeover switch BU is assigned to each of these shift registers. The basic key is in this bridge switch z. B. fed in as shown in FIG. 2 and used for an agreed period (z. B. 1 day, 1 week or 1 month). The basic key consists of 56 bits, the contacts of the bridge changeover switch being opened or closed according to the binary information formed by these bits, namely 12 in the bridge changeover switch BU I, 16 in the bridge changeover switch BU II, 18 in the bridge changeover switch BU III and 10 in the bridge changeover switch BU IV. For the sake of clarity, only a part of these contacts is drawn. The information can also be entered via the keyboard or the punched tape reader, by means which are not explained in more detail. For the sake of simplicity, these contacts are shown as mechanical, but they can also be electronic. The basic key consists of irreducible polynomials.

The saying key consists of any characters and goes ahead of every encrypted saying. He can use the keyboard can be entered for encryption, but also automatically generated by the key generator. To Ent key of the transmitted saying is the saying enter the key again, be it by hand over the Keyboard or automatically using a received hole streaking. The use of this saying key has to Aim to get a certain starting position from the very long one Period and with a high probability to encrypt each saying with a new starting position.

Serve for the generation of the key bit sequence next the shift registers RS I to RS III. The number the possible spell key results from the total period to (2¹³-1) · (2¹⁷-1) · (2¹⁹-1) ≅5.5 · 10¹⁴.

Since the number of digits of each shift register is a prime  number is irredu, and for the bridge switch setting cible polynomials are used, it is ensured that the period has no sub-periods. Furthermore, the Requirement to meet that at least 1 bridge switch ge closed and in the shift register at least one binary 1 is available.

The number of possible basic keys is from tables and is irreducible when used Polynomials: 630 x 7710 x 27 594≅10¹¹.

The operation of the circuit Fig. 1 is as follows: The binary information zero or one running through the last register position with each cycle when the shift register rotates is output to the AND / OR mixer U / OM. This mixes the incoming information in 3 ways:

• 1) I (from RS I) + II (from RS II) with III (from RS III) or
• 2) I + III with II or
• 3) II + III with I.

The bits are returned from the outputs of two coupled shift register passed over an AND gate and the bits from one of these outputs and the Bits at the third output via an OR gate and on the bits are then signed at the outputs of these two gates or they become  Bits over a half adder not taking carry into account mod 2 headed. The average remains occurrence of 0 or 1 is approximately the same.

These mixing circuits are in irregular rows follow one after the other effectively. The quasi-random type of Ab change is prepared by the return of the further coupled shift register RS IV information output, which converts a circuit selector SW into an analog statement and passes on to the AND / OR mixer U / OM. The usage one or more shift registers RS I to RS III for Derivation of information for the selection of the circuit type through the AND / OR mixer is possible.

When using a special shift register RS IV for this purpose the number of basic and saying key required bits and thus also the Key depth.

It would also be possible to shift register RS IV to Er generation of the long total period to take into account that then to: (2¹¹-1) · (2¹³-1) · (2¹⁷-1) · (2¹⁹-1) ≅ 1.1 · 10¹⁸ bit grows. The number of possible basic keys when using irreducible polynomials: 176 · 630 · 7710 · 27 594 ≅ 1.7 x 1013. The switching types of the AND / OR mixer U / OM  result from the 4 outputs of the shift register now 6 options, namely:

• 1) The outputs of the first two random generators lead to an AND gate, the outputs of the two other random generators to an OR gate;
• 2) the outputs of the first and third random generators lead to an AND gate, the outputs of the second and fourth random generator to an OR gate;
• 3) the outputs of the first and fourth random generators lead to an AND gate, the outputs of the second and third random generator to an OR gate;
• 4) the outputs of the third and fourth random generator lead to an AND gate, the outputs of the first and second random generator to an OR gate;
• 5) the outputs of the second and fourth random generator lead to an AND gate, the outputs of the first and third random generator to an OR gate;
• 6) the outputs of the second and third random generator lead to an AND gate, the outputs of the first and fourth random generator lead to an OR gate.
  The outputs of the AND gate and the OR gate are each fed to a common half adder mod 2 in the manner mentioned above.

These possibilities of mixing binary values from 4 outputs A1 to A4 of the feedback shift registers can be supplemented by others. If you use z. B. each output twice, so that on the one hand to feed an AND circuit and on the other hand simultaneously an OR circuit, there are two AND and 20 OR circuits in the first mixer stage M1 (see FIG. 4). If one summarizes their results to a second mixer stage M2, one uses an AND circuit and an OR circuit. Their results are finally combined in a third mixing stage M3 with sign multiplication or half adder mod 2 to give the final result (see FIG. 4).

Such a mixing circuit is by adding more Any number of even outputs from shift registers expandable. Possible variants that the mixed result change, result from changing the ranking of Outputs A1 to A4 of the shift register to inputs E1 to E4 of the mixing circuit. Generally speaking, at the routing of n outputs to n inputs n! Possible available. If n = 4, 1 · 2 · 3 · 4 = 24 Opportunities.  

The circuit of FIG. 1 operates in such a manner that each stored three consecutive bits in the selector circuit SW and retrieved in parallel. The three-digit binary numbers occurring after every third work cycle are divided into groups of two and, depending on the addition result, determine the mixer circuit to be used, which thus changes continuously. For example, with a bit sequence 000 or 100 on the circuit selector SW, it is possible to mix the results mentioned above under 1) at the outputs of the shift registers RS I to RS III, with a bit sequence 110 or 001 at the circuit selector SW the sequence under 2) Mixture mentioned and with a bit sequence 011 or 111 on the circuit selector SW, the mixture mentioned under 3). If the bit sequences 010 or 101 occur on the circuit selector SW, on the other hand, there is no change to the mixture which has taken place previously.

The time at which the out in the circuit selector SW selected mixing circuit takes effect, but depends on one other parameters from the sequence of the slide gister RS I to RS III is created.

The bit sequence obtained in the mixer U / OM namely runs into a register PD, the so-called parallel actor, and leaves this as a parallel character in the 5-digit code in order to be decoded in the decoder De in (). While potentials at outputs 1 to 26 identify the key number that is fed to an adder mod 26 Ad for encryption or decryption, the activation of outputs 27 to 32 indicates the time at which the selected mixed circuit change takes effect. In Fig. 1 it is assumed that the adder Ad via the input K plain text either from the keyboard Ta or from the hole strip reader Le supplied and removed via the output V ver encrypted text. In the cases in which the outputs 27 to 32 of the decoder are active, no addition can take place in the adder Ad. In this case, therefore, the generation of a key bit must be repeated, if necessary until one of the outputs 1 to 26 of the decoder becomes active. For this purpose, the pulse line d is used, which then instead of coming from the adder Ad the pulse line controls the clock generator Tg for the key bit generation. The mixture of bit sequences from the shift registers RS I to RS IV thus depends on many, constantly changing parameters:

• 1) From the basic key and saying key information in the shift register RS IV, which the circuit choice certainly,
• 2) of all entered in the shift registers stored basic and spell key information,
• 3) from the time when the decoding one of the Outputs 27 to 32 meet.

In order to ensure the proper progress of the encryption or decryption, care must be taken when bits occur at one of the outputs 27 to 32 that a further cycle for controlling the adder mod 26 is initiated. For example, further characters can be called up for decoding in quick succession. The mean probability of not getting a usable hit quickly decreases; it is (6/26) ⁿ = (0.23) ⁿ for the nth character. At z. B. n = 10 characters, the mean probability reaches a sufficiently small value of 0.4 · 10 ^-6 .

With encryption and decryption with 10 characters / s shift register and mixing circuit maximum 100 Z / s, d. H. Can deliver 500 bits / s. That brings for the sub clocks even higher speeds.

You can use a different method, for each Hit by the decoder that goes to outputs 27. . . 32 falls, provides a replacement number. It is a Ring shift register available, in which the key numbers 1 to 26 can be entered, pointing the decoder in the direction Leave adder mod 26. This ring shift register has 26 memory cells and added mod 26. So each contains the sign a count value, which consists of all previously current results. If you notice a hit in the decoder  Output 27 to 32, so that is in the ring shift register saved count value used as key number.

So that the ring shift registers of the decrypt and decrypt the device always have the same position, they will be at Start of each encryption or decryption of a saying zeroed. So with two or more hits, that happen to fall one after the other on exit 27 to 32, not the same key number to the ring shift register is removed, it is also forwarded at these hits by 27 to 32 digits, d. H. the addition mod 26 by 1 to 6 digits.

According to a further embodiment, both can be described Procedures can be combined. So you leave max. Get 4 characters that don't match 1 to 26 before you takes the replacement number from the ring register. Thus these are only used very rarely, in the example with a medium one Probability for every 350th character.

Claims (9)

1. Method for forming key bit sequences using random generators, in particular for encrypting or decrypting teletype messages, for example by adding mod. 26, 27, 28, 29, 30, 31, 32 using basic and saying key with quasi-random key bit sequence, characterized in that the outputs of a plurality of random generators (RS I, RS II and RS III) controlled by a additional random generator (RS IV) in a quasi-random order with the inputs (E1, E2 ...) of a mixing gate circuit (U / OM). 2. The method according to claim 1 for encrypting or decrypting telex messages with quasi-random key-bit sequences from random generators by addition mod 26, 27, 28, 29, 30, 31 or 32 using basic and spell keys, characterized,
that a quasi-random mixture of the bits occurring at the outputs of three or a larger odd number of random generators takes place in such a way that the outputs of these random generators are scrambled in a quasi-random sequence and quasi-random way of alternation and with the inputs one Mixing gate circuit can be connected
that two inputs (E1 and E2, E3 and E4 ... E (n-2) and E (n-1)) are connected to the inputs of a common AND gate in this mixed gate circuit of n inputs,
one of these inputs and another circuit input (E2 and E3, (if present E4 and E5)... E (n-1)) and E n (each) are connected to the inputs of a common OR gate and
the outputs (each) of two AND and OR gates are connected to the inputs of a half adder mod 2 - optionally with the interposition of further pairs of AND or OR gates and
that a common output of this mixing circuit is used to generate the key-bit sequence. 3. The method according to claim 1 for encrypting or decrypting telex messages with quasi-random key-bit sequences Random generators by addition mod 26, 27, 28, 29, 30, 31 or 32 using basic and saying keys, characterized in that a quasi-random mixture of the at the outputs of four or more even numbers Number of randomly generated bits by ab alternate routing of the bits from the outputs of two Random generators via an AND or an OR gate, alternately routing the at the outputs of these gates occurring bits via a further AND or OR Gate, if necessary - with more than four random generators - repetition of this type of mixing, and in the last multiplication step subsequent sign multiplication that at the outputs of the AND and OR gates of the front last mixing stage occurring bits or line this Bits over a half adder mod 2 each in quasi-random temporal sequence and quasi-random type of change is used to generate the key bit sequence. 4. Device for performing the method according to claim 2 or 3, characterized in that the at the binary output the mixing circuit occurring in such number of bits Bit sequence that in a memory the binary value in the code frame of the predetermined telex code arises in parallel representation is fed to a decoder (D), wherein Depending on the agreement, the 5-code on one of 26 to 32 bits of decoding outputs appearing in the adder  mod 26 or 27. . . 32 for encryption or decryption is conducted while an impulse occurs the mixing one or one of several predetermined outputs circuit is switched, according to a quasi-random bit sequence of another random generator. 5. Device according to claim 4 or for carrying out the Method according to claim 2 or 3, characterized in that that one of the existing random genes at the binary output sequence of several (e.g. 3) bits by their binary value the type of the claim 1 or 2 mentioned mixture determined. 6. Device according to claim 4 or for carrying out the Method according to claim 2 or 3, characterized in that that one at the binary output of an additional random generator occurring sequence of several (e.g. 3) bits by their Binary value the type of those mentioned in claims 2 and 3, respectively Mixture determined. 7. Device according to claim 4, 5 or 6, characterized records that fed back as individual random generators Shift registers are used, the number of digits of which varies which correspond to prime numbers, or relative to each other are prim and taking the saying key into the memory cells of all shift registers is entered during the  Basic key the position of the individual switching devices determined in the feedback loops. 8. With addition mod 26 facility according to An saying 4, characterized in that one on one of 26 Bit occurring at predetermined outputs of the decoder each the adder mod 26 for the closings or resolutions is fed while a bit occurs switching on one of the remaining six outputs the mixing circuit is initiated, and that a another cycle to control the adder mod 26 is left. 9. With addition mod 26 facility according to An Proverb 8, characterized in that after a election number of cycles of the shift registers, which successively other hits on exits 27. . . 32 of the decoder surrendered, no further cycles and for locking A replacement number is available to adder mod 26 is made from a special ring slide gister comes, which all for the same saying on Output of the decoder resulting binary values 1 out of 32, mod 26 added up with carry.