DE1537955B2 - ANALOG-DIGITAL CONVERTER - Google Patents

Description

The invention relates to an analog-digital converter for converting a sequence of analog pulses same edge duration, but different amplitude and pulse duration in an identical cycle Sequence of single-valued digital pulses.

With the optical letter scanning of some letter readers, analog pulses of the above occur Kind on. Slides e.g. B. a photocell across a letter line, then an output pulse in the photocell is triggered, the edge of which rises until the photocell with its entire cross-section has caught the letter line. As long as the photocell has this letter line with all of its Detected cross-section, the output pulse remains at its maximum amplitude, and as soon as the photocell in the course of the further movement no longer covers the line with its entire cross-section, the begins Trailing edge of the output pulse. The edge duration is dependent on the relative movement between Photo cell and letter line and construction data of the letter reader, so for everyone Letter strokes that meet certain characteristics, which in many cases apply to all letter strokes applies, of the same edge duration, but different amplitude, since the amplitude is below among other things also depends on the width of the scanned letter lines.

For further digital processing of scanning results that occur in the form of such analog pulses, it is necessary to convert these analog pulses into binary pulses, with binary pulses are required, the beginning and end of which are exactly due to certain characteristics of the analog pulses are set so that the information content is retained during implementation. The ones to be digitized Analog pulses can instead of the normal trapezoidal shape, in which after the leading edge has elapsed Amplitude remains constant for a time before the trailing edge begins, also in triangular form as triangular pulses are present. Such triangular pulses only consist of a leading and trailing edge.

The object of the invention is to design an analog-digital converter of the type mentioned at the outset in such a way that that at least one flank - the leading edge or the trailing edge - of each Digital pulse clearly through the corresponding edge of the analog pulse from which the digital pulse is derived, can be determined precisely and reproducibly with simple means, even if the Analog pulses are present in a mixed trapezoidal and triangular shape. The invention is characterized by an amplitude comparator to which the analog pulses are transmitted via at least two parallel channels, the are equipped with at least one attenuator and a retarder, are supplied, and although undamped in the first channel and attenuated in the second channel and offset in time to the first Channel, so that a highest edge value of a damped analog pulse with the same amplitude The value of the edge on the same side of the undamped analog pulse coincides in time and that the comparator makes a transition in one when the sign of the comparison result is reversed binary output signal triggers. To determine positive or negative peak values of an input signal it is known from French patent specification 1389162, the input signal in to delay one of two channels over the other. This French patent concerns but not the subject matter from which the invention is based, nor does it provide a solution to the stated Task on which the invention is based. The invention is applicable to both on the leading flank as well as on the trailing flank and on both flanks. Will she be on the leading flank applied, then the undamped analog pulse is delayed compared to the damped one. If the damping then takes place at 50% and the delay at 50% of the leading edge duration, then with a straight leading edge, the damped pulse has reached its full amplitude when the undamped Pulse has reached half its amplitude. At this moment the transition of the binary output signal triggered. The comparator can capture this moment very easily because before At this moment the amplitude of the undamped pulse is smaller than that of the damped one and afterwards greater. The result of the comparison therefore reverses its sign at the moment in question. So exactly, as just described, with a straight flank course, the conditions are in practice usually not before. But that is not of great importance for the application of the invention, because by readjusting the attenuation with respect to the delay time, you can always achieve the desired Achieve relationships. Since the analog pulses in question due to their oblique Flanks are sweeping, they may touch each other. In order to get an exact To be able to carry out conversion into digital impulses, the conversion must be carried out without any recovery time in between two conversions take place, and this is possible with converters according to the invention. the Flank ratios are primarily a result of the design data of a letter reader other applications depending on the design data of the analog pulse generator, so that a single adjustment is usually sufficient. What just explained for a percentage of 50 Vo also applies to other percentages. ' One of the * Corresponding development of the invention is characterized in that the retarder by one Percentage of the edge duration designed to be retarded

is around which the attenuator is formed in a damping manner. These considerations apply to both triangular as well as trapezoidal analog pulses according to the task at hand.

According to the invention, the analog pulse to be digitized arrives at the comparator in various forms, although it is only subjected to attenuations and time delays. ' The single ones Channels can only be equipped with retarders or attenuators, i.e. very easily equipped.

An embodiment of the invention which allows the leading edge to be digitized is characterized in that that the first channel has a delay and the second channel has an attenuator and that the comparator triggers the leading edge of a binary output pulse when the amplitude value of the undamped analog pulse exceeds that of the damped one. The leading edge of the binary pulse is, as described above, determined by the sign reversal of the comparison result. The trailing edge can be different Way to be determined. If the exact position of the trailing edge is not important, you can trigger by the end of the analog pulse. But you can also use the same amplitude value as with the leading edge also with the trailing edge to trigger the trailing edge of the binary signal use, and this can be done very easily according to an embodiment of the invention, which thereby is characterized in that the comparator has a storage capacity for the maximum amplitude of the has damped pulse and that the comparator has the trailing edge of the binary output pulse triggers when the stored amplitude falls below that of the undamped analog pulse will.

In some cases the exact position of the leading edge of the binary pulse is not important, but probably on the back flank. A corresponding embodiment of the invention is thereby characterized in that, in a first channel, the analog pulses are sent without delay and undamped to the Get comparator and that an attenuator and a delay are provided in a second channel are and that the comparator triggers the trailing edge of a binary output pulse when the The amplitude value of the undamped analog pulse falls below that of the damped one.

One can trigger the transitions in the binary output signal according to the invention as well apply to both the leading and trailing edges. A corresponding preferred embodiment of the invention, which makes it possible to convert analog pulses into digital pulses of the same duration as to convert the analog pulses is characterized by a first channel with a delay, a second channel with an attenuator and a third channel with about twice as much Long as the delay of the first channel delaying delay and such a coordination of the attenuation to the delay times, that the maximum amplitude of the leading edge of the undelayed damped analog pulse is the same as that of the amplitude Value of the leading edge of the undamped analog pulse coincides and that the maximum amplitude of the trailing edge of the delayed and damped analog pulse with the same amplitude value of the trailing edge of the undamped Analog pulse coincides and that the comparator triggers a binary output signal, this continues as long as the amplitude of the undamped analog pulse is that of the damped one Analog impulses dominated. Are the analog pulses symmetrical in terms of their edges and occur the attenuation and time delay also symmetrically by placing both attenuated pulses around the are damped to the same extent and the leading one leads the undamped one by the same amount as the trailing one lags, then the binary transition becomes the leading edge at the same amplitude value and the trailing edge triggered. These ratios can be used in practice, especially in Mainly use in connection with letter readers. The invention is not based on this symmetrical application limited. In the described embodiment of the invention or in Modification of the same can trigger the binary trailing edge completely independently of that of the binary leading edge. The binary leading edge can e.g. B. at an amplitude value of ( 70% of the analog leading edge are triggered », -during the binary trailing edge with an amplitude value of the analog trailing edge of 30% can be triggered. By matching the delay times with the degree of damping the conditions can always be set as required for the respective practical application is most appropriate.

In some cases the analog voltage to be digitized will be disturbed by noise voltages. Such noise voltages can be suppressed quite easily in converters according to the invention in the course of the provided comparison process. A corresponding embodiment of the invention is characterized by a comparison voltage generator connected to the delay, which allows a comparison voltage to reach the comparator that is significantly smaller than the amplitude of the undamped analog pulse to be digitized and that binary output signals are suppressed as long as the amplitude of the un- (The damped analog pulse does not exceed the reference voltage. In such a case, the comparator has the undamped analog voltage and one or more damped analog voltages in addition to the reference voltage. If the comparison is now made from the undamped analog voltage on the one hand to all other voltages including the reference voltage and triggers the transition in the binary signals if and only if the undamped analog voltage exceeds or falls below the highest of the other voltages, then all analog pulses are inevitable suppressed for the binary output signal that do not exceed the comparison voltage.

The invention is not limited to the implementation of analog voltages in letter readers, but can be used particularly advantageously in connection therewith. For implementation, the attenuation must be matched to the delay times that the Implementation, meaningful. If you bring the binary with a letter reader Impulses again in the form of letters for display, then one can observe this

7 8

show the attenuation and time delay as long as the attenuator 16 can be a simple clamping

Readjust until the observed display is optimal, voltage-dividing resistance combination. Of the

z. B. is optimally readable. This, so to speak, integrated delay 19 can be a known artificial

Adjustment option has proven to be very advantageous delay line. The comparator 13 compares

grasslands. 5 continuously connect the two to the input

The invention is now based on the drawing sen I and II injected voltages and generated

explained in more detail. According to the comparison result, the drawing shows a digital

F i g. 1 in the block diagram shows an example of an output signal that is sent to the output terminal 26

according to the invention, in which the implementation of the reaches. The details of the operation of the comparator

Leading edge of the pulses goes out,. io will be discussed further below with reference to FIGS. 4 explained.

F i g. 2 shows a second exemplary embodiment in block FIG. 2 shows a detector in a block diagram,

circuit diagram in which the conversion from the reverse to the trailing edge of the analog pulses responds,

edge of the impulses goes out, which in the text to F i g. 1 described analog pulses

F i g. 3 shows a third exemplary embodiment in the block approach according to FIG. 2 to input port 12 circuit diagram created by the composition of 15 and from there via two parallel channels to the two first exemplary embodiments has arisen, same 13, the two input connections I ', II' on-

F i g. 4 is a timing diagram to explain the point. The first channel consists only of a conduction mode of operation of the third embodiment, connection 20 'between the input port 12

F i g. 5 shows the circuit of the third execution terminal and the input terminal I '. The second channel

for example, somewhat modified and detailed, 20 has a delay 22 which is connected via the line

F i g. 6 the circuit of the first embodiment 21 is connected to the input terminal 12. To the

example, supplemented by a storage capacity of the delay 22 is an attenuator 24 via a

Comparator and shown in more detail, line 23 connected downstream. The attenuator 24

F i g. 7 a modification to the embodiment is via a line 25 to the input connection II '

example according to FIG. 6 and 25 placed. The output terminal of the comparator, the

F i g. 8 is a timing diagram to explain the output terminal of the detector at the same time

Embodiment according to FIG. 7th tors is denoted by 26. The comparator

According to FIG. 1, a transformer is processed with 10 similar to that from FIG. 1, its function

draws which, for example, becomes an optical letter - in more detail below with reference to Fig. 4

can belong to the scanner. In such a case, 30 will be explained.

the transmitter 10 is supplied with optical signals. The two delayers 19 and 22 from FIG. 1 can

suggests that the optical scanning of letters NEN have the same structure and function

be identical due to reflection on the white background. The same applies to the

and in the transformer in electrical voltage attenuators 16 and 24.

or current pulses are converted. This 35 F i g. 3 shows in the block diagram a third off-voltage or meet current pulses with regard to the exemplary embodiment according to the invention, through their edges and their amplitudes do not affect the combination of the exemplary embodiments from FIG. 1 conditions that may have arisen for further digital processing and 2 and on the front and such impulses must be provided. In order to show this trailing edge of the fed-in analog pulses To express themselves, the output 40 is speaking. In the following, analog pulses from the transmitter 10 are sent to the input terminal 12 as analog signals, as in the text relating to FIG. 1 explained, fed in, impulses, they have flat front and the input terminal 12 is over three parallel Trailing edges and different amplitudes. For channels at the three input connections I, II, III of the the indicated scanning of letters and comparator 13 '. The first and second channels off however, the rise time is also 45 F i g in other cases. 3 are identical to the first and second and the fall time of the edges for all pulses channel from FIG. 1, while the third channel is off the same size, whereby this period of time by once F i g. 3 fixed a piece with the second channel Data of the scanning device is determined. falls, so that the second and third channels the Ver-Bei the scanning of letters via a light retarder 19 have in common. Following the sensitive disc are z. B. the diameter 50 retarder 19 branches off the remainder of the third channel. of this disc and the speed with which this remainder is formed in the same way as the second the scan moved over the letters, measured channel from F i g. 2. The channels are given in a number numbered for the rise and fall times of the sequence in which, due to the delay Flanks. The analog pulses in question, which are 19,22, are fed into the comparator 13 ' have the same rise and fall times, get out of 55. An analog input pulse at the input dem Transmitter 10 with the interposition of connection 12 passes over attenuated and without delay Amplifier 11 to the input terminal 12 of the first channel in the comparator 13 '. The same Detector. analog input pulse arrives delayed, but un-

The input connection 12 is attenuated via two channels in the second channel in the comparator

two inputs marked with I and II of a Ver 60 13 'and also twice delayed and attenuated

same 13 connected. The first channel is via the third channel into the comparator 13 '. Of the

a line 15 an attenuator 16 follows the on-undamped pulse in the second channel

output connection 12 connected, and the damping a time unit delays the damped pulse

Fung member 16 is on line 17 at the input in the first channel, and the attenuated pulse in the connection I of the comparator 13. In the second channel, the third channel is followed by a further time unit

Via line 18 a delay 19 to the input to the undamped pulse of the second channel,

output connection 12 connected via the line In the comparator 13 'is the undamped,

20 is at the input terminal II of the comparator 13. but with a delayed pulse by one time unit

compared to the pulses of channels I and III. The resulting output signal of the comparator 13 'is binary and is present if and only if the pulse at the input terminal II is greater than both than the one at the input connection I as well as the one at the input connection II. It can also a comparison voltage source 28 ί can be provided on the comparator 13 ', the ^ a comparison voltage via the line 29 in the comparator 13' feeds. The comparator 13 'can be designed in such a way that the binary output pulse is suppressed if and as long as the undamped pulse at input terminal II does not become the comparison voltage towers. The comparison voltage can be far below the voltage of the analog pulses at the input connection 12 lie, so that only small noise pulses and other interference pulses for the binary output are suppressed. The two detectors from FIG. 1 1 and 2 can accordingly be supplemented by such a comparison voltage source 28.

In Fig. 4, the pulses fed into the comparator 13 'are shown in the top line and denoted by the same Roman numerals as the input connections at which they are fed into the comparator 13'. In the second line, the respective binary output signal derived therefrom and occurring at connection 26 is recorded in a timely manner. The constant comparison voltage of the comparison voltage source 28 is designated by THR in FIG. 4. In Fig. 4, three analog pulses with different amplitudes are shown in the first line. The first two are trapezoidal, and the last is triangular. The analog pulses drawn in strong lines in FIG. 4 are those arriving via the second channel in the comparator 13 'and are therefore only delayed by one time unit compared to those present at the input connection 12. It can be seen that all three analog pulses have the same edge duration, ie both the leading and trailing edges of all analog pulses extend over the same period. It is assumed from ^{FIG. 1} that the attenuators 16 and 24 each attenuate by exactly 50%. The delays 19 and 22 are accordingly each matched to a delay time that is exactly half as long as the edge duration, that is, the time that the pulse edge needs to fully rise or fully fall. This dimensioning has the consequence that the amplitude of the analog pulse I is half as large as that of the analog pulse II. Since the analog pulse II is delayed by half the edge duration, it has just reached half its amplitude when the pulse I has reached its full amplitude . At this moment the amplitudes of impulses I and II are the same, and then the amplitude of impulse II is the greater.

The binary output signal in the second line of FIG. 4 therefore has a transition at this moment, namely it drops from its inactive high voltage level to its active lower voltage level and thus indicates that the pulse amplitude of the analog pulse II is now greater than that of the analog pulses I and III and that of the comparison voltage THR . The circuit from FIG. 1 also acts in the same way as just described, and with the same dimensioning of the attenuator 16 and the delay 19 from FIG. 1, the binary pulse begins at the output terminal 26 as soon as the analog pulse II, delayed by a unit of time, has reached half of its maximum amplitude.

S In the circuit according to FIG. 1 falls the binary Output pulse from the end of the delayed analog pulse II and, if a reference voltage source 28 is provided when the trailing edge of the delayed analog pulse II the

ίο falls below comparison voltage.

According to FIG. 4, the analog pulse II, delayed by two time units and attenuated, begins in the Moment at which the amplitude of pulse II exceeds that of pulse I. That is a consequence of the special dimensioning chosen in this exemplary embodiment. The trailing edge of pulse III begins at the moment when the amplitude of pulse II falls below that of pulse III at this moment to the amplitude of the pulse II

zo is no longer the largest, an opposite transition takes place in the binary output signal, which now falls back to its inactive level. Only the pulses II and III were involved in this backward transition, which are also present in the second exemplary embodiment. \ In the second embodiment, so the trailing edge of the binary output signal is produced the same way as just explained, the leading edge, however, the analog input signal coincides with the beginning. If a comparison voltage source according to FIG. 2 is provided, the leading edge of the binary output signal falls according to FIG. 2 together with the moment at which the fed-in analog signal exceeds the comparison voltage.

. As shown in FIG. 4, they are sufficient the represented analog pulses derived binary pulses from the moment where the leading edge has reached half the amplitude until the moment when the trailing edge has half the amplitude falls below, completely independent of the value of the amplitude of the fed in analog pulses. The duration of the binary output pulses is therefore determined solely by the actual width of the analog pulses, regardless of their amplitude. The two in FIG. 4 analog pulses drawn on the right touch each other. But this has to do with the Deriving the binary impulses as they are -. in the circuit according to FIG. 3 takes place, no influence. The circuit of FIG. 3 therefore does not require any recovery time between two analog pulses.

If you want to capture an amplitude level other than 50% of the maximum amplitude, then you have to you can adjust the retarders 19 and 22 and the dampers 16 and 24 accordingly. Do you want z. B.

the transitions in the binary output signal trigger at 70% of the maximum amplitude, then the Damping can be set to 30% and a delay time unit to 30% of the edge duration. Of course, these considerations only apply strictly to straight flanks. In practice they are Flanks not straight, but by adjusting the attenuators and accordingly the delay the detector can always be adjusted so that the transitions in the binary signal take place at the desired locations. The most appropriate setting in practical use the circuit parameters mentioned can best be obtained empirically by considering the respective

compares derived binary impulses with ideals using an oscillograph.

F i g. 5 shows the circuit from FIG. 3 in detail, some block boxes from FIG. 3 are again shown in dashed lines and with the same reference numerals as in Fig. 3 are designated. Furthermore, in FIGS. 3 and 5 equal parts; with same Designated reference numerals. The input connection 12 is located according to FIG. 5 has a capacity 31 at the Line 32. The capacitance 31 serves as a direct current block between the detector circuit shown and a transformer corresponding to the transformer 10 from FIG. 1, which is connected to the input terminal 12 is. The line 32 is connected to a diode 33 on the line 34, which in turn is connected to a - 6 volt direct voltage potential is present. Positive Input pulses are therefore at this reference voltage of - 6 volts, while negative input pulses are short-circuited via this voltage source will. A positive analog pulse on line 32 arrives via three parallel channels the three input terminals I, II and III of the comparator 13 '. The first channel leads from the line 32 via the voltage divider 16 to the input terminal I. The second channel leads through the first Half of the delay line 35 from a center tap 36 to the input terminal II. The third Channel leads over the entire delay line 35 and a voltage divider 24 to the input terminal III. The end of delay line 35 is short-circuited via a resistor 38 which is parallel to the resistor of the voltage divider 24 lies. This ensures that no energy flows from the end of the delay line into the Delay line can be reflected back.

The three input keys, II and III of the comparator 13 'are connected to the base electrodes of the three transistors 41, 42 and 43, respectively. The emitter electrodes of these transistors are connected to a common line 44, which in turn is connected via a resistor 45 and line 46 at a -12 volt potential lies. The line 44 is also connected to the emitter electrode of a further transistor 40, its base electrode via line 29 to a comparison voltage source 28, which has a resistance as Has voltage divider between the -6 volt potential is on line 34 and a ground connection. The collector electrode of the transistor 42 is connected to a +6 volt potential via line 49. The collector electrodes of the other transistors 40, 41 and 43 are connected to one via a common line 50 and a positional resistor 51 + 12 volt potential. The line 50 is also connected to a diode 53 and to the base electrode of one Transistor 54. The other electrode of diode 53 is at ground potential and at the emitter electrode of the transistor 54. The collector of this transistor 54 is connected to the output terminal 26 and via a Resistor 55 at the already mentioned - 12 volt potential. The circuit components 53 to 55 form an inverter 52, the meaning of which will be explained further below.

If no signals are fed in, the three input connections I to III of the comparator are present 13 'all at - 6 volt potential. The base electrode of the transistor 40, however, lies on a comparison voltage whose value is between 0 and - 6 volts, e.g. B. to -5 volts, corresponding to an actual comparison voltage of +1 volt. Under these circumstances, the control voltage on the base electrode of the transistor is higher than that of all other transistors 41 to 43. The transistor 40 is conductive under these circumstances, so that the Voltage on common emitter line 44 corresponds to the comparison voltage, while the three Transistors 41 to 43 are turned off. However, as soon as one of these transistors has a voltage higher when the comparison voltage picks up, the transistor becomes conductive, and the common emitter voltage rises and transistor 40 turns off. So it is always one of the four transistors 40 up to 43 conductive. The diode 53 is switched off and the transistor 54 is conductive, so that the output voltage is at its high level, in practice at zero volt level. These conditions do not change when an analog pulse occurs on input terminal 12. When the leading edge of the pulse in channel I exceeds the comparison voltage, the transistor 40 switches off and the Transistor 41 is on, but the voltage on line 50 remains low and the output voltage is on Output port 26 at its high level, e.g. B. to 0 volts.

However, as soon as the undamped pulse II in the second channel becomes the most positive (this is the case, when the leading edge reaches 50% of the maximum amplitude), transistor 42 is turned on, and the voltage on the line 50 exceeds 0 volts, whereby the diode 53 becomes conductive and the Transistor 54 is turned off. The output voltage at the output terminal 26 then falls steeply to -12 volts and remains at this negative value until one of the transistors 40,41 or 43 becomes conductive and transistor 42 is switched off. This happens as soon as the trailing edge of the undamped pulse II in the second channel falls below 50% of the full amplitude. In In this case, the transistor 43 becomes conductive, whereupon the voltage on the line 50 increases again negative value drops. The transistor 54 then becomes conductive again, and at the output terminal 26 the potential quickly rises again to the high value, here 0 volts. At the same moment it is Circuit prepared to process a new analog input pulse in the manner described. So no recovery time is needed. It should also be noted that the comparator 13 ', which has been described here, also in connection with the circuit according to FIG. 1 find use can. The second part of the delay line 35, the attenuator 24 and the transistor 43 are then superfluous. Accordingly, the comparator 13 'can also be used in conjunction with FIG. 2 can be used, in which case the attenuator 16, the transistor 41 and the first part of the delay line 35 are superfluous. In changing the mode of operation described, it is also possible instead of the Line 50 to pick up the output signal also from line 49, as is now shown with reference to FIGS. 6th is explained in more detail.

The in F i g. The circuit shown in FIG. 6 is similar to that in FIG. 1 shown, but in more detail. The comparator 130 has three transistors 40, 41 and 42 with a common resistor 45, which are connected as in Fig. 5. The comparator 130 is also equipped with a capacitance,

13 14

which sampled the maximum amplitude of the damped pulse I like the leading edge. The advantage of this

according to FIG. 1 receives and stores, so that this circuit compared to that of F i g. 5 is that

stored value can be tightened to with only a shorter delay line needed

On the other hand, the comparator 130 needs

to be resembled. 5 from FIG. 6, a short recovery time, in particular

The base electrode of the transistor 41 lies over after an analog pulse of large amplitude, the line 47 at the base of the; In the examples described so far, its collector electrode was sampled together with the output signal if and as long as the collector electrodes of transistors 40 and 41 at analog pulse II is greater than all other comparisons of its line 50, which is at a +6 volt potential j . _{o there was} tension. There is also an inverse connected to it. The emitter electrode of the Tran solution, which is now shown on the basis of FIG. 7 is explained, sistor 57 is connected via a diode 58 to a common connection in the circuit according to FIG. 7 is the same emitter line 44, on which the emitters of a detector circuit according to FIG. 1, supplemented by the other transistors 40 to 42, are located. The one storage capacity in the comparator. The VerEmitterelektrode of the transistor 57 is also set i ₅ gleichereingangI is shown in Fig 7 on the base through a capacitor 59 to line 46, which in the an npn transistor 61 whose collector is connected to a mentioned -. Volt potential 12 is connected. The +12 volt potential is present, while the emitter is connected to the collector of transistor 42 via the line 64. The line 64 is connected via a 49 and a resistor 56 to a +12 volt diode 65 to a reference voltage source THR, potential. The line 49 is also on a ₂ o z. B. a +8 volt potential, and via the capacitance inverter 60 at the output terminal 26. The In- did 66 at a +6 volt potential. In addition, verter 60 can be constructed in the same way as the line 64 via a resistor 63 at the emitter inverter 52 from FIG. 5. a pnp transistor 62, the base of which is connected to the circuit according to FIG. as long as there is no analog pulse at the input, output 26 is 25. The collector of the transistor 62 ^ «only the transistor 40 conductive. The transistor 42 is also switched off to ground potential via the diode 68, and the line 49 is connected to its high level and via a resistor 67 to a voltage level, and the output signal is connected to the off-12 volt potential. The pulse that is output terminal 26 is at its low level. when operating the circuit according to FIG. 7 occur, when the transistor 40 is conductive, the voltage 30 is shown in FIG binary output pulses as in voltage source 28. Because of the diode 58, the F i g. 4th

The voltage of the capacitance 59 should never be higher than Before an analog pulse is fed into the circuit according to the voltage on the line 44. 35 Fig. 7, the comparators - If an analog pulse at the input terminal 12, inputs I and II of the comparator 132 are both fed to , the transistor 41 becomes conductive. The. +6 volt potential. A current then flows from the transistor 57, via the line 47, the +8 volt potential via the diode 65, the line analog pulse I as control voltage, and accordingly 64, the resistor 63, the transistor 62 and the following also follow the voltage across the capacitor 40 resistor 67 to the -12 volt potential. The sator 59 the analog pulse I. As soon as the analog voltage Vc at the capacitance 66 is now pulse I has reached its maximum amplitude, conducts +7.8 volts. The transistor 61 does not conduct. The transistor 57 does not continue, and the voltage resistor 63 limits the emitter current of the Tran corresponding to the last value of the control voltage sistor 62. The resistor 67 is set so that at the base of the transistor 57 in the capacitance 45 only a part, z. B. a tenth of the collector current 59 is stored. The diode 58 is now blocked, and the voltage on the line 44 follows the analog flow via this resistance at the -12 volt potential. The collector voltage then rises above pulse II, which controls transistor 42. The voltage is 0 volts, so that the diode 68 becomes conductive and the voltage now exceeds the peak voltage of the collector forces it to ground potential. The output analog pulse I, the voltage stored in the capacitor 59 is now approximately 0 volts. However, if was. While transistor 42 is conductive, before transistor 62 is turned off, the voltage on line 49 switches to output voltage at output terminal 26 suddenly to its lowest level, and therefore the off is from 0 to -12 volts only because the output signal at the output terminal 26 cease to be at its last 10% of the collector current, high level. After half of the trailing edge 55, when the leading edge of the attenuated analog of the analog pulse II has expired, it reaches the pulse I above + 7.8VoIt, the peak voltage of the analog pulse I and the lower transistor 61 are conductive. The voltage Vc at the increases this. The diode 58 is now forward. The diode 65 charges via the diode 58 and the resistor 45. 60 is blocked. The transistor 62 remains conductive until the analog pulse II, consisting of the capacitance 59 delayed but not attenuated, and the resistor 45, is chosen so large that it has reached half of its maximum amplitude. Voltage on line 44 drops more slowly than now analog pulses I and II coincide, and the trailing edge of analog pulses II. The result is that the emitter and base voltages of transistor 62 are switched off and transistor 42 is switched off and transistor 65 is equal, so that it turns off. The transistors output signal at the output terminal 26 again on 61 and 62 and the diode 65 are now all when its low value drops. The trailing edge of the switched so that the charge in the capacitance 66 analog pulse is thus stored over the same level. The output signal has turned on

its -12 volt potential changed. This switching state now remains until the analog pulse II drops and the stored one with its trailing edge The peak voltage of the analog pulse I undershoots. If this takes place, then the transistor 62 becomes conductive and switches the output voltage at the output terminal 26 back to 0 volts. The ^ capacity 66

■■ £ - ■■■

is now charged via the resistor 63 and the transistor 62, whereupon the voltage Vc returns to the comparison voltage +7.8 volts. The system is now back in its original state. The diode 65 is now conductive. F i g. 8 shows the emitter voltage of the transistor 62, which is drawn in with a dotted line and denoted by Ve.

1 sheet of drawings

309 510/402

Claims (11)

Patent claims: 1. Analog-digital converter for converting a sequence of analog pulses of the same type Edge duration, but different amplitude and pulse duration in a taktsjeiche sequence of single-valued digital pulses, characterized by an amplitude comparator (13), which the analog pulses via at least two parallel channels (I, II), which with at least one Attenuator (16) and a delay (19) are supplied, namely in the first channel (II) undamped and in the second channel (I) damped and offset in time to first channel, so that a highest edge value of a damped analog pulse with the The same-amplitude value of the edge of the undamped analog pulse on the same side coincides in time and that the comparator (13) causes a transition in a binary output signal when the sign of the comparison result is reversed triggers. 2. Analog-to-digital converter according to claim 1, characterized in that the delay (19) is designed to be retarded by a percentage of the edge duration in order to dampen the Attenuator (16) is formed. 3. Analog-digital converter according to claim 1 and / or 2, characterized in that the first channel (II) has a delay (19) and the second channel (I) has an attenuator (16) and that the comparator (13) triggers the leading edge of a binary output pulse, when the amplitude value of the undamped analog pulse exceeds that of the damped one. 4. Analog-digital converter according to claim 3, characterized in that the comparator (130) has a storage capacity (59) for the maximum amplitude of the damped pulse and that the comparator (130) triggers the trailing edge of the binary output pulse, if the stored amplitude falls below that of the undamped analog pulse. 5. Analog-digital converter according to one or more of claims 1 to 3, characterized in that that in a first channel (I ') the analog pulses reach the comparator without delay and undamped and that in one second channel (H ') an attenuator (24) and a delay (22) are provided and that the Comparator (13) ■ the trailing edge of a binary output pulse triggers when the amplitude value of the undamped analog pulse is that of the subdued falls below. 6. Analog-to-digital converter according to one or more of the preceding claims for Conversion of the analog pulses into digital pulses each with the same duration as the analog pulses, characterized by a first channel (II) with a delay (19), a second channel (I) with an attenuator (16) and a third channel with an approximately twice as long as the Delayers (19) of the first channel delaying delay (19, 22) and such a tuning the attenuation on the delay times that the maximum amplitude of the leading edge of the instantaneously attenuated analog pulse (I) with the same amplitude value the leading edge of the undamped analog pulse coincides and that the maximum amplitude of the trailing edge of the delayed and damped analog pulse with the same amplitude value of the trailing edge of the undamped Analog pulse coincides and that the comparator triggers a binary output signal that lasts as long as the amplitude of the undamped analog pulse exceeds that of the damped analog pulse. 7. Analog-digital converter according to one or more of the preceding claims, characterized by a comparison voltage generator connected to the delay (13 ') (28), of which a comparison voltage is much smaller than the amplitude of the undamped, too digitizing analog pulse can reach the comparator (13 ') and that binary output signals can be suppressed as long as the amplitude of the undamped analog pulse does not exceed that of the reference voltage. ■ -. protrudes. V. 8. Analog-to-digital converter according to claim 6 or 7, referring back to claim 6, characterized by a voltage divider (16) connected to an input connection (12) as Attenuator whose tap is connected to the base of a first transistor (41) of the comparator (13 ') and through a delay line connected to the input terminal (12) (35), which is connected via a center tap to the base of a second transistor (42) of the comparator (13 ') and via an end tap to the base of a third transistor (43) of the comparator (13 ') is connected, and in that the emitters, these comparator transistors (41 to 43) combined via a common resistor (45) to a negative potential (-12VoIt) are connected, and in that the collector of the second transistor (42) to a first positive potential (+ 6VoIt) and the collectors of the other comparator transistors (41, 43) to an output terminal (26) and via a common resistor (51) to a second, higher positive potential (+12 volts) are connected. 9. Analog-digital converter according to claim 4, characterized by a voltage divider connected to the input connection (12) (16), its tap on the base of a first transistor (41) and the base of a third transistor (57) of the comparator (130) is connected and through a to the input connection (12) connected delay line (19), the output side to the base of a second transistor (42) of the comparator (130) is connected, and in that the emitters of the first and second transistor directly and the emitter of the third transistor with the interposition a diode (58) combined via a resistor (45) to a negative potential (-12VoIt) are connected, to which the emitter of the third transistor (57) also is connected via a capacitance (59), and in that the collectors of the first and third transistor (41, 57) a first positive Potential (+ 6VoIt) and the collector of the second transistor (42) to an output terminal (26) and via a resistor (56) are connected to a second, higher positive potential (+12 volts). 10. Analog-to-digital converter according to claim 8 or 9, characterized in that the common Collector connection uncr the output (26) an inverter (52) is interposed. 11. Analog-digital converter according to claim 7, characterized in that a fourth comparator transistor (40) is provided, the emitter of which is connected to the negative potential (-12VoIt) via the common resistor (45), whose collector lies on the common collector connection (50) and its base on one A voltage divider (28) designed as a comparison voltage generator is located.