DE10211570A1 - Method of running linear store e.g. for processor systems, requires updating used storage zones via driver circuit - Google Patents

Method of running linear store e.g. for processor systems, requires updating used storage zones via driver circuit

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Publication number
DE10211570A1
DE10211570A1 DE2002111570 DE10211570A DE10211570A1 DE 10211570 A1 DE10211570 A1 DE 10211570A1 DE 2002111570 DE2002111570 DE 2002111570 DE 10211570 A DE10211570 A DE 10211570A DE 10211570 A1 DE10211570 A1 DE 10211570A1
Authority
DE
Germany
Prior art keywords
memory
rcu
dram
linear
driver circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE2002111570
Other languages
German (de)
Inventor
Wolfgang Ecker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE2002111570 priority Critical patent/DE10211570A1/en
Publication of DE10211570A1 publication Critical patent/DE10211570A1/en
Application status is Ceased legal-status Critical

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Abstract

The invention relates to a method for operating a linear memory and a digital circuit arrangement with a linear memory. Such linear memories are used in particular in digital circuit arrangements such as processor systems with a memory control unit (memory management unit) and an associated, in particular embedded, linear memory. DOLLAR A Since the refresh of the linear memory has a large share in the power consumption of the circuit arrangement, it is provided to reduce the power consumption that only periodical updates of the memory areas of the linear memory (RAM, 2) by a driver circuit (RCU, 6) only the memory areas used be updated.

Description

  • The invention relates to a method for operating a linear memory and a digital circuit arrangement with a linear memory.
  • Such linear memories are used especially in digital Circuit arrangements such as processor systems with one Memory control unit and one assigned, in particular embedded, linear memory used.
  • The Memory Management Unit (MMU) is with processors, threads or similar data processing arrangements coupled, the each have a memory area of the DRAM with a specific one Take up size. There is one in the MMU Mapping table provided, the one or more virtual Memory areas of the processors, threads or the like in each case maps a memory area of the linear memory (RAM). It is possible that the memory areas of the processes the storage capacity of linear memory exceed what an outsourcing of storage areas to another medium required, which is usually a larger, but slower storage medium. It is also possible that at times not the entire memory area of the linear memory from the memory areas of the processors managed by the MMU is needed.
  • As a linear storage for large capacity is usually a dynamic RAM (DRAM) used, the memory elements in Rows and columns are organized. The storage elements are via a row address and a column address described. It is operated in such a way that the Memory contents are updated periodically (refresh). This DRAM is operated by a driver circuit (refresh Control Unit) performed by the Memory contents read out line by line and rewritten after the last line with the first is started. If there is no update, the Memory contents of volatile memory lost.
  • In an allocation table is the for each memory area allocation information stored in the linear memory the respective memory area as "used" or "not Used "or" Available "indicates. On request for space by a processor only those are considered "Not used" marked memory areas for a Assignment to the processor available. The content of the Allocation table is therefore based on that of the Processors currently requested memory areas. The each required memory areas vary depending on the Complexity of the process carried out.
  • In FIG. 1, a digital circuit arrangement according to the prior art. The memory management unit (MMU or a hardware unit with similar functionality) contains a mapping table (Fig-Tab), an allocation table (All-Tab), a control unit (MMU Control) and a driver circuit (RCU: Refresh Control Unit). The MMU is connected to one or more processors, threads, or similar data processing circuits, which are not shown. A digital circuit arrangement according to the prior art with a linear memory which is coupled to the MMU is explained with reference to FIG. 1. The mapping table maps the virtual memory areas of the processes to a linear memory area of the DRAM. When a process accesses the linear memory, the corresponding memory area of the DRAM is addressed by means of a row address and a column address using the mapping table based on the transmitted process ID and virtual process address.
  • If the MMU Control receives control signals via a control line with which the memory area for a process is to be enlarged (stack and / or heap), the MMU Control searches for available memory areas in the allocation table via another control line. If no storage capacity is available, the request is rejected or a storage area is swapped out. The outsourcing to another storage medium is not shown in FIG. 1. If free memory areas can still be made available, this is allocated to the process. To do this, the address space of the process is enlarged and the mapping table expanded accordingly. The allocation table is also adjusted, ie these memory areas are marked as "used".
  • If a process opposes a smaller memory area required, the assigned linear memory area be made smaller. For this, the entry in the figure table removed and the memory area in the allocation table again marked as "available".
  • The RCU updates the memory areas of the DRAM line by line, the refresh being repeated periodically. The rows of the DRAM are addressed in succession using the column address and a refresh signal is applied in each case, so that an update time t R is required for each row. The method according to the prior art is shown in FIG. 2 by a flow chart. After a line n has been refreshed, the next line n + 1 is then refreshed by the RCU. When the last line of the DRAM n max is reached , the RCU then refreshes the first line again.
  • Due to increasing integration with more circuits in one digital system can pass through in a confined space Heat generated can become problematic. in the worst case, even the functionality of the digital Systems will be affected. An attempt must therefore be made to To keep the power consumption of the individual circuits low or decrease. A low power consumption is also for known ecological and economic reasons advantageous especially when used in battery operated Devices become clear.
  • To reduce the power consumption are in particular Process known on the reduction of leakage currents based, depending on the amount of target Reduction of a more or less large amount of circuitry is necessary for implementation.
  • Since the refresh of the linear memory accounts for a large proportion of the Power consumption will be advantageous there after Wanted energy saving opportunities. Therefore, in addition to the physical Procedure for reducing power consumption still one Method known in which a statistical investigation is carried out to determine whether more "0" or "1" values are saved. Dependent on the power consumption for the refresh of "0" or "1" values then all values are stored unchanged or inverted. This process requires considerable effort Determination of the statistical evaluation and if necessary for one Inversion of the values to be saved.
  • It is therefore the object of the invention to provide a method for Operation of a linear memory that easily a Reduction of the power consumption of such a memory enables, as well as a linear memory with reduced To create power consumption.
  • The task is accomplished through a procedure with the Features listed claim 1 solved.
  • In the method according to the invention, the periodic Update of the memory areas for the memory areas of the linear memory (DRAM), which at the time not used during the update. During the Operating the linear memory, the values are in one or temporarily no longer in several memory areas needed. If all the storage elements for one at a time Refresh is to be performed in a memory area whose values are no longer required, then a refresh is not required for this area. That is, if everyone Storage elements of a row for a storage area belong that is no longer needed, the refresh is omitted for this line. If there is no refresh, the Memory contents are not renewed and are lost. This one Areas not used, however, are the memory contents (i.e. the state of charge) without meaning. By dropping out the refresh can save power.
  • In an advantageous embodiment of the invention The procedure is the one stored in an allocation table Information about used and unused Memory areas supplied to the RCU. This already for the allocation of available memory areas Allocation information is now also made available to the RCU. Thereby the RCU receives the information in a particularly simple manner about used memory areas.
  • In a further embodiment, the RCU carries out a refresh if the respective memory areas are identified as "used" in the allocation table. If a refresh should be carried out for an available memory area, this is omitted. The RCU remains in an idle state in the update time t R provided for this refresh and does not perform the refresh for the next line prematurely. Such pauses reduce the power consumption of a digital circuit arrangement.
  • In a further development of the procedure, the RCU receives only that Allocation information from the allocation table for the available memory areas. If the RCU is one Allocation information is supplied to the associated Indicates memory area as "Available", the refresh omitted and the RCU put into an idle state. Since the Al Location information of the memory areas used is not omitting the refresh can be particularly difficult can be easily realized. In particular, the RCU can can also be arranged within the linear memory, and only receives the information whether the refresh for a Line is not performed.
  • Furthermore, the task is still digital Circuit arrangement with the features solved as in Claim 5 is specified. The digital circuit arrangement contains a linear memory (DRAM) and one Memory control unit (MMU), the coupled data processing circuits (Processors or the like) Memory areas of the linear memory assigns. A driver circuit (RCU) is with the Circuit arrangement designed in such a way that it only the used memory areas of the linear memory periodically updated (refresh). The RCU is therefore switchable designed so that it is possible to refresh for one to refrain from available memory area. The absence a refresh leads to a loss of the Memory content of the affected area, which is available, not used, but memory area is not critical. However, the RCU of the invention Power consumption of the circuit arrangement can be reduced because each Eliminating a refresh saves performance.
  • The digital circuit arrangement according to the invention is advantageously designed such that an allocation table to store information about the availability of Memory areas of the linear memory is provided, the via a control line with the driver circuit (RCU) connected is. To manage the linear memory is in the MMU usually contain an allocation table to use the Allocation information for storage space requirements Processors can assign a memory area. By the RCU can establish the connection via the control line The information is supplied in a surprisingly simple manner as to whether a memory area is used. Then the RCU can Dependency of this allocation information in an active one State or a hibernation what is on particularly simple way by supplying an activation signal can be realized.
  • The invention can be particularly advantageous in systems with embedded linear memory can be used (embedded Systems).
  • Exemplary embodiments of the invention are described below described by figures. Show
  • Fig. 1 is a block diagram of a digital circuit arrangement according to the prior art,
  • Fig. 2 is a flow diagram of a method for operating a linear memory according to the prior art,
  • Fig. 3 is a block diagram of a digital circuit arrangement according to the invention and
  • Fig. 4 is a flowchart of a method for operating a linear memory according to the invention.
  • In FIG. 3, in a schematic block diagram of a digital circuit arrangement of the invention is shown, to which a memory control unit (Memory Management Unit) 1, and a linear memory (DRAM) 2 belong. The processors or similar data processing circuits which are connected to the memory management unit (MMU) 1 are not shown. The MMU 1 operates the DRAM 2 and controls access to the memory areas of the DRAM 2 by the processor or processors. The processors each have a virtual memory area that is managed by the MMU 1 . For this purpose, a mapping table (Fig-Tab) 3 receives from a process a ProcessID, with which the respective process is identified, and a virtual memory address (Process Address) of the process. The mapping table 3 maps this virtual memory area to a memory area of the linear memory 2 . The DRAM 2 also has an address and a data line, via which the memory can be accessed. As a rule, the MMU 1 also performs other tasks such as direct memory access (DMA) and memory block transfer, which are not shown in the drawing for clarity.
  • The size of the memory areas required by the processes varies: If the memory area of a process is to be changed, a control circuit (MMU control) 4 receives a corresponding request by means of MMU control signals. The MMU Control 4 is connected to an allocation table (All-Tab) 5 , in which information about the availability of the memory areas of the DRAM 2 is stored. The allocation table 5 contains allocation information “used” or “available” for each memory area.
  • If the memory area of a process is to be enlarged, the MMU Control 4 looks up in the allocation table 5 whether there is still memory capacity available. If no storage area is available, the process request is rejected or a storage area is moved to another storage medium, not shown. This can be, for example, a larger, external memory, but the processing speed is usually slower. If it is determined from the allocation information that memory areas are still available, a memory area is allocated to the process in accordance with the requirement. For this purpose, the address space of the process is enlarged and the mapping table 3 is expanded accordingly. Furthermore, this memory area is marked in the allocation table 5 as "used". If the memory area of a process is to be reduced, the associated entry in the mapping table 3 is deleted and the memory area in the allocation table 5 is marked as "available".
  • The allocation table 5 is connected via a control line 7 to a driver circuit (refresh control unit) 6 which periodically updates the memory content of the DRAM 2 line by line (refresh). For this purpose, the rows of the DRAM 2 are addressed in succession using the column address and a refresh signal is applied for an update time t R. During the refresh, the memory contents of the line are read out and saved again. If the refresh fails, the memory contents of the volatile memory are lost, as described above. However, not all memory areas are always used during the operation of the DRAM 2 , so that the memory contents of one or more memory areas are no longer required in the meantime. This allocation information is fed to the RCU 6 via the control line 7 from the allocation table 5 . If all the memory elements for which a refresh is to be carried out on one piece are in a memory area, the values of which are no longer required at this point in time, the refresh can be omitted for this area. The omission of a refresh does not mean that the RCU 6 then immediately carries out the following necessary refresh. Rather, the RCU 6 is then in an idle state for the update time, so that power can be saved.
  • A flow chart of the method according to the invention shown in Fig. 4 for operation of the DRAM. 2 If the RCU is to perform a refresh, it is decided on the basis of the allocation information from the allocation table whether the line to be updated belongs to a memory area used. In the case of allocation information “used”, the refresh is carried out, while in the case of allocation information “available” the RCU is in an idle state. This sequence is repeated one after the other for each line n, with nmax starting again with the first line after the last line.
  • The MMU 1 usually manages the memory areas of the DRAM 2 in such a way that several lines of the DRAM 2 are combined to form a block or memory area. Then only 1 allocation information is stored in the allocation table 5 as to whether this entire memory area is used or available. Due to the line-by-line update of the DRAM 2 , the RCU 6 can then omit a corresponding number of refreshes in the case of a memory area marked as "available" which comprises several lines. This granularity of the DRAM 2 is advantageously used when the MMU 1 manages several rows of the DRAM 2 in one memory area, since with each available memory area several refreshes can be omitted.
  • The RCU 6 does not necessarily have to be arranged in the MMU 1 , so in another exemplary embodiment the RCU is part of the linear memory. The RCU then only receives the information when the refresh should be carried out for a line. Likewise, the mapping table 3 and / or the allocation table 5 can be partially or completely stored in the linear memory 2 . The values of the table are then each read from the memory or are loaded into a smaller partial mapping table and / or allocation table.
  • Since the refresh process in digital circuit arrangements with a linear memory according to the invention has a large share in the current consumption of the circuit arrangement, the use of the method or circuit arrangement according to the invention enables a considerable reduction in power consumption. Reference numeral 1 memory control unit
    2 memory
    3 Figure table
    4 Memory management for the control circuit
    5 Allocation table
    6 driver circuit
    7 control line

Claims (10)

1. A method for operating a linear memory (DRAM, 2) by means of a memory control unit (MMU, 1), characterized in that only periodical updates of the memory areas of the linear memory (DRAM, 2) by a driver circuit (RCU, 6) are used Memory areas are updated.
2. The method according to claim 1, characterized in that information about the availability of memory areas of the linear memory (DRAM, 2) is stored in an allocation table ( 5 ) and this allocation information is supplied to the driver circuit (RCU, 6).
3. The method according to claim 2, characterized, that the driver circuit (RCU, 6) when receiving a Allocation information "Uses" the refresh of the carries out the respective memory area and upon receipt of a Allocation information "Available" during the Update time of the respective memory area the update (Refresh) not performed.
4. The method according to claim 1, characterized in that information about the availability of memory areas of the linear memory (DRAM, 2) is stored in an allocation table ( 5 ), allocation information about the available memory areas and the driver circuit are supplied to the driver circuit (RCU, 6) (RCU, 6) upon receipt of allocation information "available" is put into a quiescent state during the update time of the respective memory area.
5. Digital circuit arrangement with at least one linear Memory (DRAM, 2) and a memory control unit (MMU, 1) for the allocation of memory areas of the linear memory (DRAM, 2) to coupled data processing circuits, characterized, that a driver circuit (RCU, 6) for periodic Update only the used memory areas of the linear Memory (DRAM, 2) is provided.
6. Digital circuit arrangement according to claim 5, characterized in that an allocation table ( 5 ) for storing information about the availability of memory areas of the linear memory ( 2 ) via a control line ( 7 ) with the driver circuit (RCU, 6) is connected.
7. Digital switching arrangement according to claim 6, characterized, that the driver circuit (RCU, 6) when receiving a Allocation information "Used" is active, and when receiving a Allocation information "Available" is in an idle state.
8. Digital circuit arrangement according to one of the preceding Expectations, characterized, that the linear memory (DRAM, 2) several distributed DRAM Has modules.
9. Digital circuit arrangement according to claim 8, characterized in that a common allocation table ( 5 ) is provided.
10. Digital circuit arrangement according to one of the preceding Expectations, characterized, that multiple driver circuits (RCU, 6) for one shared, parallel refresh of the DRAM modules provided are.
DE2002111570 2002-03-15 2002-03-15 Method of running linear store e.g. for processor systems, requires updating used storage zones via driver circuit Ceased DE10211570A1 (en)

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DE2002111570 DE10211570A1 (en) 2002-03-15 2002-03-15 Method of running linear store e.g. for processor systems, requires updating used storage zones via driver circuit

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DE2002111570 DE10211570A1 (en) 2002-03-15 2002-03-15 Method of running linear store e.g. for processor systems, requires updating used storage zones via driver circuit

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0820065A2 (en) * 1996-07-15 1998-01-21 Motorola, Inc. Dynamic memory device with refresh circuit and refresh method
US5928365A (en) * 1995-11-30 1999-07-27 Kabushiki Kaisha Toshiba Computer system using software controlled power management method with respect to the main memory according to a program's main memory utilization states

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5928365A (en) * 1995-11-30 1999-07-27 Kabushiki Kaisha Toshiba Computer system using software controlled power management method with respect to the main memory according to a program's main memory utilization states
EP0820065A2 (en) * 1996-07-15 1998-01-21 Motorola, Inc. Dynamic memory device with refresh circuit and refresh method

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
KAI, K. *
MURAKAMI, K.: Optimizing the DRAM refresh count for merged DRAM/logic LSIs Proceedings of International Symposium on Low Power Electronics and Design, 1998, S. 82-87 *
OHSAWA, T. *

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