DE102021205516A1 - METHOD FOR MANUFACTURING VERTICAL SEMICONDUCTOR DEVICE AND VERTICAL SEMICONDUCTOR DEVICE - Google Patents

Abstract

A method for manufacturing a vertical semiconductor component (100) is provided, the method comprising: forming a gallium nitride layer system (15, 16, 17) on or over a first side of a substrate (61); Forming a front-side contact structure (21, 41) on or above the gallium nitride layer system (15, 16, 17), the front-side contact structure (21, 41) having at least a first electrode structure (41) and a second electrode structure (21) which are electrically separated from each other are isolated; Forming a backside contact structure (52) on or over a second side of the substrate (61), which is opposite the first side, and/or on or over the gallium nitride layer system (15, 16, 17) at the second side, the backside contact structure ( 52) is electrically isolated from the first electrode structure (42) and the second electrode structure (21); Applying a carrier support (101) on or over the rear-side contact structure (52) by means of a joining material (112), the carrier support (101) having a step structure (111) which is set up in such a way that the carrier support (101) is free or essentially is free of the step structure (111) in the area of a desired separation point (72, 402) of the gallium nitride layer system (15, 16, 17) and/or the substrate (61); Processing the gallium nitride layer system (15, 16, 17) and/or the substrate (61); and removing part of the carrier support (101) such that the area of the intended separation point (72, 402) is free or substantially free of the carrier support (101).

Description

State of the art

Transistors based on gallium nitride (GaN) offer the possibility of realizing components with lower on-resistances and at the same time higher breakdown voltages than comparable components based on silicon or silicon carbide.

GaN transistors are primarily known for what are known as high-electron mobility transistors (HEMTs), in which the current flow takes place laterally on the top side of the substrate through a two-dimensional electron gas that forms the transistor channel. Such lateral components can be produced by heteroepitaxy of the functional GaN layers on silicon wafers. However, for high breakdown voltage with small on-resistance per unit area, vertical devices, in which the current flows from the front of the substrate to the back of the substrate, are more advantageous in terms of both the size and the electric field distribution inside the device. Such a component cannot be produced directly using heteroepitaxial GaN layers on silicon (Si), since insulating intermediate layers (a so-called buffer) are required to adapt the lattice mismatch between GaN and Si and to reduce the substrate curvature.

The buffer itself is mechanically strained in such a way that it just compensates for the strain of the GaN layers at room temperature. However, since the buffer is an insulator, the current flow from the front of the substrate to the back of the substrate is prevented by the buffer.

Native GaN substrates are also known on which the required additional epitaxial GaN layers of the device can be grown without the need for an insulating buffer. However, such GaN substrates are small (typically 50 mm in diameter) and expensive.

In order to reduce the transistor price per area element, it can be advantageous to use the available heteroepitaxial GaN layers on large silicon substrates. Vertical components (trench MOSFET, pn diode) are known for this purpose, in which the silicon substrate and the insulating buffer under the component are selectively removed, whereby a backside trench (backside trench) is formed in order to directly cover the backside of the drift zone of the component to be able to contact. 1 shows the basic structure of such a component 100 with an insulating buffer and rear side trench (here based on a trench MOSFET 100). The rear side trench can also be referred to below as a rear side cavern or rear side aperture.

As in 1 is illustrated, the following III-V nitride semiconductor layers (GaN with the exception of the buffer) are grown epitaxially on the silicon substrate 61 or generally the carrier substrate 61: the insulating buffer 13, a highly doped contact semiconductor layer with n conductivity 14, the low-doped n-conductive drift layer 15, a p-conductive body layer 16 and a highly doped n-conductive source contact layer 17.

Source contact layer 17 and body layer 16 are penetrated by a trench (trench), the side walls and bottom of which are separated from gate electrode 21 by a gate dielectric 22 . Source contact layer 17 and body layer 16 are contacted by a source electrode 41 which is separated from gate electrode 21 by an insulating layer 31 . At the rear, the silicon substrate 61 and the buffer 13 are removed by a rear-side trench 51, which ends in the highly doped contact semiconductor layer with n-type conductivity 14. This is contacted by a drain electrode 52 on the rear. In operation, a conductive channel is formed in the body layer 16 by applying a gate voltage to the gate electrode 21, through which a current flow from the source electrode 41 to the drain electrode 52 is permitted.

In 1 For simplicity, a transistor with three cells, ie three repeating structures, is illustrated. In a real transistor, there are typically a large number of such cells and are therefore effectively connected in parallel. Typical active areas are in the range of a few square millimeters, the remaining GaN layers have a thickness of a few micrometers. The drain electrode 52 can consist of multiple metallic layers.

In vertical power transistors based on GaN-on-Si, the active GaN layer, a few µm thick, is epitaxially grown on a Si substrate. The Si substrate is electrically insulating and is at least partially removed in order to allow a vertical flow of current in the finished chip, so that a rear side cavern 51 is formed. Separation of Si wafers with very thin membranes (a few µm thick) or very thin wafers (a few µm thick) is technically demanding with the known separation process, since the membrane or wafer can break quickly.

2A and 2 B show, in schematic cross-sectional views, a method common in the related art for forming a wafer with a plurality number of transistor chips into individual chips. 2A illustrates the transistor chip before dicing and 2 B illustrates the transistor chip after singulation. After being separated, the transistor chips can be picked off in order to be further processed using standard methods of assembly and connection technology. For this purpose, markings, so-called saw kerfs 72, are applied to the front in an area outside the active transistor area. These markings can, as in 2A illustrated may be an etch in which portions of the insulating layer 31 are removed. Alternatively, additional layers are provided as a marking, for example in the form of a metallization that is not electrically connected to the source electrode 41 .

The marking of the sawing ditch 72 serves as a marker for the subsequent sawing or separating process. For this purpose, the wafer is applied to a so-called sawing film 71 (dice tape or bluetape), which is clamped in a frame. The wafer is then singulated along the sawing grooves 72 by means of a diamond-coated saw blade, so that a wider sawing street 73 is formed and isolated chips then remain on the sawing foil 71, which can then be picked off. In such a sawing process, the same sawing line can also be sawed several times to different depths, or different saw blades can also be used for different depths. Alternatively, the chips can also be separated using a laser, in which case the separation actually takes place using the laser, or using a so-called stealth-dice process, in which a type of predetermined breaking point is created using the laser, at which a subsequent lateral expansion occurs break the chips in half with the saw foil.

In the case of power semiconductors, the drain connection 52 is generally arranged on the underside of the chip (also referred to as the rear side). The drain connection is usually connected over an area to an electrically conductive material. The connection process takes place at the chip level, i.e. after the wafer has been separated into chips. The joining process is performed, for example, by means of sintering or soldering.

In the case of substrates 61 made of a very hard material, for example silicon carbide (SiC), only a low feed rate can be selected for the saw while the chips are being separated. If the feed speed of the saw is too high during separation, the substrate 61 may chip. However, a low feed of the saw causes high process costs. Laser dicing is a very expensive process and can cause damage to the material around the laser spot due to heating. Both separation methods are mechanically very stressful for the substrate 61 and the substrate 61 can mechanically fracture during the separation process.

Disclosure of Invention

Advantages of the Invention

The inventive method for producing a vertical semiconductor device with the features of claim 1 has the advantage of removing the substrate and the buffer layers from a GaN-on-Si wafer by clearly an additionally applied, graded metal foil, such as copper, molybdenum or Tungsten or corresponding layer combinations, is provided on the vertical semiconductor component before the singulation process. The graded metal foil is joined to the rear side of the wafer, which has a multiplicity of vertical semiconductor components, for example by means of silver technology or diffusion soldering, before the multiplicity of vertical semiconductor components is separated. Thus, the wafer can be handled more easily for the singulation process. Before the singulation process, for example a wafer sawing process, the upper layer of the stepped metal foil is removed. As a result, intended separation points, for example saw lines, are exposed between adjacent vertical semiconductor components on the wafer.

A stepped metal foil (also referred to as a carrier support with a stepped structure) is clearly provided in wafer format. The graded metal foil is formed, for example, from copper, molybdenum, tungsten or a corresponding combination of layers. After the end of the semiconductor processing, for example after a partial removal of the substrate from the rear side of the wafer, the stepped metal foil can be applied to the wafer by means of silver technology or diffusion soldering.

The space between chips, for example a desired separation point between adjacent chips, for example the area of the subsequent sawing line, can be free of metal foil or only partially connected to the metal foil. This allows each chip to be stabilized individually. This enables chipping or wafer cracking of the substrate to be reduced or prevented. The chips can be separated by sawing, breaking or laser dicing of the intended separation point. Manufacturing costs can be reduced as a result.

Developments of the aspects and advantageous configurations of the vertical semiconductor component are described in the dependent claims and the description.

character list

• 1 eine schematische Darstellung eines Membran-Transistors der bezogenen Technik;
• 2A und 2B schematische Darstellungen eines vertikalen Feldeffekttransistors der bezogenen Technik; und
• 3 bis 4B schematische Darstellungen eines vertikalen Halbleiterbauelements gemäß verschiedenen Aspekten.

Embodiments of the invention are shown in the figures and are explained in more detail below. Show it:

• 1 a schematic representation of a membrane transistor of the related art;
• 2A and 2 B schematic representations of a related art vertical field effect transistor; and
• 3 until 4B schematic representations of a vertical semiconductor device according to various aspects.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It is understood that the features of the various exemplary embodiments described herein can be combined with one another unless specifically stated otherwise. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. In the figures, identical or similar elements are provided with identical reference symbols, insofar as this is appropriate.

In the following description, various aspects and embodiments of a vertical semiconductor component are described using a trench MOSFET as an example. However, it goes without saying that the use of the stepped metal foil for processing the rear side of a semiconductor component is not limited to a trench MOSFET, so that in principle any vertical semiconductor components can be produced using this technology, such as Schottky diodes, pn diodes, vertical Diffusion MOSFETS (VDMOS), Current-Aperture Vertical Electron Transistors (CAVETs), vGroove Vertical High Electron Mobility Transistors (vHEMTs) or Fin Field Effect Transistors (FinFETs).

Description of the embodiments

3 FIG. 12 illustrates, in a schematic cross-sectional view, a stepped metal foil 101, which is also referred to as a carrier support 101, which is applied to the rear side of the vertical semiconductor device wafer before the vertical semiconductor devices 100 are singulated. In other words, a multitude of the in 3 The illustrated vertical semiconductor device 100 is mounted on a common substrate 61 (in 3 not illustrated). This structure is referred to as a vertical semiconductor device wafer. The carrier support 101 is set up to carry (in 3 not illustrated).

The carrier support 101 can have a step structure 111 on a foil 110, for example a metal foil, which is coupled to the rear side of the vertical semiconductor component wafer by means of a joining material 112 (in 3 illustrated by the arrow).

The foil 110 can have or be formed from copper, molybdenum, tungsten or a corresponding combination of layers.

The stepped structure 111 can be set up in such a way that the areas of the intended separation points, for example the saw ditches 72 (see 2A) are free of step structure 111. At least part of the foil 110 can be the removed part of the carrier support 101.

The substrate 61 may be a semiconductor substrate such as Si, SiC, or GaN; or a non-conductive substrate, e.g. alumina, e.g. sapphire.

Alternatively, the carrier support 101 can have a step structure 111 on a foil 110 . The step structure 111 can have at least a first step structure 111 and a second step structure 111 which are mechanically connected to one another by means of the foil 110 . The first step structure 111 can be coupled to the first electrode structure 42 by means of the joining material 112 and the second step structure 111 can be coupled to the second electrode structure 23 by means of the joining material 112 . At least part of the foil 110 can be the removed part of the carrier support 101 .

The joining material 112 can be designed to be electrically conductive, for example a silver paste. This allows contacting of the drain electrode 52 of the separated vertical semiconductor component on a printed circuit board (not illustrated) by a step structure 111 remaining on the back (and by the joining material 112). The metal foil 101 can be applied to the semiconductor component wafer 100 by means of silver sintering technology or diffusion soldering, for example. For this purpose, the metal foil 110 can have the joining material 112, for example a silver sintering paste or electrolytic tin, which is arranged on the step structure 111, so that the joining material 112 is arranged between the step structure 111 and the semiconductor component wafer 100. For example, the step structure 111 is coated with the joining material 112 .

The metal foil 110 coated with joining material 112 and having a stepped structure 111 can be applied to the semiconductor component wafer 100 by means of pressure and/or temperature, for example joined.

During the application of the metal foil 101 to the rear side of the semiconductor component wafer 100, the semiconductor component wafer 100 can be supported on the front side by a carrier material, for example a further carrier carrier.

In various embodiments, the metal foil 110 and the step structure 111 are formed in one piece, for example as a structured metal foil 101. The flat foil portion 110 of the metal foil 101 can be removed by means of a chemical and/or mechanical removal process, for example chemical-mechanical polishing, so that only or essentially only the stepped structure portion 111 of the metal foil 101 remains on the back of the vertical semiconductor component 100. During the removal process, the vertical semiconductor device 100 can be mechanically stabilized (not illustrated) by means of another carrier support that is applied on the front side of the vertical semiconductor device wafer.

As an example, the metal foil 110 may be removed using an abrasive process, such as chemical and/or mechanical polishing. This can make it possible for there to be no or only a few metal connections between the individual chips before singulation. When metal foil 110 is removed, semiconductor device wafer 100 can be mechanically stabilized by having a further carrier, for example a sawing film or another carrier carrier, on the front side of semiconductor device wafer 100 on the front side contact structure, for example source electrode 41 and/or the Gate electrode 23 are applied. After mechanically stabilizing the semiconductor device wafer 100, the chips can be singulated. In various embodiments, the singulation may occur before the metal foil 110 is removed from the backside.

The singulation method can be one or a combination of sawing with a saw, laser cutting with a laser and breaking with an elastic carrier support on the front-side contact structure. For example, the singulation method may be saw scribing followed by laser stealth dicing and then breaking the semiconductor device wafer 100 .

4A illustrates a supervision and 4B illustrates a schematic cross-sectional view along the in 4A Illustrated line 400 of a semiconductor device wafer 100 with a plurality of vertical semiconductor devices and a carrier support 101 according to various embodiments. In 4B 1 is illustrated step structure 111 and metal foil 110 of carrier support 101 bonded to the backside of semiconductor device wafer 100 . In this case, the carrier support 101 is connected to the rear side of the semiconductor component wafer 100 by means of the joining material, which in 4B however, is not illustrated.

In various embodiments, target separation points 402 can be defined in the substrate and/or the gallium nitride layer system, for example by locally removing or mechanically weakening material of the substrate using a plasma process.

The metal foil 110 can be removed, for example reduced, to such an extent that only the step structure 111 remains on the semiconductor component wafer 100 . Target separation points 402, for example sawing lines, can be exposed between the steps of the step structure 111. In this state, the semiconductor device wafer 100 can be sawed and the semiconductor devices can be singulated.

• In verschiedenen Ausführungsformen weist das Verfahren zum Herstellen eines vertikalen Halbleiterbauelement-Wafers 100 ein Ausbilden eines Galliumnitrid-Schichtensystems 15, 16, 17 auf oder über einer ersten Seite eines Substrats 61 auf. Das Verfahren weist ein Ausbilden einer Vorderseitenkontaktstruktur 23, 41 auf oder über dem Galliumnitrid-Schichtensystem 15, 16, 17 auf. Die Vorderseitenkontaktstruktur 23, 41 weist mindestens eine erste Elektrodenstruktur 41 und eine zweite Elektrodenstruktur 23 auf, die elektrisch voneinander isoliert sind. Das Verfahren weist ein Ausbilden einer Rückseitenkontaktstruktur 52 auf oder über einer zweiten Seite des Substrates 61, die der ersten Seite gegenüberliegt, und/oder auf oder über dem Galliumnitrid-Schichtensystem 15, 16, 17 bei der zweiten Seite auf. Die Rückseitenkontaktstruktur 52 ist von der ersten Elektrodenstruktur 42 und der zweiten Elektrodenstruktur 23 elektrisch isoliert. Das Verfahren weist ein Aufbringen eines Carrierträgers 101 auf oder über der Rückseitenkontaktstruktur 52 mittels eines Fügematerials 112 auf. Der Carrierträger 101 weist eine Stufenstruktur 111 auf, die derart eingerichtet ist, dass der Carrierträger 101 frei ist oder im Wesentlichen frei ist von der Stufenstruktur 111 im Bereich einer Soll-Trennstelle 402 des Galliumnitrid-Schichtensystems 15, 16, 17 und/oder des Substrates 61. Das Verfahren weist ferner ein Bearbeiten des Galliumnitrid-Schichtensystems 15, 16, 17 und/oder des Substrates 61 auf. Das Verfahren weist ein Entfernen eines Teils des Carrierträgers 101 derart auf, dass der Bereich der Soll-Trennstelle 402 frei ist oder im Wesentlichen frei ist von dem Carrierträger 101.

In other words:

• In various embodiments, the method for manufacturing a vertical semiconductor device wafer 100 includes forming a gallium nitride layer system 15 , 16 , 17 on or over a first side of a substrate 61 . The method includes forming a front-side contact structure 23, 41 on or above the gallium nitride layer system 15, 16, 17. The front-side contact structure 23, 41 has at least a first electrode structure 41 and a second electrode structure 23, which are electrically insulated from one another. The method includes forming a backside contact structure 52 on or over a second side of the substrate 61 opposite the first side and/or on or over the gallium nitride layer system 15, 16, 17 at the second side. The rear contact structure 52 is electrically isolated from the first electrode structure 42 and the second electrode structure 23 . The method includes applying a carrier support 101 to or above the rear-side contact structure 52 by means of a joining material 112 . The carrier support 101 has a step structure 111 which is set up in such a way that the carrier support 101 is free or essentially free of the step structure 111 in the area of a desired separation point 402 of the gallium nitride layer system 15, 16, 17 and/or the substrate 61. The method also includes processing the gallium nitride layer system 15, 16, 17 and/or the substrate 61. The method includes removing part of the carrier support 101 in such a way that the area of the intended separation point 402 is free or essentially free of the carrier support 101.

The procedure can be carried out in the order mentioned above. In various embodiments, the method can have further features, for example one or more intermediate steps before, after or between the aforementioned method steps.

If the substrate 61 has been completely removed, at least locally, so that the GaN layer system 15, 16, 17 is exposed on the back, there can clearly no longer be a second side of the substrate 61. The rear side of the semiconductor device wafer 100 is processed, for example forming the rear side electrode structure, from the direction of the second side of the substrate 61 (which may previously have been present) or in other words “on the second side of the substrate 61 and/or on or above a Side of the gallium nitride layer system 15, 16, 17, which is opposite the first side of the substrate 61.

The backside contact structure 52 may include a third electrode structure 52 . The third electrode structure 52 is electrically insulated from the first electrode structure 42 and the second electrode structure 23 .

The vertical semiconductor device wafer 100 may be a vertical transistor 100 . In this case, the first electrode structure 41 is a source electrode 41 or a drain electrode, the second electrode structure 23 is a gate electrode 23 and the rear side contact structure 52 or the third electrode structure 52 is a drain electrode 52 or a source -Electrode. The method can include electrically contacting the first electrode structure 42 , the second electrode structure 23 and the rear-side contact structure 52 or the third electrode structure 52 with a printed circuit board 71 .

In various embodiments, the method alternatively or additionally includes forming a front-side contact structure on or above the gallium nitride layer system 15, 16, 17, the front-side contact structure having a first electrode structure of a first vertical semiconductor component and a second electrode structure of a second vertical semiconductor component. A predetermined separation point is arranged (laterally) between the first electrode structure and the second electrode structure or is formed there. The method further includes forming a backside contact structure on or over a second side of the substrate 61 opposite the first side and/or on or over the gallium nitride layer system 15, 16, 17 at the second side. The backside contact structure is electrically isolated from the frontside contact structure. The backside contact structure has a third electrode structure of the first vertical semiconductor component and a fourth electrode structure of the second vertical semiconductor component. The intended separation point is arranged (laterally) between the third electrode structure and the fourth electrode structure. The method includes the application of the carrier support 101 on or over the rear-side contact structure using the joining material 112 . The carrier support 101 is set up in such a way that the third electrode structure is coupled to the fourth electrode structure. The method comprises processing, from the first side of the substrate 61, at least one of the gallium nitride layer system (15, 16, 17), the substrate (61) and the front-side contact structure. The method includes removing part of the carrier support 101 in such a way that the third electrode structure and the fourth electrode structure are at least electrically insulated from one another after the removal.

The carrier support 101 has, for example, a stepped structure 111 that is set up in such a way that the carrier support 101 is free or essentially free of the Step structure 111. The method also includes processing the gallium nitride layer system 15, 16, 17 and/or the substrate 61. The method includes removing part of the carrier support 101 in such a way that the area of the intended separation point 402 is free or essentially free of the carrier support 101.

Clearly, the method can be used to singulate a number of vertical semiconductor components that are arranged on a common semiconductor component wafer. In this case, the first vertical semiconductor component and the second vertical semiconductor component can be controlled semiconductor components, for example transistors, or uncontrolled semiconductor components, for example diodes. If the first semiconductor device and the second semiconductor device are each a diode, the first electrode structure and the second electrode structure is an anode electrode and the third electrode structure and the fourth electrode structure is a cathode electrode, or vice versa.

The method of any of the embodiments described above may include separating the target separation point 402 such that the first vertical semiconductor device and the second vertical semiconductor device are singulated. A desired separation point, which is set up for dicing the semiconductor component—for example a sawing line or a breaking edge, can be arranged between adjacent steps or step structures of the step structure 111 .

In one of the embodiments described above, the processing can include, for example, at least removing part of the substrate 61 . The removal can take place, for example, in such a way that a rear-side cavern 51 is formed below the first electrode structure and the second electrode structure. Alternatively, the processing can be done in such a way that the substrate 61 is completely removed. The backside contact structure 52 is formed after removing the portion of the substrate 61 in various embodiments.

The joining material 112 can be electrically conductive, for example a silver, tin or copper sinter paste, or electroplated silver, tin or copper.

The gallium nitride layer system 15, 16, 17 can have, for example, at least one drift layer 17, a p-doped gallium nitride layer 15, 16 and an n-doped gallium nitride layer 16, 15.

The rear side contact structure 52 can be in direct contact with the gallium nitride layer system 15, 16, 17 at least in one area.

The carrier support 101 can have, for example, a step structure 111 on a foil 110, a first step structure of the step structure 111 being coupled to the third electrode structure of the first vertical semiconductor component by means of the joining material 112 and a second step structure of the step structure 111 to the fourth electrode structure of the second vertical semiconductor component is coupled. The stepped structure 111 is set up in such a way that the rear-side contact structure 52 is free from physical contact with the carrier support 101 in the area of the intended separation point 402. In this case, at least part of the film 110 is the removed part of the carrier support 101. A or the intended Separation point can be arranged between adjacent (partial) step structures of the step structure, for example laterally between the first step structure and the second step structure.

The front-side contact structure 23, 42 can be applied to a carrier material, for example another carrier carrier, before the carrier carrier 101 is applied; and wherein the carrier material is removed before the gallium nitride layer system 15, 16, 17 and/or the substrate 61 is processed.

A desired separation point, which is set up for dicing the semiconductor component—for example a sawing line or a breaking edge, can be arranged between adjacent steps or step structures of the step structure 111 .

In at least one method step, the vertical semiconductor component wafer 100 can have: a gallium nitride layer system 15, 16, 17 on or above a first side of a substrate 61; a front-side contact structure on or above the gallium nitride layer system 15, 16, 17, the front-side contact structure having at least a first electrode structure and a second electrode structure which are electrically insulated from one another; a backside contact structure on or over a second side of the substrate 61, which is opposite the first side, and/or on or over the gallium nitride layer system 15, 16, 17 on the second side, the backside contact structure being electrically isolated from the first electrode structure and the second electrode structure is isolated; a carrier support 101 on or above the rear-side contact structure, which is mechanically coupled to the rear-side contact structure by means of a joining material 112, wherein the carrier support 101 has a step structure 111 which is set up in such a way that the carrier support 101 is free or is essentially free of the step structure 111 in the area of a desired separation point 402 of the gallium nitride layer system 15, 16, 17 and/or the substrate 61.

The embodiments described and shown in the figures are only chosen as examples. Different embodiments can be combined with one another completely or in relation to individual features. Also, an embodiment by features of a further From form of leadership to be supplemented. Furthermore, method steps described can be repeated and carried out in a different order than in the order described. In particular, the invention is not limited to the specified method.

Claims (18)

A method of manufacturing a vertical semiconductor device (100), the method comprising: forming a gallium nitride layer system (15, 16, 17) on or over a first side of a substrate (61); Forming a front contact structure (21, 41) on or above the gallium nitride layer system (15, 16, 17), wherein the Front side contact structure (21, 41) has at least a first electrode structure (41) and a second electrode structure (21) which are electrically isolated from each other; Forming a backside contact structure (52) on or over a second side of the substrate (61), which is opposite the first side, and/or on or over the gallium nitride layer system (15, 16, 17) at the second side, the backside contact structure ( 52) is electrically isolated from the first electrode structure (42) and the second electrode structure (21); Application of a carrier support (101) on or above the Rear-side contact structure (52) by means of a joining material (112), the carrier support (101) having a step structure (111) which is set up in such a way that the carrier support (101) is free or essentially free of the step structure (111) in the area of a desired separation point (72, 402) of the gallium nitride layer system (15, 16, 17) and/or the substrate (61); Processing the gallium nitride layer system (15, 16, 17) and/or the substrate (61); and Removing part of the carrier support (101) in such a way that the area of the intended separation point (72, 402) is free or essentially free of the carrier support (101). procedure according to claim 1 , wherein the vertical semiconductor component (100) is a vertical transistor (100), wherein the first electrode structure (41) is a source electrode (41) or a drain electrode, the second electrode structure (21) is a gate electrode (21 ) and the rear contact structure (52) has a drain electrode (52) and a source electrode. Method according to one of Claims 1 or 2 , further comprising: forming the desired separation point, at least part of the substrate (61) and/or the gallium nitride layer system (15, 16, 17) being removed, and the desired separation point (72, 402) laterally next to a the first electrode structure (42) and the second electrode structure (21) is formed. A method of manufacturing a vertical semiconductor device (100), the method comprising: forming a gallium nitride layer system (15, 16, 17) on or over a first side of a substrate (61); Forming a front-side contact structure on or above the gallium nitride layer system (15, 16, 17), the front-side contact structure having a first electrode structure of a first vertical semiconductor component and a second electrode structure of a second vertical semiconductor component, with a desired separation point (72, 402) between the first electrode structure and the second electrode structure is arranged; Forming a backside contact structure on or over a second side of the substrate (61), which is opposite the first side, and/or on or over the gallium nitride layer system (15, 16, 17) on the second side, the backside contact structure being electrically separated from the frontside contact structure is isolated, and wherein the backside contact structure has a third electrode structure of the first vertical semiconductor device and a fourth electrode structure of the second vertical semiconductor device, wherein the predetermined separation point (72, 402) is arranged between the third electrode structure and the fourth electrode structure; Application of a carrier support (101) on or above the Rear-side contact structure by means of a joining material (112), the carrier support (101) being set up in such a way that the third electrode structure is coupled to the fourth electrode structure; and processing, from the first side of the substrate (61), at least one of the gallium nitride layer system (15, 16, 17), the substrate (61) and the front-side contact structure; and Removing part of the carrier support (101) in such a way that the third electrode structure and the fourth electrode structure are at least electrically insulated from one another after the removal. procedure according to claim 4 , further comprising: separating the target separation point (72, 402) so that the first vertical semiconductor device and the second vertical semiconductor device are singulated. Method according to one of Claims 1 until 5 , wherein the processing comprises at least removing a part of the substrate (61). procedure according to claim 6 , With a rear cavern (51) below the first elec Rodenstruktur and the second electrode structure is formed. procedure according to claim 6 , wherein the substrate (61) is completely removed. Method according to one of Claims 6 until 8th , wherein the backside contact structure (52) is formed after removing the part of the substrate (61). procedure according to claim 1 until 9 , wherein the gallium nitride layer system (15, 16, 17) has at least one drift layer (17), a p-doped gallium nitride layer (15, 16) and an n-doped gallium nitride layer (15, 16). Method according to one of Claims 1 until 10 , wherein the rear-side contact structure (52) is in direct contact with the gallium nitride layer system (15, 16, 17) at least in one area. Method according to one of Claims 1 until 11 , wherein the joining material (112) is electrically conductive. Method according to one of Claims 4 until 12 , wherein the carrier support (101) has a step structure (111) on a film (110), the step structure (111) having at least a first step structure (111) and a second step structure (111) which is mechanically connected by means of the film (110). are connected to one another, wherein the first step structure (111) is coupled to the third electrode structure (52) of the first vertical semiconductor component (100) by means of the joining material (112) and the second step structure (111) is coupled to the fourth electrode structure by means of the joining material (112). (52) of the second vertical semiconductor device (100); and at least part of the foil (110) is the removed part of the carrier support (101). procedure according to Claim 13 , wherein the intended separation point is arranged between adjacent step structures of the step structure (111). Method according to one of Claims 1 until 14 , wherein the processing has at least a removal of part of the substrate (61) and/or the gallium nitride layer system (15, 16, 17) in the area of the desired separation point (72, 402). Method according to one of Claims 1 until 15 , wherein the front-side contact structure (23, 42) is applied to a carrier material before the carrier carrier (101) is applied; and wherein the carrier material is removed before the processing of the gallium nitride layer system (15, 16, 17) and/or the substrate (61). Method according to one of Claims 13 until 16 , wherein the intended separation point (72, 402) is arranged between adjacent steps of the step structure (111). Vertical semiconductor device wafer (100) comprising: a gallium nitride layer system (15, 16, 17) on or over a first side of a substrate (61); a front-side contact structure (21, 41) on or above the gallium nitride layer system (15, 16, 17), the front-side contact structure (21, 41) having at least a first electrode structure (41) and a second electrode structure (21) which electrically insulates from one another are; a backside contact structure (52) on or over a second side of the substrate (61), which is opposite the first side, and/or on or over the gallium nitride layer system (15, 16, 17) on the second side, the backside contact structure (52 ) a third electrode structure (52) electrically isolated from the first electrode structure (42) and the second electrode structure (21); a carrier support (101) on or above the rear-side contact structure (52), which is mechanically coupled to the rear-side contact structure (52) by means of a joining material (112), wherein the carrier support (101) has a step structure (111) which is set up in such a way that the carrier support (101) is free or essentially free of the step structure (111) in the area of a desired separation point (72, 402) of the gallium nitride layer system (15, 16, 17) and/or the substrate (61).

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