DE102021108930B3 - Signalprüfung - Google Patents
Signalprüfung Download PDFInfo
- Publication number
- DE102021108930B3 DE102021108930B3 DE102021108930.1A DE102021108930A DE102021108930B3 DE 102021108930 B3 DE102021108930 B3 DE 102021108930B3 DE 102021108930 A DE102021108930 A DE 102021108930A DE 102021108930 B3 DE102021108930 B3 DE 102021108930B3
- Authority
- DE
- Germany
- Prior art keywords
- signal
- source
- test
- function
- destination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2839—Fault-finding or characterising using signal generators, power supplies or circuit analysers
- G01R31/2841—Signal generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102021108930.1A DE102021108930B3 (de) | 2021-04-09 | 2021-04-09 | Signalprüfung |
| US17/713,308 US12196803B2 (en) | 2021-04-09 | 2022-04-05 | Signal test |
| JP2022064352A JP2022161888A (ja) | 2021-04-09 | 2022-04-08 | 信号テスト |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102021108930.1A DE102021108930B3 (de) | 2021-04-09 | 2021-04-09 | Signalprüfung |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE102021108930B3 true DE102021108930B3 (de) | 2022-10-13 |
Family
ID=83361495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102021108930.1A Active DE102021108930B3 (de) | 2021-04-09 | 2021-04-09 | Signalprüfung |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US12196803B2 (https=) |
| JP (1) | JP2022161888A (https=) |
| DE (1) | DE102021108930B3 (https=) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100188097A1 (en) | 2009-01-23 | 2010-07-29 | Chinsong Sul | Fault testing for interconnections |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3449231B2 (ja) * | 1998-08-14 | 2003-09-22 | 日本電気株式会社 | シリアルデータ監視装置 |
| US6917916B2 (en) * | 2001-12-13 | 2005-07-12 | Motorola, Inc. | Method and apparatus for testing digital channels in a wireless communication system |
| EP2752768B1 (en) * | 2003-05-28 | 2016-11-02 | Polaris Innovations Limited | Error detection in a circuit module |
| US7945831B2 (en) * | 2008-10-31 | 2011-05-17 | Texas Instruments Incorporated | Gating TDO from plural JTAG circuits |
| JP2016025641A (ja) * | 2014-07-24 | 2016-02-08 | エヌ・ティ・ティ・コミュニケーションズ株式会社 | 通信システム、通信装置、データ通信方法、及びプログラム |
| US20160349320A1 (en) * | 2015-05-26 | 2016-12-01 | Qualcomm Incorporated | Remote bus wrapper for testing remote cores using automatic test pattern generation and other techniques |
| JP7204698B2 (ja) * | 2020-03-11 | 2023-01-16 | 株式会社東芝 | 故障検出回路及び半導体装置 |
-
2021
- 2021-04-09 DE DE102021108930.1A patent/DE102021108930B3/de active Active
-
2022
- 2022-04-05 US US17/713,308 patent/US12196803B2/en active Active
- 2022-04-08 JP JP2022064352A patent/JP2022161888A/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100188097A1 (en) | 2009-01-23 | 2010-07-29 | Chinsong Sul | Fault testing for interconnections |
Non-Patent Citations (1)
| Title |
|---|
| AKARE, U. [u.a.]: Performance of Simulink based SS-OFDM model for Broadband Wireless Access Network. In: Second International Conference on Emerging Trends in Engineering & Technology, 16-18 December 2009, pp. 1132 – 1137. |
Also Published As
| Publication number | Publication date |
|---|---|
| US20220326298A1 (en) | 2022-10-13 |
| JP2022161888A (ja) | 2022-10-21 |
| US12196803B2 (en) | 2025-01-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R012 | Request for examination validly filed | ||
| R016 | Response to examination communication | ||
| R018 | Grant decision by examination section/examining division | ||
| R020 | Patent grant now final | ||
| R082 | Change of representative |