DE102020122151A1 - SEMICONDUCTOR DEVICE AND METHOD - Google Patents

Abstract

In one embodiment, a device comprises: a first interconnect structure comprising metallization structures; a second interconnection structure comprising a bus bar; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor and the first transistor including an epitaxial source / drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization structures and the conductive via contacting the epitaxial source / drain region.

Description

PRIORITY CLAIM AND CROSS REFERENCE

This application claims priority from U.S. Provisional Patent Application No. 63 / 016,520 , filed April 28, 2020, which is incorporated herein by reference.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate and patterning the various layers of material using lithography to form circuit components and elements thereon.

The semiconductor industry is continuously improving the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum element size, so that more components can be integrated into a given area. However, as the minimum element sizes decrease, there are other problems that should be addressed.

Figure list

• 1 illustriert ein Beispiel von vereinfachten Nanostrukturfeldeffekttransistoren (Nano-FETs) nach einigen Ausführungsformen.
• 2 bis 14B sind verschiedene Ansichten von Zwischenstufen bei der Herstellung von Nano-FETs nach einigen Ausführungsformen.
• 15 bis 22 sind verschiedene Ansichten von Zwischenstufen bei der Herstellung von Halbleitervorrichtungen nach einigen Ausführungsformen.
• 23A bis 31 sind verschiedene Ansichten von Zwischenstufen bei der Herstellung von Halbleitervorrichtungen nach einigen anderen Ausführungsformen.
• 32A bis 40 sind verschiedene Ansichten von Zwischenstufen bei der Herstellung von Halbleitervorrichtungen nach einigen anderen Ausführungsformen.

Aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Indeed, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of explanation.

• 1 illustrates an example of simplified nanostructured field effect transistors (nano-FETs) according to some embodiments.
• 2 until 14B Fig. 14 are various views of intermediate stages in the fabrication of nano-FETs according to some embodiments.
• 15th until 22nd FIG. 12 are various views of intermediate stages in the manufacture of semiconductor devices in accordance with some embodiments.
• 23A until 31 FIG. 13 are various views of intermediate stages in the manufacture of semiconductor devices in accordance with some other embodiments.
• 32A until 40 FIG. 13 are various views of intermediate stages in the manufacture of semiconductor devices in accordance with some other embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples of implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course only examples that are not to be understood as restrictive. For example, in the description below, forming a first element or a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which further elements are formed between the first and second elements so that the first and second elements do not have to be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples. This repetition is for simplicity and clarity and does not by itself dictate any relationship between the various embodiments and / or configurations illustrated.

Furthermore, spatially relative terms such as “below”, “below”, “lower”, “above”, “upper” and the like may be used herein for ease of description to describe the relationship of an element or feature to one or more other element (s ) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or in operation in addition to the orientation illustrated in the figures. The device may be otherwise oriented (rotated 90 degrees or in a different orientation) and the spatially relative terms used herein may be construed accordingly.

According to various embodiments, a semiconductor device is formed having a device layer formed between two interconnect structures. The device layer comprises transistors, e.g. B. Nanostructure field effect transistors (Nano-FETs). One of the interconnection structure is at the front of the Device layer and includes conductive elements that connect the transistors of the device layer to form functional circuits. The other of the interconnect structure is at the back of the device layer and includes conductive elements that are used to provide power circuitry for the device layer. In particular, the rear interconnection structure comprises its own busbars for providing a reference voltage, supply voltage or the like for the functional circuits. Conductive vias are formed through the device layer and connect the conductive elements of the rear interconnect structure to the conductive elements of the front interconnect structure. The formation of such conductive vias allows the interconnect structures to be connected by conductive elements rather than semiconductor elements, which can improve the performance of the resulting semiconductor devices.

1 illustrates an example of simplified nano-FETs according to some embodiments. 1 Figure 13 is a three-dimensional sectional view with some elements of the nano-FETs omitted for clarity of illustration. The nano-FETs can be nanosheet field effect transistors (NSFETs), nanowire field effect transistors (NWFETs), gate-all-around field effect transistors (GAAFETs) or the like.

The nano-FETs comprise nanostructures 56 over a substrate 50 like about Finns 54 that differ from the substrate 50 extend. The nanostructures 56 are a semiconductor layer that serve as channel regions for the nano-FETs. Isolation regions 60 such as shallow trench isolation regions (STI regions) are above the substrate 50 and between adjacent ones of the fins 54 placed above and between adjacent isolation regions 60 can emerge. Even if the isolation regions 60 than from the substrate 50 are described / illustrated separately, the term “substrate” can refer to the substrate 50 alone or on a combination of the substrate 50 and the isolation regions 60 relate. The Finns are still there 54 as single, continuous materials as a substrate 50 illustrated, the Finns 54 and / or the substrate 50 however, may comprise a single material or multiple materials. In this context, the Finns refer 54 on the section that extends over and between the adjacent isolation regions 60 extends.

Gate structures 100 are about the nanostructures 56 wrapped. The gate structures 100 include gate dielectrics 102 and gate electrodes 104 . The gate dielectrics 102 are along upper surfaces; Sidewalls and lower surfaces of the nanostructures 56 and can extend along side walls and / or over top surfaces of the fins 54 extend. The gate electrodes 104 are located above the gate dielectrics 102 . The epitaxial source / drain regions 92 are on opposite sides of the gate structures 100 arranged. In embodiments in which multiple transistors are formed, the epitaxial source / drain regions can be 92 shared between different transistors. For example, adjacent epitaxial source / drain regions 92 by epitaxial growth or by coupling the epitaxial source / drain regions 92 be electrically coupled to a same source / drain contact, such as by fusing the epitaxial source / drain regions 92 . One or more interlayer dielectric (ILD) layers (explained in more detail below) are located over the epitaxial source / drain regions 92 and / or gate structures 100 , through the contacts (explained in more detail below) to epitaxial source / drain regions 92 and gate electrodes 104 are formed.

Some embodiments discussed herein are discussed in the context of nano-FETs using a gate-last process. In other embodiments, a gate-first process can be used. In addition, some embodiments consider aspects used in planar devices, such as in planar FETs or in fin field effect transistors (FinFETs).

1 reference also illustrates a cross section used in later figures. Cross section AA runs along a longitudinal axis of a nanostructure 56 and in a direction of, for example, current flow between the epitaxial source / drain regions 92 of a nano-FET. Successive figures relate to this reference cross-section for the sake of clarity.

2 until 14B Fig. 14 are various views of intermediate stages in the fabrication of nano-FETs according to some embodiments. 2 , 3 , 4th , 5A , 6A , 7A , 8A , 9A , 10A , 11A , 12A , 13A and 14B are three-dimensional views that have a similar three-dimensional view as 1 but showing a gate structure and two fins. 5B , 6B , 7B , 8B , 9B , 10B , 11B , 12B , 13B and 14B are cross-sectional views taken along reference cross-section AA in FIG 1 are illustrated. 5A , 6A , 7A , 8A , 9A , 10A , 11A , 12A , 13A and 14B are simplified three-dimensional views and do not show all elements of the corresponding 5B , 6B , 7B , 8B , 9B , 10B , 11B , 12B , 13B and 14B .

In 2 is a substrate 50 for forming nano-FETs. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, an insulator substrate (SOI substrate) or the like, which may be doped (e.g. with a p- or n-dopant) or undoped. The substrate 50 can be a wafer such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer or the like. The insulating layer is provided on a substrate, usually silicon or a glass substrate. Other substrates, such as a multilayer or gradient substrate, can also be used. In some embodiments, the semiconductor material of the substrate can be 50 Silicon; Germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

The substrate 50 has an n region 50N and a p-region 50P on. The n region 50N can serve to form n-devices like NMOS transistors, e.g. B. n-nano-FETs, and the p-region 50P can be used to form p-devices such as PMOS transistors, e.g. B. p-nano-FETs. The n region 50N can be physically different from the region 50P be separate (not separately illustrated), and any number of device elements (e.g., other active devices, doped regions, isolation structures, etc.) may be between the n-region 50N and the p-region 50P be arranged.

The substrate 50 can be lightly doped with a p- or n-impurity. The anti-punch-through implant (APT implant) can therefore be carried out on an upper portion of the substrate 50 to form an APT region. During the APT implant, dopants can be present in the n-region 50N and the p-region 50P be implanted. The dopants can have a conductivity type that opposes a conductivity type of source / drain regions, which is subsequently in the n-region 50N and the p-region 50P is formed. The APT region can extend under subsequently formed source / drain regions in the nano-FETs that are formed in subsequent processes. The APT region can be used to block the leakage from the source / drain regions into the substrate 50 to reduce. In some embodiments, the doping concentration in the APT region can range from about 10 ¹⁸ cm ^-3 to about 10 ¹⁹ cm ^-3 .

A multilayer stack 52 is above the substrate 50 educated. The multilayer stack 52 alternately comprises first semiconductor layers 52A and second semiconductor layers 52B . The first semiconductor layers 52A are formed from a first semiconductor material and the second semiconductor layers 52B are formed from a second semiconductor material. The semiconductor materials can each be selected from the candidate semiconductor materials of the substrate 50 be chosen. In the illustrated embodiment, the multilayer stack comprises 52 four layers of each of the first semiconductor layers 52A and the second semiconductor layers 52B . It should be recognized that the multilayer stack 52 any number of the first semiconductor layers 52A and the second semiconductor layers 52B may include.

In the illustrated embodiment, the second semiconductor layers 52B used channel regions for nano-FETs in the n-region 50N and the p-region 50P to build. The first semiconductor layers 52A are sacrificial layers (or dummy layers), which are removed in subsequent processing, around the upper surfaces and the lower surfaces of the second semiconductor layers 52B to be disclosed in both regions. The second semiconductor material of the second semiconductor layers 52B is a material suitable for n- and p-type nano-FETs, such as silicon, and the first semiconductor material of the first semiconductor layers 52A is a material that has a high etching selectivity from the etching of the second semiconductor material, such as silicon germanium.

In another embodiment, the first semiconductor layers 52A used to form channel regions for the nano-FETs in a region (e.g. the p-region 50P ), and the second semiconductor layers 52B are used to form channel regions for the nano-FETs in another region (e.g. the n-region 50N ). The first semiconductor material of the first semiconductor layers 52A may be suitable for p-nano-FETs, such as silicon _{germanium (e.g. Si x} Ge _1-x , where x can be in the range from 0 to 1), pure or essentially pure germanium, a III-V compound semiconductor , a II-VI compound semiconductor or the like, and the second semiconductor material of the second semiconductor layers 52B can be suitable for n-nano-FETs, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor or the like. The first semiconductor material and the second semiconductor material can have a high etching selectivity for the mutual etching, so that the first semiconductor layers 52A without removing the second semiconductor layers 52B in the n region 50N can be removed, and the second semiconductor layers 52B without removing the first semiconductor layers 52A in the p region 50P can be removed.

Each of the layers of the multilayer stack 52 can using a process such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD) or the like. Each of the layers may be formed to have a small thickness, such as a thickness in a range of about 5 nm to about 30 nm. In some embodiments, a group is layers (e.g., the second semiconductor layers 52B ) formed to be thinner than the other groups of layers (e.g. the first semiconductor layers 52A ). For example, in embodiments in which the second semiconductor layers 52B can be used to form channel regions and the first semiconductor layers 52A Sacrificial layers (or dummy layers) are the first semiconductor layers 52A be formed with a first thickness T ₁ and the second semiconductor layers 52B can be formed with a second thickness T ₂ , the second thickness T _{2 being} from about 30% to about 60% less than the first thickness T ₁ . Forming the second semiconductor layers 52B having a smaller thickness allows the channel regions to be formed with a higher density.

In 3 become trenches in the substrate 50 and the multilayer stack 52 etched to Finns 54 and nanostructures 56 to build. Finns 54 are semiconductor strips that are in the substrate 50 are structured. The nanostructures 56 comprise the remaining portions of the multilayer stack 52 to the Finns 54 . Specifically, include the nanostructures 56 alternating first nanostructures 56A and second nanostructures 56B . The first nanostructures 56A and the second nanostructures 56B are made up of remaining portions of the first semiconductor layers 52A or the second semiconductor layers 52B educated. After forming, the second are nanostructures 56B in the intermediate levels of the structure between two of the first nanostructures 56A arranged. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof, and can be done with masks 58 be executed, which is a structure of the fins 54 and the nanostructures 56 having. The etching can be anisotropic.

Finns 54 and the nanostructures 56 can be structured using any suitable method. For example, Finns 54 and the nanostructures 56 patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double structuring or multiple structuring processes combine photolithography and self-aligned processes, which allows the creation of structures that, for example, have spacings that are smaller than would otherwise be possible using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used as masks 58 used the Finns 54 and the nanostructures 56 to structure. In some embodiments, the masks 58 (or other layer) on the nanostructures 56 stay.

Finns 54 and the nanostructures 56 can have widths in a range from approx. 8 nm to approx. 40 nm. Finns 54 and the nanostructures 56 in the n region 50N and the p-region 50P are illustrated as being substantially equal widths for illustrative purposes. In some embodiments, the fins 54 and the nanostructures 56 in a region (e.g. the n-region 50N ) wider or narrower than the fins 54 and the nanostructures 56 the other region (e.g. the p-region 50P ).

STI regions 60 are then to the Finns 54 formed adjacent. The STI regions 60 can by depositing an insulating material over the substrate 50 and the nanostructures 56 and between adjacent ones of the fins 54 be educated. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, the like, or a combination thereof, and can be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by an acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide, which is formed by an FCVD process. An annealing process can be performed when the insulating material is formed. In one embodiment, the insulating material is formed so that excess insulating material masks 58 (if any) or the nanostructures 56 covers. Although the insulating material is illustrated as a single layer, embodiments can use multiple layers. For example, in some embodiments a liner may only be along surfaces of the substrate 50 , the Finn 54 and the nanostructures 56 are formed. A filler material such as that discussed above can then be formed over the liner.

A removal process is then applied to the insulating material to remove excess insulating material over the masks 58 (if present) or the nanostructures 56 to remove. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch back process, combinations thereof, or the like may be used. The planarization process lays the masks 58 (if any) or the nanostructures 56 open so that upper Areas of the masks 58 (if available) or the nanostructures 56 and the insulating material are coplanar (within the process variations) upon completion of the planarization process.

The insulating material is then cut out to cover the STI regions 60 to build. The insulating material is cut out so that at least a section of the nanostructures 56 from between neighboring STI regions 60 protrudes. In the illustrated embodiment, the top surfaces are the STI regions 60 (within the process variations) with the upper surfaces of the fins 54 coplanar. In some embodiments, the top surfaces are the STI regions 60 above or below the top surfaces of the fins 54 . Furthermore, the upper surfaces of the STI regions 60 a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The upper surfaces of the STI regions 60 can be formed flat, convex and / or concave by suitable etching. The STI regions 60 can be cut out using an acceptable etch process, such as one that is selective to the material of the insulating material (e.g., the insulating material of the STI regions 60 etches faster than the materials used in the Finns 54 and the nanostructures 56 ). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) can be applied.

The masks 58 (or other layer) can be used before, during or after the formation of the STI regions 60 removed. For example, the masks 58 by the etching processes that are used, the fins are removed 54 and the nanostructures 56 to structure, or by the etching processes that are used, the STI regions 60 cut out. In another embodiment, the masks 58 removed by another etching process after the STI regions 60 are cut out.

The process described above is just an example of how the Finns do 54 and the nanostructures 56 can be formed. In some embodiments, the fins 54 and the nanostructures 56 be formed by an epitaxial growth process. For example, a dielectric layer can be over a top surface of the substrate 50 can be formed and trenches can be etched through the dielectric layer to the underlying substrate 50 to disclose. Epitaxial structures can be built up epitaxially in the trenches and the dielectric layer can be cut out such that the epitaxial structures protrude from the dielectric layer around the fins 54 and the nanostructures 56 to build. The epitaxial structures may comprise the alternating semiconductor materials explained above, such as the first semiconductor material and the second semiconductor material. In embodiments in which epitaxial structures are built up epitaxially, the epitaxially built materials can be doped during the growth in place, which can mask previous and / or subsequent implants, but wherein in-situ and implant doping can be used together.

Furthermore, suitable wells can be found in the substrate 50 , the Finn 54 and / or the nanostructure 56 are formed. In some embodiments, a p-well can be in the region 50N can be formed and an n-well in the region 50P be educated. In another embodiment, p-wells or n-wells can be in the n-region 50N and the p-region 50P be educated.

In embodiments with different wave types, the different implantation steps for the n-region 50N and the p region 50P can be achieved using a photoresist or other mask. For example, a photoresist can be over the fin 54 , the nanostructures 56 and the STI regions 60 in the n region 50N are formed. The photoresist is structured, the p-region 50P to disclose. The photoresist can be formed using a spin-on technique and can be formed using acceptable photolithography techniques. When the photoresist is patterned, an n-impurity implantation takes place in the p-region 50P and the photoresist can serve as a mask to substantially prevent n-type impurities from entering the n-region 50N be implanted. The n-impurities can be phosphorus, arsenic, antimony, or the like, which are implanted ^{into the region at a concentration in the range of about 10 13} cm ^-3 to about 10 ¹⁴ cm ^-3. After implantation, the photoresist is removed, such as by an acceptable ash process.

After the implantation of the p-region 50P becomes a photoresist over the fins 54 , the nanostructures 56 and the STI regions 60 in the p region 50P educated. The photoresist is structured, p-region 50P to disclose. The photoresist can be formed using a spin-on technique and can be formed using acceptable photolithography techniques. If the photoresist is patterned, a p-type impurity can be implanted in the n-region 50N and the photoresist can act as a mask to substantially prevent p-type impurities from entering the p-region 50P be implanted. The n-impurities can be boron, boron fluoride, indium, or the like, which are implanted ^{into the region at a concentration in the range of about 10 13} cm ^-3 to about 10 ¹⁴ cm ^-3. After the implantation, the Photoresist can be removed, such as by an acceptable ash process.

After the n region implants 50N and the p-region 50P annealing can be performed to repair implant damage and activate the p and / or n impurities that have been implanted. In some embodiments, the built-up materials or epitaxial fins can be doped in place as they are grown, which can remove the implant doping, but in situ and implant doping can be used simultaneously.

In 4th becomes a dummy dielectric layer 62 on the Finns 54 and the nanostructures 56 educated. The dummy dielectric layer 62 For example, it can be silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or built up thermally using acceptable techniques. A dummy gate layer 64 will be over the dummy dielectric layer 62 and formed a mask layer 66 is over the dummy gate layer 64 educated. The dummy gate layer 64 can over the dummy dielectric layer 62 deposited and then planarized, such as by CMP. The mask layer 66 can over the dummy gate layer 64 to be deposited. The dummy gate layer 64 may be made of conductive or non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitride, metallic silicides, metallic oxides, and metals. The dummy gate layer 64 can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques to deposit the selected material. The dummy gate layer 64 may consist of one or more materials that have a high etch selectivity from the etching of insulating materials, e.g. B. the materials of the STI regions 60 and / or the dummy dielectric layer 62 . The mask layer 66 may comprise one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. This example uses a single dummy gate layer 64 and a single mask layer 66 over the n region 50N and the p-region 50P educated. Even if the dummy dielectric layer 62 the STI regions 60 should be shown covering, it should be noted that the dummy dielectric layer 62 can be formed in other ways. In some embodiments, such as when the dummy dielectric layer 62 is thermally built up, is the dummy dielectric layer 62 formed to only the Finns 54 and the nanostructures 56 to cover.

5A until 14B illustrate further intermediate stages in the manufacture of nano-FETs. 5B , 6B , 7B , 8B , 9B , 10B , 11B , 12B , 13B and 14B can for the n region 50N and the p region 50P are valid. Differences (if any) in the structures of the n-region 50N and the p-region 50P are described in the text accompanying each figure.

In the 5A and 5B is the mask layer 66 patterned using acceptable photolithography and etching techniques to form masks 76 to build. The structure of the masks 76 is then attached to the dummy gate layer using an acceptable etching technique 64 transferred to dummy gates 74 to build. The structure of the masks 76 can optionally also be applied to the dummy dielectric layer with an acceptable etching technique 62 transferred to dummy dielectrics 72 to build. The dummy gates 74 cover sections of the nanostructures 56 which are exposed in subsequent processing to form channel regions. Specifically, the dummy gates extend 74 along the sections of the nanostructures 56 that are used, channel regions 68 to build. The structure of the masks 76 can be used to set any of the neighboring dummy gates 74 physically separate. The dummy gates 74 can also have a longitudinal direction that is essentially at right angles (within the process limits) to the longitudinal directions of the fins 54 are. The masks 76 can optionally be removed after patterning, such as by an acceptable etching technique.

In 6A and 6B are gate spacers 80 over the nanostructures 56 and the Finns 54 on exposed side walls of the masks 76 , the dummy gates 74 and the dummy dielectrics 72 educated. The gate spacers 80 can be formed by conformally forming an insulating material and then etching the insulating material. The insulating material of the gate spacers 80 may be silicon nitride, silicon carbonitride, silicon oxycarbonitride, combinations thereof, or the like, and may be formed by thermal oxidation, deposition, a combination thereof, or the like. The gate spacers 80 may be formed from a single layer insulating material or multiple layers of insulating materials. In some embodiments, the gate spacers include 80 several layers of silicon oxycarbonitride each, wherein each layer can have a different composition of silicon oxycarbonitride. In some embodiments, the gate spacers include 80 one layer of silicon oxide each, which is arranged between two layers of silicon nitride. Other spacer structures can be formed. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etch such as RIE, NBE, or the like. After the etch, the gate spacer can 80 have straight side walls or curved side walls.

Before forming the gate spacer 80 implants can be carried out for lightly doped source / drain regions (LDD regions). In the embodiments with different device types, similar to the implants explained above, a mask, such as a photoresist, may be over an n-region 50N be formed while the p-region 50P is disclosed, and a suitable impurity (e.g. type p) can be present in the nanostructures 56 and the Finns 54 implanted in the p-region 50P are disclosed. The mask can then be removed. A mask, such as a photoresist, can then be applied over the p-region 50P while the n-region 50N is disclosed, and impurities of a suitable type (e.g., type n) can be incorporated into the nanostructures 56 and the Finns 54 that are in the n region 50N are disclosed, are implanted. The mask can then be removed. The n-impurities can be any of the n-impurities discussed above, and the p-impurities can be any of the p-impurities discussed above. The lightly doped source / drain regions can have a concentration of impurities in the range from approx. 10 ¹⁵ cm ^-3 to approx. 10 ¹⁹ cm ^-3 . Annealing can be used to repair the implant damage and activate the implanted impurities. The canal regions remain during the implantation 68 through the dummy gates 74 covered so that the canal regions 68 remain essentially free of the impurity implanted in the LDD regions.

It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be used, different step sequences can be used (e.g. further spacers can be formed and removed, etc.) and / or the like. Furthermore, the n and p devices can be formed using various structures and steps.

After the gate spacers 80 are then formed source / drain cutouts 82 in the nanostructures 56 educated. In the illustrated embodiment, the source / drain cutouts extend 82 through the nanostructures 56 to expose the Finns 54 . The source / drain cutouts 82 can also get into the substrate 50 and / or the Finns 54 extend. In other words, the source / drain cutouts 82 can only in the nanostructures 56 be formed as by 6A shown, or can also be in the Finns 54 be formed extensively, as in 6B shown. In various embodiments, the source / drain cutouts can be 82 from an upper surface of the substrate 50 extend without the substrate 50 to etch; the substrate 50 can be etched so that lower surfaces of the source / drain cutouts 82 under the upper surfaces of the STI regions 60 are arranged; or similar. The source / drain cutouts 82 can by etching the nanostructures 56 using anisotropic etching processes such as an RIE, an NBE, or the like. The gate spacers 80 and the masks 76 collectively mask portions of the nanostructures 56 , the Finn 54 , and the substrate 50 during the etching processes used to form the source / drain cutouts 82 . A single etch process can be used to create each of the nanostructures 56 to etch. In other embodiments, multiple etching processes can be used, the nanostructures 56 to etch. Timed etching processes can be used to etch the source / drain cutouts 82 stop after the source / drain cutouts 82 reach a desired depth D1. The depth D ₁ can be in the range from approx. 40 nm to approx. 140 nm.

Inner spacers 84 are optional on the sidewalls of the remaining sections of the first nanostructures 56A formed, e.g. B. the sidewalls through the source / drain cutouts 82 are disclosed. As will be explained in more detail below, source / drain regions are subsequently in the source / drain cutouts 82 formed, and the first nanostructures 56A are subsequently replaced by corresponding gate structures. The inner spacers 84 act as insulating elements between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the inner spacers 84 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as etching processes that are used to subsequently form the gate structures.

As an example of forming the inner spacers 84 can the source / drain cutouts 82 be expanded. In particular, sections of the side walls of the first nanostructures 56A going through the source / drain cutouts 82 exposed, cut out. Even if side walls of the first nanostructures 56A as just illustrated, the side walls can be concave or convex. The sidewalls can be cut out by an acceptable etching process, such as one that is selective to the material of the first nanostructures 56A is (e.g. selectively the material of the first nanostructures 56A etches faster than the material or materials of the second nanostructures 56B and the Finns 54 ). The etching can be anisotropic. For example, if the Finns 54 and the second nanostructures 56B are formed from silicon and the first nanostructures 56A made of silicon germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH ₄ OH), or the like. In another embodiment, the etching process can be a dry etching using a fluorine-based gas such as hydrogen fluoride (HF) gas. In some embodiments, the same etch process can be performed continuously to both the source / drain cutouts 82 train as well as the side walls of the first nanostructures 56A cut out. The inner spacers 84 can then be formed by conformally forming an insulating material and then etching the insulating material. The insulating material can be a material such as silicon nitride or silicon oxynitride, but any suitable material such as materials having a lower dielectric constant (low k) with a k less than about 3.5 can be used. The insulating material can be deposited by a conformal deposition process such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etch such as RIE, NBE, or the like. Even if the original outer side walls of the inner spacer 84 than flush with the side walls of the gate spacer 80 illustrated, the outer sidewalls of the inner spacers 84 over the side walls of the gate spacers 80 extend or be cut out from it. In other words, the inner spacers 84 can partially fill, fill completely, or overfill the sidewall cutouts. Furthermore, the side walls are the inner spacers 84 as just illustrated are the side walls of the inner spacers 84 however, they can also be concave or convex.

In 7A and 7B are epitaxial source / drain regions 92 in the source / drain cutouts 82 educated. The epitaxial source / drain regions 92 are in the source / drain cutouts 82 formed so that each of the dummy gates 74 between respective adjacent pairs of the source / drain epitaxial regions 92 is arranged. In some embodiments, the gate spacers 80 used to make the epitaxial source / drain regions 92 from the dummy gates 74 and the first nanostructures 56A to separate a suitable lateral distance so that the epitaxial source / drain regions 92 no short circuit can be formed with subsequently formed gates of the nano-FETs. The epitaxial source / drain regions 92 can come into contact with the inner spacers 84 (if present) be formed and can be located on side walls of the second nanostructures 56B extend past. The epitaxial source / drain regions 92 can use the second nanostructures 56B load and thus improve performance.

The epitaxial source / drain regions 92 in the n region 50N can by masking the p-region 50P are formed. Then the epitaxial source / drain regions 92 epitaxially in the source / drain cutouts 82 in the n region 50N built up. The epitaxial source / drain regions 92 can include any acceptable material suitable for n-type nano-FETs. For example, the epitaxial source / drain regions 92 in the n region 50N Include materials that have a tensile force in the canal regions 68 apply, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide or the like. The epitaxial source / drain regions 92 in the n region 50N may have surfaces that are from respective faces of the second nanostructures 56B and the Finns 54 are elevated and can have facets.

The epitaxial source / drain regions 92 in the p region 50P can by masking the n region 50N are formed. Then the epitaxial source / drain regions 92 epitaxially in the source / drain cutouts 82 in the p region 50P built up. The epitaxial source / drain regions 92 can include any acceptable material suitable for p-type nano-FETs. For example, the epitaxial source / drain regions 92 in the p region 50P Include materials that are compressive to the canal regions 68 exercise, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin or the like. The epitaxial source / drain regions 92 in the p region 50P may have areas that are different from respective areas of the second nanostructures 56B and the Finns 54 are raised and may have facets.

The epitaxial source / drain regions 92 , the second nanostructures 56B and / or the Finns 54 may be implanted with dopants to form source / drain regions, similar to the process previously used for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have an impurity concentration in the range from approximately 10 ¹⁹ cm ^-3 to approximately 10 ²¹ cm ^-3 . The n and / or p impurities for source / drain regions can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions can 92 be endowed locally during growth.

As a result of the epitaxial process that is used, the source / drain epitaxial regions 92 have upper surfaces of the epitaxial source / drain regions 92 Facets on that extend laterally outward over the faces of the second nanostructures 56B and the Finns 54 extend beyond. This is how the epitaxial source / drain regions point 92 a height H ₁ which is greater than the depth D _{1 of} the source / drain cutouts 82 is. For example, the height H _{1 can be} in the range from approx. 30 nm to approx. 120 nm. In some embodiments, adjacent source / drain epitaxial regions remain 92 in the p region 50P remain separate after the epitaxial process is complete, as in 7A is illustrated. In other embodiments, these facets cause adjacent source / drain epitaxial regions 92 of the same nano-FET to fuse. In the embodiments described in 7A and 7B As illustrated, the spacer etch that is used becomes the gate spacers 80 to form, adapted to remove the spacer material so that the epitaxial source / drain regions 92 on the upper surfaces of the STI regions 60 can extend. In another embodiment, the gate spacers are 80 formed, sections of the sidewalls of the nanostructures 56 cover that is across the STI regions 60 extend and thus epitaxial growth on the upper surfaces of the STI regions 60 To block.

The epitaxial source / drain regions 92 may comprise one or more layers of semiconductor material. For example, the epitaxial source / drain regions 92 comprise first semiconductor material layers, second semiconductor material layers, and third semiconductor material layers. Any number of semiconductor material layers can be used for the epitaxial source / drain regions 92 be used. Each of the first semiconductor material layers, the second semiconductor material layers and the third semiconductor material layers can be formed from different semiconductor materials and / or can be doped to different dopant concentrations. In some embodiments, the first semiconductor material layers may have a dopant concentration that is less than that of the second semiconductor material layers and greater than that of the third semiconductor material layers. In embodiments in which the epitaxial source / drain regions 92 comprise three semiconductor material layers, the first semiconductor material layers from the fins 54 be constructed, the second semiconductor material layers can be constructed from the first semiconductor material layers and the third semiconductor material layers can be constructed from the second semiconductor material layers.

In 8A and 8B is a first ILD 96 over the epitaxial source / drain regions 92 and the STI regions 60 educated. The first ILD 96 can be formed from a dielectric. Dielectrics can be oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG) or the like; Nitrides such as silicon nitride or the like. Other insulating materials can be used.

The first ILD 96 can by depositing a dielectric over the epitaxial source / drain regions 92 , the gate spacers 80 , the masks 76 (if available) or the dummy gates 74 and the STI regions 60 , and then planarizing the dielectric. The deposition can be done by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Other acceptable processes can be used to form the dielectric. The planarization can be done by any suitable method, such as a CMP, an etch-back process, combinations thereof, or the like. The planarization process levels the top surface of the first ILD 96 with the upper surfaces of the masks 76 or the dummy gates 74 a. The planarization process can also use the masks 76 at the dummy gates 74 and portions of the gate spacer 80 along side walls of the masks 76 remove. After the planarization process, the top surfaces are the first ILD 96 , the gate spacer 80 and the masks 76 (if available) or the dummy gates 74 coplanar (within the process variations). Accordingly, the top surfaces of the masks 76 (if available) or the dummy gates 74 through the first ILD 96 disclosed. In the illustrated embodiment, the masks remain 76 back and the planarization process the top surface of the first ILD 96 to the upper surfaces of the masks 76 aligns.

In some embodiments, a contact etch stop layer (CESL) 94 between the first ILD 96 and the epitaxial source / drain regions 92 , the gate spacer 80 and the STI regions 60 arranged. The CESL 94 may comprise a dielectric such as silicon nitride, silicon oxide, silicon oxynitride or the like, which has a high etch selectivity by etching the first ILD 96 having.

In 9A and 9B become the masks 76 (if available) and the dummy gates 74 removed in an etching process so that cutouts 98 are formed. Sections of the dummy dielectrics 72 in the clippings 98 can also be removed. In some embodiments, the dummy gates 74 removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process that uses one or more reactive gases that selectively define the dummy gates 74 etch at a faster rate than the first ILD 96 or the gate spacers 80 . During the removal can the dummy dielectrics 72 can be used as etch stop layers when the dummy gates 74 to be etched. The dummy dielectrics 72 can then after removing the dummy gate 74 removed. Every cutout 98 lays out sections of the canal regions 68 in the second nanostructures 56B open and / or superimposed on this. Sections of the second nanostructures 56B that are considered the canal regions 68 are between adjacent pairs of the epitaxial source / drain regions 92 arranged.

The remaining sections of the first nanostructures 56A are then removed to the cutouts 98 to remove. The remaining sections of the first nanostructures 56A can be removed by an acceptable etching process that selectively removes the material of the first nanostructures 56A etches faster than the materials of the second nanostructures 56B , Finns 54 and the STI regions 60 . The etching can be anisotropic. For example, if the Finns 54 and the second nanostructures 56B are formed from silicon and the first nanostructures 56A made of silicon germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH ₄ OH), or the like.

The exposed portions of the second nanostructures 56B and the Finns 54 are optionally cut back. The trimming reduces the thickness of the exposed portions of the second nanostructures 56B of the second thickness T ₂ (above with reference to 2 explained) to a third thickness T ₃ , the third thickness T _{3 being} in a range from approx. 3 nm to approx. 8 nm and the third thickness T _{3 being} between approx. 40% and approx. 70% less than the second thickness T2 . The trimming can be done at the same time as the cutouts are made 98 take place or after forming the cutouts 98 take place. For example, the exposed portions of the second nanostructures 56B and the Finns 54 can be tailored through an acceptable etching process that selectively selects the material (s) of the second nanostructures 56B and the Finns 54 etches at a faster rate than the materials of the first nanostructures 56A , the inner spacers 84 and the gate spacers 80 . The etching can be anisotropic. For example, if the Finns 54 and the second nanostructures 56B are formed from silicon and the first nanostructures 56A are formed from silicon germanium, the etching process may be a wet etching using a dilute ammonium hydroxide hydrogen peroxide mixture (APM), a sulfurous acid hydrogen peroxide mixture (SPM), or the like.

In 10A through 108 are gate dielectrics 102 and gate electrodes 104 formed for replacement gates. The gate dielectrics 102 are compliant in the cutouts 98 deposited, such as on top surfaces and side walls of the fins 54 and on top surfaces, sidewalls, and bottom surfaces of the second nanostructures 56B . The gate dielectrics 102 can also be used on upper surfaces of the first ILD 96 , the gate spacer 80 and the STI regions 60 to be deposited. The gate dielectrics 102 include one or more dielectric layers, such as an oxide, a metal oxide, a metal silicate, the like, or combinations thereof. In some embodiments, the gate includes dielectrics 102 Silicon oxide, silicon nitride, or several layers thereof. In some embodiments, the gate includes dielectrics 102 a high-k dielectric, and in these embodiments the gate dielectrics 102 have a k value greater than about 7.0 and comprise a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead and combinations thereof. The gate dielectrics 102 can be multilayered. For example, in some embodiments, the gate dielectrics 102 each comprise an interface layer of silicon oxide formed by thermal and chemical oxidation and a metal oxide layer over the interface layer. The method of formation of the gate dielectrics 102 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

The gate electrodes 104 are each above the gate dielectrics 102 arranged and fill the remaining sections of the cutouts 98 . The gate electrodes 104 can comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof or several layers thereof. For example, they are single-layer gate electrodes 104 illustrates the gate electrodes 104 however, may include any number of liner layers, any number of work function adjustment layers, and a filler material. Any combination of the layers that make up the gate electrodes 104 can represent in the areas between each of the second nanostructures 56B and between the Finns 54 and the second nanostructures 56B be secluded. The method of forming the gate electrodes 104 can include ALD, PECVD, and the like. After filling the cutouts 98 A planarization process such as a CMP can be performed to remove excess portions of the gate dielectric materials 102 and the gate electrodes 104 remove, leaving these excess sections over the top surfaces of the first ILD 96 and the gate spacer 80 are located. The remaining sections of the gate dielectric materials 102 and the gate electrodes 104 thus form replacement gates of the resulting nano-FETs. The gate dielectrics 102 and the gate electrodes 104 can be used collectively as gate structures 100 or “gate stack”.

The making of the gate dielectrics 102 in the region 50N and the region 50P can at the same time occur so that the gate dielectrics 102 are formed from the same materials in each region and the formation of the gate electrodes 104 can occur simultaneously, so that the gate electrodes 104 are formed from the same materials in each region. In some embodiments, the gate dielectrics 102 be formed in each region by its own process, making the gate dielectrics 102 can consist of different materials, and / or the gate electrodes 104 in each region can be formed by separate processes, so that the gate electrodes 104 can consist of different materials. Different masking steps can be used to mask and reveal appropriate regions using separate processes.

In 11A and 11B are source / drain contact openings 106 through the first ILD 96 and the CESL 94 educated. The source / drain contact openings 106 can be done initially in the first ILD using acceptable photolithography and etching techniques 96 be formed, such as with an etch process that is selective to the first ILD 96 is (e.g. the material of the first ILD 96 etches faster than the material of the CESL 94 ). For example, the source / drain contact openings 106 initially by dry etching using ammonia (NH ₃ ) and hydrogen fluoride (HF) gas through the first ILD 96 be educated. The source / drain contact openings 106 are then made by the CESL using acceptable photolithography and etching techniques 94 expanded, such as with an etching process that is selective for CESL 94 is (e.g. the material of the CESL 94 etches faster than the material of the epitaxial source / drain regions 92 ). For example, the source / drain contact openings 106 with dry etching using a fluorine-based gas (e.g. C ₄ F ₆ ) and hydrogen ( H2 ) or oxygen gas ( 02 ) through the CESL 94 be extended. The source / drain contact openings 106 are then partially in the epitaxial source / drain regions 92 extends, such as into the upper portions of the epitaxial source / drain regions 92 . For example, the source / drain contact openings 106 by dry etching using chlorine gas (Cl2 gas), hydrogen bromide gas (HBr gas) and oxygen gas (O ₂ gas), into the upper portions of the source / drain epitaxial regions 92 be extended.

Once formed, the source / drain contact openings extend 106 by a distance D ₂ into the upper portions of the epitaxial source / drain regions 92 . In some embodiments, the distance D _{2 is} about half the height H _{1 of} the epitaxial source / drain regions 92 . Timed etching processes can be used to etch the source / drain contact openings 106 after widening the source / drain contact openings 106 on the upper portions of the epitaxial source / drain regions 92 to expand a desired distance D ₂ . For example, if the etchants described above are used, the epitaxial source / drain regions 92 To etch, the etching can be carried out for a duration in the range from about 50 seconds to about 200 seconds, covering the source / drain contact openings 136 can cause a distance D ₂ in the range of about 15 nm to about 60 nm in the upper sections of the epitaxial source / drain regions 92 to extend.

Metal semiconductor alloy regions 108 are in the source / drain contact openings 106 such as at portions of the source / drain epitaxial regions 92 passing through the source / drain contact openings 106 are disclosed. The metal semiconductor alloy regions 108 may be silicide regions formed from a metal silicide (e.g. titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g. titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions, the same are formed from a metal silicide and a metal germanide, or the like. The metal semiconductor alloy regions 108 can be achieved by depositing a metal in the source / drain contact openings 106 and then performing a heat annealing process. The metal can be any metal capable of interfering with the semiconductor materials (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain regions 92 react to form a low resistance metal semiconductor alloy such as nickel, cobalt, titanium, tantalum, platinum, tungsten or other precious metals, other refractory metals, rare earth metals, or their alloys. A metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. In one embodiment, the metal semiconductor alloy regions are 108 Silicide regions formed from titanium silicon. After the thermal anneal process, a cleaning process, such as wet cleaning, can be performed to remove residual metal from the source / drain contact openings 106 such as from the upper surfaces of the first ILD 96 .

In the illustrated embodiment, the source / drain are contact openings 106 formed in a self-aligned structuring process so that all of the first ILD 96 in the cross section 11B removed. In another embodiment, other structuring techniques can be used so that some of the first ILD 96 in the cross section 11B remain.

In 12A and 12B are the first source / drain contacts 112A in the source / drain contact openings 106 educated. A liner, such as a diffusion barrier layer, an adhesive layer or the like, and a conductive material are in the source / drain contact openings 106 educated. The liner can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The liner can be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner can include an adhesive layer and at least a portion of the adhesive layer can be treated to form a diffusion barrier layer. The conductive material can be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold or the like. The conductive material can be deposited by ALD, CVD, PVD or. A planarization process, such as a CMP, can be performed to remove excess material from the top surfaces of the first ILD 96 to remove. The remaining liner and conductive material in the source / drain contact openings 106 forms the first source / drain contacts 112A . The first source / drain contacts 112A are physically and electrically related to the metal semiconductor alloy regions 108 coupled. The upper surfaces of the first source / drain contacts 112A , the gate electrodes 104 and the gate spacers 80 are coplanar (within the process variations).

After the formation, the first source / drain contacts have 112A similar dimensions as the source / drain contact openings 106 . The first source / drain contacts 112A extend by the distance D ₂ (see 11B) into the upper portions of the epitaxial source / drain regions 92 and have a height H ₂ . The height H ₂ can be in the range from approx. 30 nm to approx. 90 nm. In embodiments in which the distance D _{2 is} approximately half the height H ₁ (see FIG 7B) , the height H _{2 is} more than about half the height H ₁ .

In 13A and 13B is a second ILD 114 above the first ILD 96 , the gate electrodes 104 and the first source / drain contacts 112A deposited. The second ILD 114 may be formed from a material selected from the same group of candidate materials of the first ILD 96 is formed and may be deposited using a method selected from the same group of candidate methods to produce the first ILD 96 to be deposited. The first ILD 96 and the second ILD 114 can be formed from the same material or comprise different materials. After forming the second ILD 114 be planarized, such as by a CMP. In some embodiments, there is an etch stop layer between the first ILD 96 and the second ILD 114 educated. The etch stop layer may comprise a dielectric, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a different etch rate than the material of the overlying second ILD 114 .

Contact openings 116 are then in the second ILD 114 educated. A first subset of the contact openings 116A makes the first source / drain contacts 112A open and a second subset of the contact openings 116B lays the gate electrodes 104 open minded. The contact openings 116 can be formed using acceptable photolithography and etching techniques.

In 14A and 14B are second source / drain contacts 112B and gate contacts 118 formed by the second ILD 114 extend. A lining, such as a diffusion barrier layer, an adhesive layer or the like, and a conductive material are in the contact openings 116 educated. The liner can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The liner can be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner can include an adhesive layer and at least a portion of the adhesive layer can be treated to form a diffusion barrier layer. The conductive material can be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold or the like. The conductive material can be deposited by ALD, CVD, PVD or. A planarization process, such as a CMP, can be performed to remove excess material from a top surface of the second ILD 114 to remove. The remaining liner and conductive material in the contact openings 116A forms the second source / drain contacts 112B . The remaining liner and conductive material in the contact openings 116B forms the gate contacts 118 . The second source / drain contacts 112B are physically and electrically connected to the first source / drain contacts 112A coupled and the gate contacts 118 are physically and electrically connected to the gate electrodes 104 coupled.

The second source / drain contacts 112B and the gate contacts 118 can be formed in different processes or can be formed in the same process. Furthermore, the second source / drain contacts 112B and the gate contacts 118 be formed in the same cross-sections that through 13B and 14B are shown, or can be formed in other cross-sections be like through 13A and 14A shown what can prevent short circuits of the contacts.

As will be explained in more detail below, a first interconnect structure (e.g., a front side interconnect structure) is provided over the substrate 50 educated. The substrate 50 is then removed and replaced with a second interconnect structure (e.g., a back interconnect structure). So becomes a device layer 120 active devices are formed between a front interconnect structure and a rear interconnect structure. The front and back interconnect structures each include conductive elements that are electrically connected to the nano-FETs of the device layer 120 be connected. The conductive elements (e.g., metallization structures, also referred to as interconnects) of the front side interconnect structure are electrically connected to front sides of one or more of the epitaxial source / drain regions 92 and the gate electrodes 104 connected to form functional circuits such as logic circuits, memory circuits, image sensor circuits, or the like. The conductive elements (e.g., bus bars) of the rear interconnect structure electrically connects to rear surfaces of one or more of the epitaxial source / drain regions 92 connected to provide a reference voltage, supply voltage or the like to the functional circuits. Furthermore, conductive vias are made through the device layer 120 that connect some of the conductive elements of the front interconnection structure to some of the conductive elements of the rear interconnection structure. Specifically, a conductive element (e.g. a bus bar) of the rear interconnection structure is connected to a conductive element (e.g. metallization structures) of the front interconnection structure and also to one or more of the epitaxial source / drain regions 92 the device layer 120 tied together. Even if the device layer 120 is described as having nano-FETs, other embodiments may include a device layer 120 having a different type of transistor (e.g., planar FETs, FinFETs, TFTs, or the like).

Even if 14B a second source / drain contact 112B illustrated referring to each of the source / drain epitaxial regions 92 extends, the second source / drain contacts 112B from certain of the epitaxial source / drain regions 92 be left out. For example, as explained in more detail below, is a subset of the source / drain epitaxial regions 92P connected to conductive elements (e.g. a bus bar) of the rear interconnect structure. In the illustrated embodiment for these particular epitaxial source / drain regions 92P are the second source / drain contacts 112B also formed so that the busbars can be connected to overlying conductive elements of the front-side interconnection structure. In other embodiments, certain epitaxial source / drain regions can be used for these 92P the second source / drain contacts 112B can be omitted or dummy contacts that are not electrically connected to overlying conductive elements of the front interconnect structure.

15th until 22nd FIG. 12 are various views of intermediate stages in the manufacture of semiconductor devices in accordance with some embodiments. Specifically, the fabrication of front and rear interconnect structures for nano-FETs is illustrated. 15th , 16 , 17th , 18B , 19B , 20th , 21 and 22nd are cross-sectional views taken along reference cross-section AA in 1 are illustrated. 18A and 19B are three-dimensional views that have a similar three-dimensional view as 1 but showing a gate structure and two fins. 18A and 19A are simplified three-dimensional views and do not show all properties of the corresponding 18B and 19B . 15th , 16 , 17th , 18B , 19B , 20th , 21 and 22nd can for the n region 50N and the p region 50P are valid. Differences (if any) in the structures of the n-region 50N and the p-region 50P are described in the text accompanying each figure.

In 15th becomes an interconnection structure 122 at the device layer 120 formed, e.g. B. at the second ILD 114 . The interconnection structure 122 may also be referred to as a front side interconnect structure as it is on a front side of the substrate 50 / device layer 120 (e.g. one side of the substrate 50 at which the device layer 120 is formed) is formed.

The interconnection structure 122 can be one or more layers of conductive elements 124 comprised in one or more stacked dielectric layers 126 are formed. Each of the dielectric layers 126 may include a dielectric, such as a low-k dielectric, a particularly low-k dielectric (ELK dielectric), or the like. The dielectric layers 126 can be deposited using an appropriate process such as CVD, ALD, PVD, PECVD, or the like.

The conductive elements 124 may include conductive lines and conductive vias connecting the layers of the conductive lines. The conductive vias can extend through respective ones of the dielectric layers 126 extend to provide vertical connections between layers of conductive lines. The conductive elements 124 can be formed by any acceptable process. For example, the conductive elements 124 be formed by a damascene process such as a single damascene process, a double damascene process, or the like. A respective dielectric layer is in a damascene process 126 patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired structure of the conductive elements 124 correspond. An optional diffusion barrier and / or optional adhesive layer can be deposited and the trenches can then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, or other alternatives, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In one embodiment, the conductive elements 124 by depositing a seed layer of copper or a copper alloy and filling the trenches with electroplating. A chemical mechanical planarization (CMP) process or the like can be used to remove excess conductive material from one surface of the respective dielectric layer 126 to remove and then planarize the surface for subsequent processing.

In the illustrated example there are five layers of conductive elements 124 and dielectric layers 126 illustrated. However, it should be noted that the interconnection structure 122 may include any number of conductive elements disposed on any number of dielectric layers. The conductive elements 124 the interconnection structure 122 are electrical with the gate contacts 118 and the second source / drain contacts 112B connected to form functional circuits. In some embodiments, the functional circuitry represented by the interconnect structure 122 include logic circuits, memory circuits, image sensor circuits, or the like. The second ILD 114 , the second source / drain contacts 112B and the gate contacts 118 can also be used as part of the interconnect structure 122 may be considered as part of a first level of conductive elements of the interconnect structure 122 .

In 16 is a carrier substrate 130 by connecting layers 132A , 132B (collectively referred to as tie layers 132 ) with a top surface of the interconnection structure 122 tied together. The carrier substrate 130 can be a glass carrier substrate, a ceramic carrier substrate, a semiconductor substrate (e.g. a silicon substrate), a wafer (e.g. a silicon wafer) or the like. The carrier substrate 130 can provide structural support during subsequent processing steps and in the finished device. The carrier substrate 130 is essentially free of all active or passive devices.

In various embodiments, the carrier substrate 130 with the interconnection structure 122 be connected using a suitable technique such as dielectric-dielectric connection or the like. Dielectric-dielectric connection can deposit the connection layers 132A , 132B on the interconnect structure 122 or the carrier substrate 130 include. In some embodiments, the connection layer comprises 132A Silicon oxide (e.g., a high density plasma oxide (HDP) or the like) deposited by CVD, ALD, PVD or the like. The connection layer 132B may also be an oxide layer formed prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials can also be used for the tie layers 132A , 132B be used.

The dielectric-dielectric connection process may further include a surface treatment on one or more of the connection layers 132 to raise. The surface treatment can comprise a plasma treatment. The plasma treatment can be done in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water or the like) applied to one or more of the tie layers 132 can be applied. The carrier substrate 130 is then attached to the interconnection structure 122 aligned and the two are pressed together to pre-connect the carrier substrate 130 to the interconnection structure 122 initiate. The pre-connection can take place at room temperature (e.g. in a range from approx. 20 ° C to approx. 25 ° C). After the pre-connection, an annealing process can be used, for example by heating the interconnection structure 122 and the carrier substrate 130 to a temperature of approx. 170 ° C.

In 17th the intermediate structure is upside down, so that the back of the substrate 50 facing up. The back of the substrate 50 refers to on the side opposite the front of the substrate 50 at which the device layer 120 is formed. The substrate 50 is then thinned to rear portions of the substrate 50 to remove. The thinning process can include a planarization process (e.g., mechanical grinding, chemical mechanical polishing (CMP), or the like), an etch back process, combinations thereof, or the like. The thinning process defines the STI regions 60 and surfaces of the Finns 54 at the back of the device layer 120 open minded.

A dielectric layer 128 is across the back of the device layer 120 arranged, such as over the fins 54 and the STI regions 60 . The dielectric layer 128 is part of an interconnect structure attached to the device layer 120 is formed. The dielectric layer 128 can physically face the remaining sections of the fins 54 and the STI regions 60 to contact. The dielectric layer 128 may be formed from a material selected from the same group of candidate materials of the first ILD 96 is formed and may be deposited using a method selected from the same group of candidate methods to produce the first ILD 96 to be deposited. The first ILD 96 and the dielectric layer 128 can be formed from the same material or comprise different materials.

In 18A and 18B is a mask 134 over the dielectric layer 128 educated. The mask 134 may be formed from a photoresist such as a single-layer photoresist, a two-layer photoresist, a three-layer photoresist, or the like. In some embodiments, the mask is 134 a three-layer mask comprising a lower layer (e.g. a lower anti-reflective coating (BARC) layer), a middle layer (e.g. a nitride, an oxide, an oxynitride, or the like), and an upper layer (e.g. . A photoresist). The type of mask used (e.g., single-layer mask, two-layer mask, three-layer mask, etc.) may depend on the photolithography process that is used, the mask 134 to be structured below. For example, in extreme ultraviolet lithography processes (EUV lithography processes), the mask 134 be a single-layer mask or a two-layer mask. The mask 134 can be formed by spin coating, a deposition process such as CVD, combinations thereof, or the like. The mask 134 can be patterned using acceptable photolithography techniques to form the openings having a pattern of subsequently formed source / drain contacts.

Source / drain contact openings 136 are through the dielectric layer 128 , Finns 54 , the epitaxial source / drain regions 92P and the metal semiconductor alloy regions 108 educated. The source / drain contact openings 136 can be done initially using acceptable photolithography and etching techniques in the dielectric layer 128 be formed, such as with an etching process that is selective to the dielectric layer 128 (e.g. the material of the dielectric layer 128 etches faster than the material used in the fins 54 ), with the mask 134 is used as an etching mask. For example, the source / drain contact openings 136 initially by dry etching using ammonia (NH ₃ ) and hydrogen fluoride gas (HF gas) through the dielectric layer 128 be educated. The source / drain contact openings 136 are then passed through the fins using acceptable photolithography and etching techniques 54 expanded, such as with an etching process that is selective for the fins 54 is (e.g. the material of the Finns 54 etches faster than the material used in the fins 92 ). For example, the source / drain contact openings 136 by dry etching using a fluorine-based gas such as hydrogen fluoride (HF) gas through the fins 54 be extended. The source / drain contact openings 136 are then through the epitaxial source / drain regions 92P and the metal semiconductor alloy regions 108 extends so that the source / drain contact openings 136 into the lower portions of the epitaxial source / drain regions 92P extend and the first source / drain contacts 112A disclose. For example, the source / drain contact openings 136 by dry etching using chlorine gas (Cl2 gas), hydrogen bromide gas (HBr gas) and oxygen gas (O ₂ gas) through the epitaxial source / drain regions 92P and the metal semiconductor alloy regions 108 be extended. In the illustrated embodiment, there is essentially no etching of the first source / drain contacts 112A on when the source / drain contact openings 136 be structured. In another embodiment, the source / drain contact openings can be 136 also in the first source / drain contacts 112A extend.

The mask 134 can during or after the patterning of the source / drain contact openings 136 removed. For example, the mask 134 by the etching processes that are used, the dielectric layer is removed 128 , Finns 54 , the epitaxial source / drain regions 92P or the metal semiconductor alloy regions 108 to structure. In another embodiment, the mask 134 after structuring the source / drain contact openings 136 removed, such as by an acceptable ash process.

Once formed, the source / drain contact openings extend 136 by a distance D ₃ into the lower portions of the epitaxial source / drain regions 92P . In some embodiments, the distance D _{3 is} approximately half the height H ₁ (see FIG 7B) of the epitaxial source / drain regions 92P . The sum of the distances D ₂ (see 11B) and D ₃ corresponds to the height H _1. In other words, the distances D ₂ and D ₃ can be the same. In another embodiment, the distances D ₂ and D _{3 are} different; for example, the distance D _{2 can be} greater or smaller than the distance D ₃ . Timed etching processes can be used to etch the source / drain contact openings 136 after widening the source / drain contact openings 136 on the lower portions of the epitaxial source / drain regions 92P to expand a desired distance D ₃ . For example, if the etchants described above are used, the epitaxial source / drain regions 92P To etch, the etching can be carried out for a duration in the range from about 50 seconds to about 200 seconds, covering the source / drain contact openings 136 can cause a distance D ₃ in the range from about 15 nm to about 60 nm into the lower sections of the epitaxial source / drain regions 92P to extend.

In 19A and 19B are metal semiconductor alloy regions 138 in the source / drain contact openings 136 such as at portions of the source / drain epitaxial regions 92P passing through the source / drain contact openings 136 are disclosed. The metal semiconductor alloy regions 138 may be silicide regions formed from a metal silicide (e.g. titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g. titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions, the same are formed from a metal silicide and a metal germanide, or the like. The metal semiconductor alloy regions 138 can be achieved by depositing a metal in the source / drain contact openings 136 and then performing a heat annealing process. The metal can be any metal capable of interfering with the semiconductor materials (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain regions 92P react to form a low resistance metal semiconductor alloy such as nickel, cobalt, titanium, tantalum, platinum, tungsten or other precious metals, other refractory metals, rare earth metals, or their alloys. A metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. In one embodiment, the metal semiconductor alloy regions are 138 Silicide regions formed from titanium silicon.

After the thermal anneal process, a cleaning process, such as wet cleaning, can be performed to remove residual metal from the source / drain contact openings 136 such as from areas of the first source / drain contacts 112A and the STI regions 60 . Even if the metal semiconductor alloy regions 108 , 138 are shown as separate regions, it should be noted that, in some embodiments, the metal semiconductor alloy regions 108 , 138 merge as they are formed so that there is no distinguishable interface between them.

Third source / drain contacts 112C are in the source / drain contact openings 136 educated. A liner, such as a diffusion barrier layer, an adhesive layer or the like, and a conductive material are in the source / drain contact openings 136 educated. The liner can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The liner can be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner can include an adhesive layer and at least a portion of the adhesive layer can be treated to form a diffusion barrier layer. The conductive material can be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold or the like. The conductive material can be deposited by ALD, CVD, PVD or. A planarization process, such as a CMP, can be performed to remove excess material from the top surface of the dielectric layer 128 to remove. The remaining liner and conductive material in the source / drain contact openings 136 forms the third source / drain contacts 112C . The third source / drain contacts 112C are physically and electrically connected to the first source / drain contacts 112A coupled. The top surfaces of the third source / drain contacts 112C , the dielectric layer 128 are coplanar (within the process variations).

After forming, the third have source / drain contacts 112C similar dimensions as the source / drain contact openings 136 . The third source / drain contacts 112C extend by the distance D ₃ (see 18B) into the lower portions of the epitaxial source / drain regions 92 and have a height H ₃ . The height H ₃ can be in the range from approx. 25 nm to approx. 70 nm. In embodiments in which the distance D _{3 is} approximately half the height H ₁ (see 7B) , the height H _{3 is} more than about half the height H ₁ .

In 20th are a dielectric layer 142 and conductive elements 144 over the dielectric layer 128 and the third source / drain contacts 112C educated. The dielectric layer 142 and the conductive elements 144 are also part of an interconnect structure that resides on the device layer 120 is formed. The dielectric layer 142 may be formed from a material selected from the same group of candidate materials of the first ILD 96 is formed and may be deposited using a method selected from the same group of candidate methods to produce the first ILD 96 to be deposited. The first ILD 96 and the dielectric layer 142 can be formed from the same material or comprise different materials.

The conductive elements 144 are in the dielectric layer 142 formed and can be conductive lines. Forming the conductive elements 144 can, for example, structure cutouts in the dielectric layer 142 using a combination of photolithography and etching processes. A structure of the cutouts in the dielectric layer 142 can be a structure of conductive elements 144 correspond. The conductive elements 144 are then formed by depositing a conductive material in the cutouts. In some embodiments, the conductive elements comprise 144 a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the conductive elements comprise 144 Copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium or the like. An optional diffusion barrier and / or optional adhesive layer can be filled with a conductive material prior to filling the cutouts. Suitable materials for the barrier layer / adhesive layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide or the like. The conductive elements 144 can be formed using, for example, CVD, ALD, PVD, plating, or the like. The conductive elements 144 are electrical through the third source / drain contacts 112C and the metal semiconductor alloy regions 138 with the epitaxial source / drain regions 92P tied together. A planarization process (e.g., CMP, grinding, etch back, or the like) can be performed to remove excess portions of the conductive elements 144 to remove that over the dielectric layer 142 are formed.

Some or all of the conductive elements 144 are busbars 144P , which are conductive lines that form the epitaxial source / drain regions 92P electrically connect to a reference voltage, supply voltage or the like. By placing the power rails 144P on a back side of the device layer 120 rather than a front side of the device layer 120 benefits can be achieved. For example, a gate density of the nano-FETs and / or an interconnection density of the interconnection structure 122 increase. Furthermore, the back side of the device layer 120 wider bus bars accommodate lower resistance and increase the efficiency of current delivery to the nano-FETs. For example, a width of the conductive elements 144 at least twice the width of a conductive line of the first level (e.g. conductive line 124A in 15th ) the interconnection structure 122 exhibit.

The first source / drain contacts 112A and the third source / drain contacts 112C form conductive vias 148 which can be referred to as busbar vias. Each busbar via includes a first source / drain contact 112A and a third source / drain contact 112C . The total height of the conductive vias 148 corresponds to the sum of the height H ₂ (see 12B) and H ₃ (see 19B) . The conductive vias 148 extend through the device layer 120 and connect the conductive elements of the interconnection structure 122 (e.g. metallization structures) with the conductive elements of the interconnection structure 150 (e.g. busbars 144P ). The reference voltage, supply voltage, etc. can thus be electrically connected to the epitaxial source / drain regions 92P and the interconnection structure 122 equally through the conductive vias 148 be connected. Connect the busbars 144P with the interconnection structure 122 by conductive elements (e.g. the conductive vias 148 ) instead of through semiconductor elements (e.g. the epitaxial source / drain regions 92P ) can achieve benefits. For example, conductive elements have a lower resistance than semiconductor elements, which improve the performance of a local interconnection between the interconnection structures 122 , 150 allow. Furthermore, the conductive vias are 148 also physically and electrically with the epitaxial source / drain regions 92P coupled where a busbar connection is desired. In this embodiment, the metal semiconductor alloy regions surround 108 , 138 the portions of the conductive vias 148 that extends through the epitaxial source / drain region 92P extend, and are coupled with it. As the conductive vias 148 through the epitaxial source / drain regions 92P can extend voltage drops across the epitaxial material of the epitaxial source / drain regions 92P can thus be avoided during operation, whereby the parasitic capacitance of the nano-FETs is reduced. Finally, the same conductive elements can be used to make the source / drain epitaxial regions 92P with the busbars 144P to connect and local interconnections between the interconnection structures 122 , 150 Establish what the amount of conductive elements in the interconnect structure 150 decreased.

In 21 become remaining portions of an interconnection structure 150 on a back side of the device layer 120 such as over the dielectric layer 142 and the conductive elements 144 . The interconnection structure 150 may also be referred to as a back interconnect structure because it is on a back side of the device layer 120 is formed. The remaining sections of the interconnect structure 150 can be similar to the interconnection structure 122 be. For example, the interconnection structure 150 comprise similar materials and be formed using similar processes as the interconnect structure 122 . In particular, the interconnection structure 150 stacked layers of conductive elements 154 include those in stacked dielectric layers 152 are formed. The conductive elements 154 may include routing lines (e.g. for routing to and from subsequently formed contact pads and external connectors). The conductive elements 154 may further include conductive vias located in the dielectric layers 152 extend to provide vertical interconnection between stacked layers of the conductive lines. The interconnection structure 150 thus includes the dielectric layers 128 , 142 , 152 and the conductive elements 144 , 154 .

In some embodiments, the conductive elements of the interconnect structure 150 further structured, one or more embedded passive devices, such as resistors, capacitors, inductors, or the like, in the interconnect structure 150 to include. The embedded passive devices can be connected to the conductive elements 144 , 154 (e.g. the busbars 144P ) be integrated to circuits (e.g. power circuits) at the rear of the device layer 120 provide.

In 22nd are a passivation layer 160 , UBMs 162 , and external connectors 164 above the interconnection structure 150 educated. The passivation layer 160 can include polymers such as PBO, polyimide, BCB, or the like. Alternatively, the passivation layer 160 inorganic dielectrics include such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The passivation layer 160 can for example be deposited by CVD, PVD, ALD or the like.

The UBMs 162 are through the passivation layer 160 on the conductive elements 154 the interconnection structure 150 formed and the external connector 164 are on the UBMs 162 educated. The UBMs 162 may include one or more layers of copper, nickel, gold, or the like formed by a plating process or the like. The external connectors 164 (e.g. solder balls) are on the UBMs 162 educated. Forming the external connectors 164 may include placing solder balls on the exposed sections of the UBMs 162 and then include reflowing the solder balls. In alternative embodiments, this includes forming the external connectors 164 performing a plating step to form solder regions over the top conductive member 154 and then a melting of the soldering regions. In another embodiment the external connectors are 164 Metal connectors with essentially vertical side walls like microbumps. The UBMs 162 and the external connectors 164 can be used to provide input / output connections to other electrical components, such as other device arrays, redistribution structures, printed circuit boards (PCBs), motherboards, or the like. The UBMs 162 and the external connectors 164 may also be referred to as rear input / output pads that provide a signal, reference voltage, supply voltage, and / or ground connections to the nano-FETs of the device layer 120 can provide.

23A until 31 FIG. 13 are various views of intermediate stages in the manufacture of semiconductor devices in accordance with some other embodiments. Specifically, the fabrication of front and rear interconnect structures for nano-FETs is illustrated. 23A , 24A , 25A , 26A , 27A , 28A , 29A and 30A are three-dimensional views that have a similar three-dimensional view as 1 show, however, two gate structures and two fins are shown. 23B , 24B , 25B , 26B , 27B , 28B , 29B , 30B and 31 are cross-sectional views taken along the reference cross-section AA in FIG 1 illustrate. 23A , 24A , 25A , 26A , 27A , 28A , 29A and 30A are simplified three-dimensional views and do not show all elements of the corresponding 23B , 24B , 25B , 26B , 27B , 28B , 29B and 30B . 23B , 24B , 25B , 26B , 27B , 28B , 29B , 30B and 31 can for the n region 50N and the p region 50P are valid.

Differences (if any) in the structures of the n-region 50N and the p-region 50P are described in the text accompanying each figure.

In the 23A and 23B a structure similar to that with reference to is obtained 10A and 10B described.

In 24A and 24B become the one or more gate structures 100 removed and through dielectric elements 172 replaced. In some embodiments, the replaced are gate structures 100 the gate structures 100 at the end of a memory cell, such as the gate structures 100 at the ends of the fins 54 . The replaced gate structures 100 and adjacent source / drain epitaxial regions 92P connected with busbars. The desired gate structures 100 can be removed with acceptable photolithography and etching techniques to form openings. The dielectric elements 172 are then formed in the openings. The dielectric elements 172 can be formed from a dielectric such as silicon oxide, silicon nitride or the like. The dielectric elements 172 can by depositing the dielectric over the remaining gate structures 100 and then planarizing the dielectric so that upper surfaces of the dielectric elements are formed 172 and the remaining gate structures 100 (within the process variations) are coplanar. The dielectric elements 172 thus surround the nanostructures 56B by the replaced gate structures 100 were surrounded.

In 25A and 25B are source / drain contact openings 106 through the first ILD 96 and the CESL 94 educated. In this embodiment, a first subset of the source / drain contact openings is also used 106P (e.g., those used to form busbar vias) through the dielectric elements 172 , the inner spacer 84 , the gate spacer 80 and the second nanostructures 56B formed around sidewalls of the epitaxial source / drain regions 92P to disclose. A second subset of the source / drain contact openings 106R (e.g., those not used to form busbar vias) does not extend through the dielectric elements 172 , the inner spacer 84 , the gate spacer 80 or the second nanostructures 56B educated.

The source / drain contact openings 106R , 106P can be formed by multiple photolithography and etching techniques. The source / drain contact openings 106R , 106P can be done initially in the first ILD using acceptable photolithography and etching techniques 96 be formed, such as with an etch process that is selective to the first ILD 96 is (e.g. the material of the first ILD 96 etches faster than the material of the CESL 94 ). For example, the source / drain contact openings 106R , 106P initially by dry etching using ammonia (NH ₃ ) and hydrogen fluoride (HF) gas through the first ILD 96 be educated. The source / drain contact openings 106R , 106P are then made by the CESL using acceptable photolithography and etching techniques 94 expanded, such as with an etching process that is selective for CESL 94 is (e.g. the material of the CESL 94 etches faster than the material of the epitaxial source / drain regions 92 ). For example, the source / drain contact openings 106R , 106P with dry etching using a fluorine-based gas (e.g. C ₄ F ₆ ) and hydrogen ( H2 ) or oxygen gas ( 02 ) through the CESL 94 be extended. The source / drain contact openings 106R are then masked, such as by forming a photoresist over the source / drain contact openings 106R . The source / drain contact openings 106P are then passed through the dielectric elements using acceptable photolithography and etching techniques 172 , the inner spacers 84 who have favourited Gate Spacers 80 and the second nanostructures 56B extends, such as with an etching process that is selective for the dielectric elements 172 , the inner spacers 84 who have favourited Gate Spacers 80 and the second nanostructures 56B (e.g. the materials of the dielectric elements 172 , the inner spacers 84 who have favourited Gate Spacers 80 and the second nanostructures 56B etches faster than the material of the epitaxial source / drain regions 92 ). For example, the source / drain contact openings 106P by dry etching using a fluorine-based gas (e.g., C ₄ F ₆ ) and hydrogen gas (H2 gas) or oxygen gas (O ₂ gas) through the dielectric elements 172 , the inner spacers 84 who have favourited Gate Spacers 80 and the second nanostructures 56B be extended. The source / drain contact openings 106P may not extend into the Finns 54 how by 25A shown, or can also be formed into the fins 54 to extend how through 25B shown.

Once formed, the source / drain contact openings extend 106R , 106P by a distance D ₄ partially into the epitaxial source / drain regions 92 such as in the upper portions of the epitaxial source / drain regions 92 . In some embodiments, the distance D _{4 is} less than about half the height H ₁ (see FIG 7B) of the epitaxial source / drain regions 92 . Timed etching processes can be used to etch the source / drain contact openings 106R , 106P after widening the source / drain contact openings 106R , 106P on the upper portions of the epitaxial source / drain regions 92 by a desired distance D4 to expand. For example, if the etchants described above are used, the epitaxial source / drain regions 92 To etch, the etching can last for a period ranging from about 10 seconds to about 40 seconds Seconds running across the source / drain contact openings 136 Can cause yourself a distance D4 in the range from approx. 2 nm to approx. 10 nm in the upper sections of the epitaxial source / drain regions 92P to extend. The source / drain contact openings 106R can with a width W1 be formed, which can be in the range from about 10 nm to about 30 nm.

After expanding, the source / drain contact openings extend 106P by a distance D5 into the intermediate structure. In some embodiments, the distance is D5 greater than the height H1 of the epitaxial source / drain regions 92 . Timed etching processes can be used to etch the source / drain contact openings 106P after widening the source / drain contact openings 106P by a desired distance D5 into the intermediate structure. For example, if the etchants described above are used, the dielectric elements 172 , the inner spacers 84 , the gate spacers, 80 and the second nanostructures 56B To etch, the etching can be carried out for a duration in the range of about 140 seconds to about 400 seconds, which the source / drain contact openings 136P can cause a distance D ₅ in the range of about 40 nm to about 120 nm to extend into the intermediate structure. The top portion of the source / drain contact openings 106R (e.g. the sections above the epitaxial source / drain regions 92P ) can also be expanded to a width W ₂ , which can be in the range from approx. 10 nm to approx. 50 nm and is greater than the width W ₁ . The lower portion of the source / drain contact openings 106R (e.g. those relating to the epitaxial source / drain regions 92P adjacent sections) can also be formed to a width W _3, which can be in the range from approx. 10 nm to approx. 30 nm and is smaller than the width W ₂ .

Metal semiconductor alloy regions 108 are then in the source / drain contact openings 106 such as at portions of the source / drain epitaxial regions 92 passing through the source / drain contact openings 106 are disclosed. In this embodiment, the metal semiconductor alloy regions extend 108 along the exposed sidewalls of the epitaxial source / drain regions 92P . The metal semiconductor alloy regions 108 may be formed in a similar manner as with reference to 11A and 11B described.

In 26A and 26B are the first source / drain contacts 112A in the source / drain contact openings 106 educated. The first source / drain contacts 112A may be formed in a manner similar to that referred to in 12A and 12B described. In this embodiment, a subset of the first source / drain contacts 112A _P , such as those in the source / drain contact openings, extend 106P are formed along the sidewalls and top surfaces of the epitaxial source / drain regions 92P and are in contact with it.

After the formation, the first source / drain contacts have 112A similar dimensions as the source / drain contact openings 106 . The first source / drain contacts 112A extend by the distance D ₄ (see 25B) into the upper portions of the epitaxial source / drain regions 92 and portions of the first source / drain contacts 112A over the epitaxial source / drain regions 92 have a height in the range from approx. 2 nm to approx. 10 nm.

In 27A and 27B is a second ILD 114 above the first ILD 96 , the gate electrodes 104 and the first source / drain contacts 112A deposited. Contact openings 116 are then in the second ILD 114 educated. The second ILD 114 and the contact openings 116 may be formed in a manner similar to that referred to in 13A and 13B described.

In 28A and 28B are second source / drain contacts 112B and gate contacts 118 formed by the second ILD 114 extend. The second source-drain contacts 112B and the gate contacts 118 can be formed in a manner similar to that relating to 14A and 14B described. As noted above, the second source / drain contacts 112B and the gate contacts 118 be formed in the same cross-sections that through 27B and 28B are shown, or may be formed in other cross-sections, such as by 27A and 28A shown.

In 29A and 29B For example, the intermediate structure can be processed in a manner similar to that referred to in reference to 15th until 17th described. For example, an interconnection structure 122 can be formed, the structure can be turned over and the substrate 50 can with a dielectric layer 128 be replaced. Source / drain contact openings 136 are then through the dielectric layer 128 and the Finns 54 educated. The source / drain contact openings 136 can also extend into the lower sections of the epitaxial source / drain regions 92P extend. The source / drain contact openings 136 can be formed in a manner similar to that relating to 18A and 18B described, e.g. By using a mask 134 as an etching mask. In this embodiment the source / drain contact openings are 136 not through the epitaxial source / drain regions 92P educated, rather extend only partially into the lower portions of the epitaxial source / drain regions 92P . Timed etching processes can be used to etch the source / drain contact openings 136 after widening the source / drain contact openings 136 on the lower portions of the epitaxial source / drain regions 92P to extend the desired distance D ₆ . For example, if the one with reference to 18A and 18B etchant described are used, the source / drain contact openings 136 To etch, the etching can be carried out for a duration in the range of about 90 seconds to about 240 seconds, covering the source / drain contact openings 136 can cause a distance D ₆ in the range of about 2 nm to about 10 nm in the lower sections of the epitaxial source / drain regions 92P to extend. The source / drain contact openings 136 can be formed with a width W ₃ , which can be in the range from about 10 nm to about 50 nm.

In 30A and 30B are metal semiconductor alloy regions 138 in the source / drain contact openings 136 such as at portions of the source / drain epitaxial regions 92P passing through the source / drain contact openings 136 are disclosed. The metal semiconductor alloy regions 138 may be formed in a similar manner as with reference to 19A and 19B described. In one embodiment, the metal semiconductor alloy regions are 138 curved layers physically associated with the sections of the metal semiconductor alloy regions 108 are coupled that extend along the sidewalls of the epitaxial source / drain regions 92P extend. Even if the metal semiconductor alloy regions 108 , 138 are shown as separate regions, it should be noted that, in some embodiments, the metal semiconductor alloy regions 108 , 138 merge as they are formed so that there is no distinguishable interface between them.

Third source / drain contacts 112C are then in the source / drain contact openings 136 educated. The third source / drain contacts 112C may be formed in a manner similar to that referred to in 19A and 19B described. In this embodiment, the third have source / drain contacts 112C Sections at the first source / drain contacts 112A _P and portions extending into the lower portions of the epitaxial source / drain regions 92P extend on. The third source / drain contacts 112C thus extend along the lower surfaces of the epitaxial source / drain regions 92P and contact them. After forming, the third have source / drain contacts 112C similar dimensions as the source / drain contact openings 136 . The first source / drain contacts 112AP and the third source / drain contacts 112C form conductive vias 148 which can be referred to as busbar vias. In this embodiment, the metal semiconductor alloy regions are 108 , 138 between each conductive via 148 and each of the two surface, the sidewall and the lower surface of the respective epitaxial source / drain region 92P arranged.

In 31 become remaining portions of an interconnection structure 150 on a back side of the device layer 120 educated. The remaining sections of the interconnect structure 150 may be formed in a manner similar to that referred to in 20th and 21 described. The interconnection structure 150 includes busbars 144P that are connected to the conductive vias 148 are connected.

A passivation layer 160 , UBMs 162 and external connectors 164 are then above the interconnection structure 150 educated. The passivation layer 160 who have favourited UBMs 162 and the external connectors 164 may be formed in a manner similar to that with reference to 22nd described.

32A until 40 FIG. 13 are various views of intermediate stages in the manufacture of semiconductor devices in accordance with some other embodiments. Specifically, the fabrication of front and rear interconnect structures for nano-FETs is illustrated. 32A , 33A , 34A , 35A , 36A , 37A , 38A and 39A are three-dimensional views that have a similar three-dimensional view as 1 show, however, two gate structures and two fins are shown. 32B , 33B , 34B , 35B , 36B , 37B , 38B , 39B and 40 are cross-sectional views taken along the reference cross-section AA in FIG 1 illustrate. 32A , 33A , 34A , 35A , 36A , 37A , 38A and 39A are simplified three-dimensional views and do not show all elements of the corresponding 32B , 33B , 34B , 35B , 36B , 37B , 38B and 39B . 32B , 33B , 34B , 35B , 36B , 37B , 38B , 39B and 40 can for the n region 50N and the p region 50P are valid. Differences (if any) in the structures of the n-region 50N and the p-region 50P are described in the text accompanying each figure.

In the 32A and 32B a structure similar to that with reference to is obtained 24A and 24B described. Source / drain contact openings 106 are then through the first ILD 96 and the CESL 94 educated. The source / drain contact openings 106 can be done initially in the first ILD using acceptable photolithography and etching techniques 96 be formed, such as with an etching process that is selective for the first ILD 96 is (e.g. the material of the first ILD 96 etches faster than the material of the CESL 94 ). For example, the source / drain contact openings 106 initially by dry etching using ammonia (NH ₃ ) and hydrogen fluoride (HF) gas through the first ILD 96 be educated. The source / drain contact openings 106 are then made by the CESL using acceptable photolithography and etching techniques 94 expanded, such as with an etching process that is selective for CESL 94 is (e.g. the material of the CESL 94 etches faster than the material of the epitaxial source / drain regions 92 ). For example, the source / drain contact openings 106 with dry etching using a fluorine-based gas (e.g. C ₄ F ₆ ) and hydrogen ( H2 ) or oxygen gas ( 02 ) through the CESL 94 be extended.

Busbar openings 174 are then through the dielectric elements 172 and the second nanostructures 56B educated. The busbar vias 174 may be formed using acceptable photolithography and etching techniques, such as an etching process that is selective to the dielectric elements 172 and the second nanostructures 56B (e.g. the materials of the dielectric elements 172 and the second nanostructures 56B Etches faster than the material of the epitaxial source / drain regions 92 ). For example, the busbar via openings 174 by dry etching using a fluorine-based gas (e.g., C ₄ F ₆ ) and hydrogen gas (H2 gas) or oxygen gas (O ₂ gas) through the dielectric elements 172 and the second nanostructures 56B be extended. The busbar vias 174 may not extend into the Finns 54 how by 32A shown, or can also be formed into the fins 54 to extend how through 32B shown.

After forming, the busbar via openings extend 174 by a distance D ₇ into the intermediate structure. In some embodiments, the distance D _{7 is} greater than the height H ₁ (see FIG 7B) of the epitaxial source / drain regions 92 . Timed etch processes can be used to etch the busbar via openings 174 after widening the busbar vias 174 by a desired distance D ₇ into the intermediate structure. For example, if the etchants described above are used, the dielectric elements 172 and the second nanostructures 56B To etch, the etching can be carried out for a duration in the range of about 140 seconds to about 400 seconds, which the source / drain contact openings 136 can cause a distance D ₇ in the range from about 40 nm to about 120 nm to extend into the intermediate structure. The busbar vias 174 can with a width W4 be formed, which can be in the range from about 10 nm to about 30 nm.

In 33A and 33B are the first source / drain contacts 112A in the source / drain contact openings 106 educated. The first source / drain contacts 112A may be formed in a manner similar to that referred to in 12A and 12B described. There are also busbar contacts 176 in the busbar vias 174 educated. The busbar contacts 176 may be formed in a similar manner as the first source / drain contacts 112A . The first source / drain contacts 112A and the busbar contacts 176 can be formed in the same process or in different processes. The busbar contacts 176 extend along but are not physically separated from the sidewalls of the epitaxial source / drain regions 92P . The busbar contacts 176 extend through the dielectric elements 172 and the second nanostructures 56B .

In 34A and 34B is a second ILD 114 above the first ILD 96 , the gate electrodes 104 , the first source / drain contacts 112A and the busbar contacts 176 deposited. Contact openings 116 are then in the second ILD 114 educated. The second ILD 114 and the contact openings 116 may be formed in a manner similar to that referred to in 13A and 13B described. In this embodiment there is a third subset of the contact openings 116C the busbar contacts 176 and the respective adjacent first source / drain contacts 112A open minded.

In 35A and 35B are second source / drain contacts 112B , Gate contacts 118 and shared contacts 178 formed by the second ILD 114 extend. The second source-drain contacts 112B and the gate contacts 118 can be formed in a manner similar to that relating to 14A and 14B described. The shared contacts 178 may be formed in a similar manner as the second source / drain contacts 112B and the gate contacts 118 . The shared contacts 178 are each with a busbar contact 176 and a respective adjacent first source / drain contact 112A tied together.

In 36A and 36B are the shared contacts 178 cut out openings 180 Form over the shared contacts 178. The remaining sections of the shared contacts 178 can be viewed as conductive lines. The shared contacts 178 can using acceptable photolithography and etching techniques be cut out, such as with an etch back process that is selective for the shared contacts 178 is (e.g. the material of the split contacts 178 etches faster than the material of the second ILD 114 ).

In 37A and 37B are dielectric plugs 182 in the openings 180 educated. The dielectric plugs 182 may be formed from a material selected from the same group of candidate materials of the dielectric elements 172 is formed and may be deposited using a method selected from the same group of candidate methods to form the dielectric elements 172 to be deposited. The dielectric elements 172 and the dielectric plugs 182 can be formed from the same material or comprise different materials. Forming the dielectric plugs 182 allows electrical isolation of the shared contacts 178 and their protection during subsequent processing.

In 38A and 38B For example, the intermediate structure can be processed in a manner similar to that referred to in reference to 15th until 17th described. For example, an interconnection structure 122 can be formed, the structure can be turned over and the substrate 50 can with a dielectric layer 128 be replaced. Source / drain contact openings 136 are then through the dielectric layer 128 and the Finns 54 educated. The source / drain contact openings 136 can also extend into the lower sections of the epitaxial source / drain regions 92P extend. The source / drain contact openings 136 can be formed in a manner similar to that relating to 18A and 18B described, e.g. By using a mask 134 as an etching mask. In this embodiment the source / drain contact openings are 136 not through the epitaxial source / drain regions 92P but only partially extend into the lower portions of the epitaxial source / drain regions 92P . Timed etching processes can be used to etch the source / drain contact openings 136 after widening the source / drain contact openings 136 on the lower portions of the epitaxial source / drain regions 92P to widen the desired distance D _8. For example, if the one with reference to 18A and 18B etchant described are used, the source / drain contact openings 136 To etch, the etching can be carried out for a duration in the range of about 90 seconds to about 240 seconds, covering the source / drain contact openings 136 can cause a distance D ₈ in the range of approximately 2 nm to approximately 10 nm into the lower sections of the epitaxial source / drain regions 92P to extend. The source / drain contact openings 136 can be formed with a width W ₅ , which can be in the range from about 10 nm to about 50 nm.

In 39A and 39B are metal semiconductor alloy regions 138 in the source / drain contact openings 136 such as at portions of the source / drain epitaxial regions 92P passing through the source / drain contact openings 136 are disclosed. The metal semiconductor alloy regions 138 may be formed in a similar manner as with reference to 19A and 19B described. In one embodiment, the metal semiconductor alloy regions are 138 curved layers. Even if the metal semiconductor alloy regions 108 , 138 are shown as separate regions, it should be noted that, in some embodiments, the metal semiconductor alloy regions 108 , 138 merge as they are formed so that there is no distinguishable interface between them.

Third source / drain contacts 112C are then in the source / drain contact openings 136 educated. The third source / drain contacts 112C may be formed in a manner similar to that referred to in 19A and 19B described. In this embodiment, the third have source / drain contacts 112C Sections at the busbar contacts 176 and portions extending into the lower portions of the epitaxial source / drain regions 92P extend on. The third source / drain contacts 112C thus extend along the lower surfaces of the epitaxial source / drain regions 92P and contact them. After forming, the third have source / drain contacts 112C similar dimensions as the source / drain contact openings 136 . The first source / drain contacts 112A and the busbar contacts 176 form conductive vias 148 which can be referred to as busbar vias.

In 40 become remaining portions of an interconnection structure 150 on a back side of the device layer 120 educated. The remaining sections of the interconnect structure 150 may be formed in a manner similar to that referred to in 20th and 21 described. The interconnection structure 150 includes busbars 144P that are connected to the conductive vias 148 are connected.

A passivation layer 160 , UBMs 162 and external connectors 164 are then above the interconnection structure 150 educated. The passivation layer 160 who have favourited UBMs 162 and the external connectors 164 may be formed in a manner similar to that with reference to 22nd described.

Embodiments can achieve advantages. Placing the busbars 144P on a back side of the device layer 120 rather than a front side of the device layer 120 can increase the gate density and / or Allow interconnection density of the resulting semiconductor devices. Furthermore, the back side of the device layer 120 wider bus bars accommodate lower resistance and increase the efficiency of current delivery to the semiconductor devices. Connect the busbars 144P with the interconnection structure 122 by conductive elements (e.g. the conductive vias 148 ) instead of through semiconductor elements (e.g. the epitaxial source / drain regions 92P ) can also achieve benefits. Specifically, the performance of the local interconnection between the interconnection structures 122 , 150 be improved. Finally, the same conductive elements (e.g. the conductive vias 148 ) are used to represent the epitaxial source / drain regions 92P with the busbars 144P to connect and local interconnections between the interconnection structures 122 , 150 Establish what the amount of conductive elements in the interconnect structure 150 decreased.

In one embodiment, a device comprises: a nanostructure; a gate structure surrounding the nanostructure; a source / drain epitaxial region adjacent to the gate structure; a first dielectric layer over a top portion of the source / drain epitaxial region; a second dielectric layer under a lower portion of the source / drain epitaxial region; and a power bar via extending through the first dielectric layer and the second dielectric layer, the power bar via physically and electrically coupled to the top portion and the bottom portion of the epitaxial source / drain region.

In some embodiments of the device, the busbar via extends through the epitaxial source / drain region. In some embodiments of the device, the busbar via includes: a first source / drain contact extending through the first dielectric layer and into a top portion of the epitaxial source / drain region; and a second source / drain contact extending through the second dielectric layer and into a lower portion of the epitaxial source / drain region, the second source / drain contact physically and electrically connected to the first source / drain -Contact is coupled. In some embodiments, the device further comprises: a metal semiconductor alloy region surrounding portions of the busbar via that extend through the epitaxial source / drain region. In some device embodiments, the power bar via extends along a sidewall of the source / drain epitaxial region. In some embodiments of the device, the device comprises: a first source / drain contact extending through the first dielectric layer, the first source / drain contact extending along the sidewall and a top surface of the epitaxial source / drain Region extends; and a second source / drain contact extending through the second dielectric layer, the second source / drain contact extending along a lower surface of the epitaxial source / drain region. In some embodiments, the device further comprises: a metal semiconductor alloy region disposed between the power bar via and each of the top surface, the sidewall, and the bottom surface of the source / drain epitaxial region.

In one embodiment, a device comprises: a first interconnect structure, including metallization structures; a second interconnection structure comprising a bus bar; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor and the first transistor including an epitaxial source / drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization structures and the conductive via contacting the epitaxial source / drain region.

In some embodiments of the device, the conductive via extends through the epitaxial source / drain region. In some embodiments of the device, the conductive via extends along and contacts a sidewall, a top surface, and a bottom surface of the epitaxial source / drain region. In some device embodiments, the conductive via extends along and contacts a bottom surface of the epitaxial source / drain region, and extends along and is physically separate from a sidewall of the epitaxial source / drain region.

In one embodiment, a method includes: forming a nanostructure over a fin; Forming a gate structure around the nanostructure; Building a source / drain epitaxial region adjacent to the gate structure; Depositing a first dielectric layer on the epitaxial source / drain region; Forming a first contact through the first dielectric layer to contact the epitaxial source / drain region; and forming a second contact through the fin to contact the source / drain epitaxial region and the first contact.

In some embodiments of the method, forming the first contact includes: forming a first opening extending through the first dielectric layer and into a top portion of the epitaxial source / drain region; and forming the first contact in the first opening. In some embodiments of the method, forming the second contact includes: forming a second opening that extends through the fin and into a lower portion of the epitaxial source / drain region, the second opening exposing the first contact; and forming the second contact in the second opening. In some embodiments of the method, forming the first opening includes: etching the first dielectric layer with a dry etch using ammonia and hydrogen fluoride gas; and etching the source / drain epitaxial region with a dry etch using chlorine gas, hydrogen bromide gas, and oxygen gas. In some embodiments of the method, the first opening extends a first distance into the upper portion of the epitaxial source / drain region and the second opening extends a second distance into the lower portion of the epitaxial source / drain region, wherein the the first distance and the second distance each lie in a range from 15 nm to 60 nm. In some embodiments, the method further comprises: replacing the gate structure with a second dielectric layer; Forming a first opening extending through the first dielectric layer and the second dielectric layer, the first opening exposing a sidewall of the epitaxial source / drain region; and forming the first contact in the first opening. In some embodiments of the method, forming the second contact includes: forming a second opening extending through the fin, the second opening exposing the first contact and the epitaxial source / drain region; and forming the second contact in the second opening. In some embodiments of the method, forming the first opening includes: etching the first dielectric layer with a dry etch using ammonia and hydrogen fluoride gas; and etching the second dielectric layer with a dry etch using fluorine-based gas and hydrogen or oxygen gas. In some embodiments of the method, a depth of the first opening is in a range from 40 nm to 120 nm.

The above describes elements of several embodiments that will enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or changing other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such respective constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and alterations therein without departing from the spirit and scope of this disclosure.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• US 63/016520 [0001]

Claims (20)

Apparatus comprising: a nanostructure; a gate structure surrounding the nanostructure; a source / drain epitaxial region adjacent to the gate structure; a first dielectric layer over a top portion of the source / drain epitaxial region; a second dielectric layer under a lower portion of the source / drain epitaxial region; and a power bar via extending through the first dielectric layer and the second dielectric layer, the power bar via physically and electrically coupled to the top portion and the bottom portion of the epitaxial source / drain region. Device according to Claim 1 wherein the busbar via extends through the epitaxial source / drain region. Device according to Claim 2 wherein the bus bar via comprises: a first source / drain contact extending through the first dielectric layer and into a top portion of the epitaxial source / drain region; and a second source / drain contact extending through the second dielectric layer and into a lower portion of the epitaxial source / drain region, the second source / drain contact physically and electrically connected to the first source / drain -Contact is coupled. Device according to Claim 2 , further comprising: a metal semiconductor alloy region surrounding portions of the bus bar via that extend through the source / drain epitaxial region. Device according to Claim 1 wherein the busbar via extends along a sidewall of the source / drain epitaxial region. Device according to Claim 5 wherein the bus bar via comprises: a first source / drain contact extending through the first dielectric layer, the first source / drain contact extending along the sidewall and a top surface of the epitaxial source / drain region; and a second source / drain contact extending through the second dielectric layer, the second source / drain contact extending along a lower surface of the epitaxial source / drain region. Device according to Claim 6 , further comprising: a metal semiconductor alloy region disposed between the bus bar via and each of the top surface, the sidewall, and the bottom surface of the source / drain epitaxial region. Apparatus comprising: a first interconnect structure comprising metallization structures; a second interconnection structure comprising a bus bar; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor and the first transistor including an epitaxial source / drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization structures and the conductive via contacting the epitaxial source / drain region. Device according to Claim 8 wherein the conductive via extends through the epitaxial source / drain region. Device according to Claim 8 wherein the conductive via extends along and contacts a sidewall, a top surface, and a bottom surface of the source / drain epitaxial region. Device according to Claim 8 wherein the conductive via extends along and contacts a lower surface of the source / drain epitaxial region, and extends along and is physically separated from a sidewall of the source / drain epitaxial region. Method comprising: Forming a nanostructure over a fin; Forming a gate structure around the nanostructure; Building a source / drain epitaxial region adjacent to the gate structure; Depositing a first dielectric layer on the epitaxial source / drain region; Forming a first contact through the first dielectric layer to contact the epitaxial source / drain region; and Forming a second contact through the fin to contact the epitaxial source / drain region and the first contact. Procedure Claim 12 wherein forming the first contact spacer comprises: forming a first opening extending through the first dielectric layer and into an upper one Extending portion of the epitaxial source / drain region; and forming the first contact in the first opening. Procedure Claim 13 wherein forming the second contact comprises: forming a second opening extending through the fin and into a lower portion of the epitaxial source / drain region, the second opening exposing the first contact; and forming the second contact in the second opening. Procedure Claim 13 wherein forming the first opening comprises: etching the first dielectric layer with a dry etch using ammonia and hydrogen fluoride gas; and etching the source / drain epitaxial region with a dry etch using chlorine gas, hydrogen bromide gas, and oxygen gas. Procedure according to Claim 12 wherein the first opening extends a first distance into the upper portion of the epitaxial source / drain region and the second opening extends a second distance into the lower portion of the epitaxial source / drain region, the first distance and the second distance are each in a range from 15 nm to 60 nm. Procedure according to Claim 12 , further comprising: replacing the gate structure with a second dielectric layer; Forming a first opening extending through the first dielectric layer and the second dielectric layer, the first opening exposing a sidewall of the epitaxial source / drain region; and forming the first contact in the first opening. Procedure Claim 17 wherein forming the second contact comprises: forming a second opening extending through the fin, the second opening exposing the first contact and the epitaxial source / drain region; and forming the second contact in the second opening. Procedure Claim 17 wherein forming the first opening comprises etching the first dielectric layer with a dry etch using ammonia and hydrogen fluoride gas; and etching the second dielectric layer with dry etching using a fluorine-based gas and hydrogen or oxygen gas. Procedure according to Claim 17 , wherein a depth of the first opening is in a range from 40 nm to 120 nm.

Images