DE102017129750A1 - Electronic switching system - Google Patents

Electronic switching system

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Publication number
DE102017129750A1
DE102017129750A1 DE102017129750.2A DE102017129750A DE102017129750A1 DE 102017129750 A1 DE102017129750 A1 DE 102017129750A1 DE 102017129750 A DE102017129750 A DE 102017129750A DE 102017129750 A1 DE102017129750 A1 DE 102017129750A1
Authority
DE
Germany
Prior art keywords
contacts
assignment
switching system
p1
p4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102017129750.2A
Other languages
German (de)
Inventor
Julian von Mendel
Hearty A. Zarzuela
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jinvent Ug (haftungsbeschrankt)
Jinvent Ug Haftungsbeschraenkt
Original Assignee
Jinvent Ug (haftungsbeschrankt)
Jinvent Ug Haftungsbeschraenkt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jinvent Ug (haftungsbeschrankt), Jinvent Ug Haftungsbeschraenkt filed Critical Jinvent Ug (haftungsbeschrankt)
Priority to DE102017129750.2A priority Critical patent/DE102017129750A1/en
Publication of DE102017129750A1 publication Critical patent/DE102017129750A1/en
Application status is Pending legal-status Critical

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/18Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
    • G05B19/19Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by positioning or contouring control systems, e.g. to control position from one programmed point to another or to control movement along a programmed continuous path
    • G05B19/40Open loop systems, e.g. using stepping motor
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure

Abstract

The present invention relates to an electronic switching system for interconnecting high-frequency digital or analog signals comprising a plurality of numbered general purpose I / O contacts (P1-P4), at least one serial or parallel digital communication interface (S) and at least one programmable interconnect unit (E2 ). The switching system according to the invention is characterized in that the communication interface (S) with an internal or external data memory (D) is connected such that a storage and / or modification of an assignment (Z) of the general purpose I / O contacts (P1-P4 ) are mutually possible and by means of the programmable switching unit (E2) the signals with a frequency of at least 4 MHz between the general purpose I / O contacts (P1-P4) unidirectional or bidirectional according to their assignment (Z) are passed through, wherein the Circuit comprises at least one means for synchronization of changes (Y) of the assignment (Z), in which these are cached and in a variant-conforming change of the assignment (Z) the stored information according to a defined specification by an external, with the communication interface (S) Connected control unit (C) are changeable.

Description

  • Technical area
  • The present invention relates to an electronic switching system for interconnecting high frequency digital or analog signals comprising a plurality of numbered I / O contacts, at least one serial or parallel digital communication interface, and at least one programmable interconnect unit.
  • State of the art
  • The use of I / O contacts in electronic circuits is commonplace and has steadily expanded with the advent of integrated circuits. In the development and productive use of electronic components every piece of flexibility and universality gained is of considerable benefit in terms of cost / benefit.
  • Snyder describes in "A Configurable input / output interface for a microcontroller" ( US 6825689 B1 ) an interface that allows dynamic interconnection of functional blocks on I / O contacts in microprocessors, the interconnect being configurable by the software of the microprocessor. Typical microprocessor solutions on the market strongly limit the number of function blocks that can be interconnected per I / O contact, and do not provide a configuration interface for adapting the interconnection matrix.
  • Snyder, et. al. describe in "Universal digital block interconnection and channel routing" ( US 7737724 B2 ) a programmable signal interconnection unit as a routing interface between multiple logic block and peripheral elements and I / O contacts within a microprocessor. The programming is done by means of the microprocessor RAM. A communication interface for communication with external control units or the use of the programmable signal switching unit as a separate component for rewiring electronic circuits is not provided here.
  • Menton describes in "Electronic control unit, in particular microcontroller, with a diagnosis interface changeable assignment between controls and input ports and between display elements and output ports" ( EP0822472 A1 ) a method that allows the free, unidirectional assignment of controls and display elements to the input / output ports of a control unit by means of a diagnostic interface.
  • Semtech's SX150 * series of GPIO expanders incorporate a programmable logic function (PLD). This can implement dynamically configurable combinatorial functions, including AND / OR gates and more sophisticated ones with up to 3-to-1 PLDs or two 3-to-2 PLDs. This functionality requires at least 2 input contacts, even for simple tasks such as passing an input signal directly to an output signal. the number of I / O contacts is decreasing rapidly.
  • Mortensel, et. al. describe in "A Matrix Switching System" ( US 20080123635 A1 ) a matrix switching system that can be configured by a control unit. This is composed of one or more "switch frames" which pass a set of balanced input signals to a selectable set of balanced output signals. Vertical and / or horizontal cascading of the switch frames can increase the number of input signal groups or the number of output signal groups up to 256x256.
  • Moore, et. al. create an "Adaptive Cable Interface" ( US 20140372631 A1 ), which enables a computer configurable cable interface. Software negotiates the signal interconnect with a connected device, eliminating the need for different cable adapters. Instead of buying new adapters, the signal interconnection can be modified by software update.
  • Presentation of the invention
  • The present invention is based on the object, an electronic switching system with a flexible interconnection of digital or analog, unidirectional or bidirectional, possibly symmetrical and possibly high-frequency signals with a matrix of general purpose input / output signal interconnections for the transmission of direct or modified To provide signals that converts a run-time modifiable interconnect matrix between a large number of input / output contacts and also incorporates at runtime reconfigurable logic operations and internal function blocks in the interconnect matrix, said configurations being transferable via serial or parallel digital communication interfaces.
  • According to the invention the above object is achieved according to the preamble of claim 1 in conjunction with the characterizing features. Advantageous embodiments and further developments of the switching system according to the invention are specified in the dependent subclaims.
  • According to the invention, an electronic switching system of the aforementioned type is characterized in that the communication interface with an internal or external data memory D is connected such that a storage and / or modification of an assignment of the general purpose I / O contacts to each other is possible and by means of the programmable switching unit E2 the signals having a frequency of at least 4 MHz between the general-purpose I / O contacts are unidirectionally or bidirectionally passed according to their assignment, the circuit having at least one means for the synchronization of changes Y the assignment Z comprises, in which they are cached and in a variant-conforming change of the assignment, the stored information according to a defined specification by an external, connected to the communication interface S control unit C are changeable.
  • The switching system according to the invention makes it possible to carry out configuration changes at any time and in real time. It thereby facilitates the rapid design and rapid reuse of electronic hardware, thereby opening up further application opportunities that take advantage of the dynamics of the electrical circuit.
  • The inventive switching system advantageously provides GPIO extensions and / or a connection for a plurality of input contacts for incoming signals from a single or multiple external components, and for a plurality of output contacts for outgoing signals to a single or multiple external components as well as for one Variety of bi-directional I / O contacts that connect two or more external bidirectional signal lines. The invention thus facilitates rapid hardware design and hardware modification by allowing significant portions of electrical circuits to be software modified to configure the connections to the I / O circuitry.
  • In another embodiment of the invention, to generate, modify, and / or process signals, internal functional blocks may provide additional functionality and include both configuration registers and virtual I / O contacts with no physically accessible contact, in the I / O register array with other signals are interconnectable. Such functional blocks may include but are not limited to: pulse width modulation (PWM) or clock output, additional communication interfaces such as UART, SPI, I2C, LIN, CAN, FlexRay, etc., logic blocks such as AND, OR, XOR, NOR , NEG, configurable signal delay, counters, etc. Function blocks can access the I / O register matrix or other function block configurations to provide further configuration options.
  • Furthermore, it may be advantageous that the configuration of the programmable switching unit E2 , which maps the assignment Z, as well as the configuration of the function blocks F1 - F4 by the control unit C can be done by a variety of communication interfaces, including but not limited to: UART, SPI, I2C, LIN, CAN, USB, TCP / IP, FlexRay, radio interfaces.
  • It is advantageous to provide at least one internal oscillator for the conversion of the switching system according to the invention in order to provide the internal clock of the I / O switching system. Also a power on reset generator and a software reset R1 are preferably part of the reaction. The software reset is controlled by the communication interface S via the control unit C and generates an RST signal which activates or reboots most of the system components.
  • Several switching systems that share a communication interface are individually addressable. The addressing is done by an addressing unit D0 supervised. For this purpose, slave select signals or assigned or automatically derived address information can be used in the communication protocol. If records with incorrect addressing are received, they will be discarded.
  • To address the electrical contacts, both the physically accessible and the internal, virtual I / O signals can be provided with unique addresses in order to be able to reference them in the communication protocol.
  • For command decoding, data sets received via the communication interface S are preferably received by the addressing unit D0 assigned, latched by an input data buffer SR, from a decoding unit D1 processed and to the command control logic D2 forwarded. There, the switch-on signal for other function blocks is switched depending on the received command. Status and error signals are provided by the status register control logic D3 held and between the command control logic D2 , the I / O control logic E1 , the read / write control RW, the internal function blocks F1 - F4 and the output data buffer ST exchanged.
  • When configuring the I / O contacts, they can be assigned multiple modes. This includes the output type, the input type (tristate), the input type with pull-up resistor and the input type with pull-down resistor. Two contacts can optionally by means of a Combination function K are used for symmetric signal transmission, internally, however, still handled as a singly addressed signal.
  • list of figures
  • Other objects, features, advantages and applications of the switching system according to the invention will become apparent from the following description of exemplary embodiments with reference to the drawings. All described and / or illustrated features, alone or in any combination form the subject matter of the invention, regardless of the summary in individual claims or their dependency.
  • In the drawings show
    • 1 a block diagram of the I / O switching system;
    • 2a a bidirectional signal interconnection and 2 B the method for transmitting the signal states;
    • 3 a flow chart for I / O read / write control;
    • 4 a cascading of the I / O switching system;
    • 5 the integration of virtual communication interfaces.
  • Embodiment of the invention
  • How out 1 As can be seen, the switching system according to the invention preferably comprises at least one communication interface S, an I / O control logic EA1, a programmable switching unit E2 in which the setpoint and actual values of the inputs and outputs are stored as well as internal function blocks F1 - F4 , the data operations on the register matrix of the programmable interconnect unit E2 and connected to the communication interface S.
  • Like also out 1 As can be seen, the configuration of the I / Os is preferably maintained in the I / O register matrix. For each individual I / O contact, this includes its mode, if necessary the output value, the interconnection state (off / unidirectional / bidirectional), the address of the interconnected contact and, if necessary, further function block-specific registers. Whenever the configuration of a GPIO is made or changed, the register matrix should be updated accordingly.
  • In addition, the control logic includes E1 the programmable switching unit E2 preferably also an I / O address decoder E3 , a read / write controller RW, configurable logic operations, and a variety of additional internal function blocks F1 - F4 including, but not limited to, PWM function blocks, BCD encoders, logic and signal operations such as signal delay units for phase shifting, configurable communication interfaces, etc. The register matrix of the programmable interconnect unit is divided into a block for physical contacts E2 .1 and a virtual contact block E2.2 , which enable the interconnection of exclusively internally used signals.
  • There are preferably different cascading options available to several of the switching systems by means of a coupling unit A to use in the composite, like out 4 seen. The I / O switching systems #1 . # 5 and # 6 are there in parallel with a control unit C connected. The switching systems #1 . # 2 . # 3 and # 4 on the other hand are serially connected in series. The switching system generally acts as a slave to the control unit C , In the serial connection, each switching system initiates control commands in a daisy chain to the successor. At the same time, the state of I / O interconnections made across two switching systems is transmitted. The maximum signal frequency decreases with the number of contacts simultaneously interconnected via switching systems, but synchronous switching is guaranteed. In the case of parallel interconnection, however, contacts interconnected via switching systems are not possible.
  • An input signal can be connected directly to an external target device via an output contact. This is referred to as a simple or unidirectional contact connection. In this case, for the output contact, the interconnected state with the destination address to the input signal is stored in the I / O register matrix, which maps the assignment Z. For all unidirectionally interconnected output contacts, the input value is then continuously obtained from the respective destination address and transmitted.
  • An input signal can be forwarded to several output contacts. A group of input signals (bus) can also be interconnected with a group of output contacts, which can be connected to a single or to a large number of external devices. The frequency of the interconnected signals can be at least, but not limited to, 4 MHz. For example, I / O contact 1 may be connected directly to I / O contacts 16 to 23, i. that a signal is forwarded to eight output contacts. On the other hand, the I / O contacts 1 to 8 could be connected to the I / O contacts 16 to 23, i. that eight different signals are passed through.
  • Bidirectional signaling is between at least, but not limited to, two I / O contacts possible. Even groups from more than two I / O contacts can be interconnected bidirectionally. For the interconnection of two bidirectional signals, these are externally held in each case by means of a resistor to a common reference voltage in a ground state. The bidirectional signal interconnection is achieved in two alternating phases. In the bus-keeper phase, the state of the signals is not changed, but completely externally controlled. However, the state is held and read via a bus holder circuit. In the copy phase, the state of contact P1 or P2 taken over to the other if and only if the read-in state on one of the contacts was not the same as the ground state and different from the state of the other contact and was not actively influenced during the last copy phase. Otherwise the signals will not be affected during this phase. The bus holder circuit is deactivated. 2 B Represents the behavior when external P2 in the copy phase T 0 - T 1 . T 2 - T 3 and T 4 - T 5 each state changes.
  • In a preferred implementation of the invention, commands can be buffered by a synchronization unit Y in order to execute them later together and to achieve configuration changes of several I / O contacts and function blocks virtually at the same time. For this purpose, before the first command to be buffered, a SYN command is transmitted, which leads to the pull-up of the internal sync_en signal. All subsequent commands are stored in the data buffer and only executed when the sync_en signal is reset by the TRG command.
  • In a preferred implementation, logic operations are available as internal function blocks. These can combine the value of one or more input signals by means of Boolean operations on an output signal. Such logic operations may include NEG, AND, NAND, OR, NOR and XOR.
  • The at least one communication interface may, for example, be UART, SPI, I2C, USB, TCP / IP, LIN, CAN, Flexray or radio interfaces. Internal function blocks can provide further, dynamically configurable communication interfaces as configuration or as freely usable data interfaces ( ).
  • In the preferred implementation of the invention, the startup configuration for I / O contacts and functional blocks after power-on is sourced from the basic configuration unit G from an internal or externally attached data memory D to prevent or relieve the control unit C.
  • The preferred implementation of the switching system further comprises an interrupt control logic I1 which allows simple or configurable interrupt contacts. These signal a state change on a group of I / O contacts, thereby allowing the control unit C to simplify the overall system monitoring. Configurable interrupt contacts can freely select the group of I / O contacts being monitored, the type of triggering interrupt event, or the length and type of generated interrupt signal.
  • Implementation of the invention may take the form of a standalone E-device, a logic switching program of an FPGA or as part of an integrated circuit, including, in particular, microprocessors, ASICs, ASSPs and SoCs.
  • The switching system according to the invention is not limited in its execution to the above-mentioned preferred embodiments. Rather, a variety of design variations are possible, which make use of the solution shown even with fundamentally different type of execution.
  • QUOTES INCLUDE IN THE DESCRIPTION
  • This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.
  • Cited patent literature
    • US 6825689 B1 [0003]
    • US 7737724 B2 [0004]
    • EP 0822472 A1 [0005]
    • US 20080123635 A1 [0007]
    • US 20140372631 A1 [0008]

Claims (7)

  1. An electronic switching system (L1) for interconnecting high frequency digital or analog signals comprising a plurality of numbered general purpose I / O contacts (P1-P4), at least one serial or parallel digital communication interface (S) and at least one programmable interconnect unit (E2) , characterized in that a) the communication interface (S) is connected to an internal or external data memory (D) such that a storage and / or modification of an assignment (Z) of the general purpose I / O contacts (P1-P4) b) by means of the programmable switching unit (E2), the signals with a frequency of at least 4 MHz between the general purpose I / O contacts (P1-P4) unidirectional or bidirectional according to their assignment (Z) are passed, wherein c) the circuit comprises at least one means for the synchronization of changes (Y) of the assignment (Z), in which they are cached and d) in a varian tenkonformen change the assignment (Z) the stored information according to a defined specification by an external, with the communication interface (S) connected control unit (C) are changeable.
  2. Electronic switching system according to Claim 1 , characterized in that internal function blocks (F1-F4) are provided for the generation, modification and / or processing of signals in the switching unit (E2) as a numbered, general purpose virtual I / O contacts (P5-P8) part of Assignment (Z) are.
  3. Electronic switching system according to Claim 1 or 2 characterized in that the programmable analog switch unit (VA) transmits analog signals having a frequency of at least 100 kHz between the general purpose I / O contacts (P1-P4) unidirectionally or bidirectionally according to their assignment (Z).
  4. Electronic switching system according to one of the preceding claims, characterized in that it comprises a combination function (K) of two general-purpose I / O contacts (P1-P4) each for a symmetrical general-purpose I / O contact (P1-P2) ,
  5. Electronic switching system (L5) according to one of the preceding claims, characterized in that a coupling unit (A) is provided for connection to at least one further, similar, electronic circuit, which due to the serial interconnection, an expansion of the number of general-purpose I / O Contacts (P1-P4) allowed.
  6. Electronic switching system according to one of the preceding claims, characterized in that a basic configuration unit (G) is provided which receives the initial assignment (Z) from an integrated or separate data memory (D).
  7. Electronic switching system according to one of the preceding claims, characterized in that a wireless coupling of the external control unit (C) to the communication interface (S) is provided.
DE102017129750.2A 2017-12-13 2017-12-13 Electronic switching system Pending DE102017129750A1 (en)

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Application Number Priority Date Filing Date Title
DE102017129750.2A DE102017129750A1 (en) 2017-12-13 2017-12-13 Electronic switching system

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Application Number Priority Date Filing Date Title
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0822472A1 (en) 1996-07-31 1998-02-04 Siemens Aktiengesellschaft Electronic controller, especially microcontroller, with allocation between input elements and input ports, and between display elements and output ports changable via diagnostic interface
US6825689B1 (en) 2000-10-26 2004-11-30 Cypress Semiconductor Corporation Configurable input/output interface for a microcontroller
US20080123635A1 (en) 2006-06-06 2008-05-29 Mortensen Keith Y Matrix switching system
US7737724B2 (en) 2007-04-17 2010-06-15 Cypress Semiconductor Corporation Universal digital block interconnection and channel routing
US20140372631A1 (en) 2013-06-12 2014-12-18 International Business Machines Corporation Adaptive cable interface

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0822472A1 (en) 1996-07-31 1998-02-04 Siemens Aktiengesellschaft Electronic controller, especially microcontroller, with allocation between input elements and input ports, and between display elements and output ports changable via diagnostic interface
US6825689B1 (en) 2000-10-26 2004-11-30 Cypress Semiconductor Corporation Configurable input/output interface for a microcontroller
US20080123635A1 (en) 2006-06-06 2008-05-29 Mortensen Keith Y Matrix switching system
US7737724B2 (en) 2007-04-17 2010-06-15 Cypress Semiconductor Corporation Universal digital block interconnection and channel routing
US20140372631A1 (en) 2013-06-12 2014-12-18 International Business Machines Corporation Adaptive cable interface

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