DE102012218284A1 - Drive unit for actuating transistor half bridge of direct current (DC)-DC converter, has input stage that is provided to form step-up converter unit, and inductor which is formed by primary coil and capacitor - Google Patents

Abstract

The drive unit (1) has an input stage (5) that is formed to generate alternating current (AC) voltage which is applied to a primary coil (20) of a transformer (7). The transformer is connected with control output units (8,9,11,13) on an output side for driving a transistor half-bridge (3). A step-up converter unit with an inductor and a capacitor (10) connected with the inductor in series is formed by a portion of the input stage. The inductor is formed by the primary coil and the capacitor. An independent claim is included for a DC-DC converter.

Description

State of the art

The invention relates to a driver unit for driving at least one transistor half-bridge. The driver unit has a transformer and an input stage connected to the transformer on the input side, in particular a semiconductor input stage. The input stage is designed to generate an alternating voltage and to charge the transformer on the input side, in particular a primary coil of the transformer, with the alternating voltage. The transformer is the output side connected to control outputs for driving the transistor half-bridge.

In driver units for driving a half-bridge, in particular a half-bridge of a DC-DC converter, there is the problem that the transformer which separates the control inputs of the half-bridge galvanically from the input stage, which generates the control signals for driving the half-bridge, in a pulse width modulated control in may saturate.

Disclosure of the invention

According to the invention, the drive unit has a capacitor and is designed to electrically charge the capacitor for generating an alternating voltage and to switch the electrical charge for generating a half-wave of the alternating voltage to a primary winding of the transformer. As a result, the current flowing through the primary coil of the transformer can advantageously be limited by the capacitance of the capacitor.

In a preferred embodiment of the driver unit, an up-converter is formed at least through part of the input stage. The boost converter has an inductance and a capacitance connected in series with the inductor. Preferably, the inductance is formed by the primary coil and the capacitance by the aforementioned capacitor.

In the embodiment of the input stage with the up-converter, the pulse-width-modulated current supply of the primary coil can advantageously be provided at low cost, and further advantageously a primary coil current can be limited by means of the up-converter.

In a preferred embodiment, the input stage is designed to switch a terminal of the primary coil and of the capacitor for a predetermined time interval to a ground potential, in particular to a ground terminal and to let the capacitor charged to generate a first half-wave of the AC voltage. The input stage is preferably further configured to connect a second terminal of the capacitor low impedance to the ground potential, in particular ground terminal for generating a second half-wave of the alternating voltage opposite to the first half-wave and thus to discharge the capacitor via the primary coil. As a result, an AC voltage with a primary coil current limited by the capacitor capacitance can advantageously be generated by the input stage. Another connection of the primary coil is preferably connected to a particular positive terminal for a supply voltage.

In a preferred embodiment, a first terminal of the capacitor is connected to the primary coil via a first semiconductor switch to a ground terminal and a second terminal of the capacitor via a second semiconductor switch connected to the ground terminal. Preferably, a diode is connected in parallel with the second semiconductor switch, so that the capacitor can hold its charge when the first semiconductor switch is turned on. Preferably, the diode is part of the up-converter.

By means of the arrangement thus formed, the generation of the alternating voltage for energizing the primary coil can be advantageous in terms of complexity-with only two semiconductor switches.

Preferably, the driver unit is designed such that the capacitor can be charged via the diode during a dead time of at least one of the semiconductor switches.

The dead time is a time interval at the beginning of which the transistor is driven to turn on or off and responsive to the drive delayed by the time interval. As a result, the dead time can be used to advantage.

In a preferred embodiment, the first semiconductor switch is a negative-conducting field-effect transistor, also called N-field-effect transistor, and the second semiconductor switch is a positive-conducting field-effect transistor, also called P-field-effect transistor. The source terminals of the field effect transistors are each connected to the ground terminal, wherein the diode is formed by a body diode of the second semiconductor switch.

The field-effect transistor is preferably an MIS-FET (MIS = Metal-Insulated-Semiconductor) or a MOS-FET (MOS = Metal-Oxide-Semiconductor).

This can advantageously the diode, in particular the diode of the up-converter, which a Maintaining the charge of the capacitor causes saved as an additional electronic component.

In a preferred embodiment, the driver unit is designed to alternately control the semiconductor switches alternately with the same switching time interval. As a result, a voltage doubling of the voltage drop across the capacitor relative to an operating voltage can advantageously be effected.

In a preferred embodiment, the transformer has two secondary windings on the secondary side, each secondary winding being connected to a transistor of two transistors of the transistor half-bridge. More preferably, the driver unit is formed, which can be driven with the voltages generated by the secondary windings mutually different transistors of the transistor half-bridge. As a result, a separate, galvanically isolated voltage source is advantageously formed for each transistor of the transistor half-bridge.

In a preferred embodiment, the driver stage comprises a clock generator which is designed to generate a clock signal. The driver stage is preferably designed to switch through or block the semiconductor switches in each case as a function of the clock signal. The clock generator is preferably connected to the input stage, in particular to an input of the input stage for the clock signal.

The invention also relates to a DC-DC converter, in particular a phase-shift full-bridge converter, with at least one driver unit according to the above-described type. The inverter has at least one full bridge. The full bridge preferably comprises two transistor half-bridges. Preferably, at least one transistor half-bridge of the transistor half-bridges, or both transistor half-bridges are connected on the input side to the driver unit.

The invention will now be explained below with reference to figures and further embodiments. Further advantageous embodiments emerge from the features of the dependent claims and the features described in the figures.

1 shows a driver unit, which is connected on the output side to a half-bridge of a power output stage, and for example forms part of an inverter, in particular an inverter;

2 shows an embodiment of a switching stage connecting a secondary winding to output terminals of the driver stage and having a bipolar transistor;

3 shows curves, each from the 1 represented driver unit represent signals generated.

1 shows an embodiment for a driver unit 1 , The driver unit 1 is the output side with a transistor half-bridge 3 connected. The driver unit 1 is formed, the transistor half-bridge 3 , especially a highside transistor 4 and a low side transistor 6 the transistor half-bridge 3 to control or block.

The driver unit 1 also has an entrance level 5 on. The driver unit 1 also has a transformer 7 on which a primary coil 20 and two secondary coils 22 and 24 having. The primary coil 20 and the secondary coils 22 and 24 each have an equal number of turns in this embodiment.

The transformer 7 is part of the input stage in this embodiment 5 , The secondary coil 22 is the output side via a switching stage 26 with the connections 8th and 11 connected. The driver unit 1 is trained over the connection 11 with a control terminal, in particular a gate terminal of the highside transistor 4 the half bridge 3 to be connected. The driver unit 1 is trained over the connection 8th with a source terminal of the highside transistor 4 to be connected.

The secondary coil 24 is the output side via a switching stage 28 with the connections 9 and 13 connected. The driver stage 1 is trained over the connection 13 with a control terminal of the low-side transistor 6 the half bridge 3 to be connected. The driver unit 1 is trained over the connection 9 with a source terminal of the low-side transistor 6 to be connected.

The half bridge 3 has a connection 39 for connecting to a supply voltage on and a connection 35 for connecting to a ground terminal of the supply voltage.

The drain terminal of the highside transistor 4 is with the connection 39 connected and the source terminal of the low-side transistor 6 is with the ground connection 35 connected. The source terminal of the highside transistor 4 is connected to the drain of the low-side transistor 6 connected, which with an output terminal 37 connected is.

The half bridge 3 may be part of an inverter, wherein the output terminal 37 With a connection of a load to be driven can be connected.

The switching stage 26 has a transistor 30 , in this embodiment, a P-type field effect transistor on.

A gate terminal of the transistor 30 is with a first connection of the secondary coil 22 connected, a second terminal of the secondary coil 22 is connected to a source terminal of the transistor 30 connected. A drain terminal of the transistor 30 is via a resistor to the gate terminal of the transistor 30 connected. The drain terminal of the transistor 30 is about another resistor with the connection 11 connected to a control terminal of a high-side transistor of a half-bridge. The transistor 30 is formed in the circuit arrangement described above, depending on one of the secondary coil 22 generated AC signal through the highside transistor durchzusteuern or block.

The switching stage 28 is like the switching stage 26 formed and has a P-field effect transistor 32 on. The outputs of the secondary coil 24 are connected to an input of the switching stage 28 connected, the outputs of the secondary stage 24 compared to the secondary coil 22 are reversed. This is due to the switching stage 28 on the input side in comparison to the switching stage 26 inverted input signal. That causes, if through the primary stage 20 an alternating current flows while a first half-wave of the alternating current, a transistor of the half-bridge is blocked, while the other transistor of the half-bridge is turned on.

The entrance level 5 has a connection 38 for a supply voltage for operating the input stage 5 on. The primary level 20 is with a first connection to the connector 38 connected for the supply voltage. A second connection of the primary coil 20 is with a drain terminal of an N-field effect transistor 14 connected. The transistor 14 is connected to its source terminal to a ground terminal.

Shown is also a diode 18 , which in this embodiment by a parasitic diode of the field effect transistor 14 is formed.

The drain terminal of the transistor 14 is with a first connection of a capacitor 10 connected. A second connection of the capacitor 10 is connected to a drain terminal of a P field effect transistor 12 connected. To the switching path of the transistor 14 is a diode 16 connected in parallel, which in this embodiment by a parasitic diode of the transistor 12 is formed.

The entrance level 5 also has a pulse width modulator 34 on, which input side with a timer 36 connected is. The timer 36 is formed for example by a quartz crystal. The pulse width modulator 34 is output with the control terminal 15 of the transistor 12 and with a control port 17 of the transistor 14 connected. The pulse width modulator 34 is formed switching pulses, in particular square pulses for driving or for blocking the transistors 12 and 14 to generate and output on the output side.

Through the primary coil 20 , the capacitor 10 and the parasitic diode 16 , continue through the transistor 14 , which forms a semiconductor switch in this embodiment, an up-converter is formed.

2 shows an embodiment of a switching stage 40 , which instead of the switching stage 26 or instead of the switching stage 28 in 1 Part of the driver unit 1 can be. The driver level 40 comprises a transistor, in this embodiment, PNP transistor, wherein an emitter terminal of the PNP transistor having an output 46 for connecting to a control terminal of a transistor of the half-bridge 3 connected is.

The collector terminal of the PNP transistor is connected to a terminal through a resistor 47 for connecting to a source terminal of the of the switching stage 40 to be switched transistor of the half-bridge connected.

The driver stage 40 also has an entrance 43 on, which with the exit 47 has the same potential. The driver stage 40 also has an entrance 42 on which has a resistor and a diode with the connection 46 connected is.

A base terminal of the PNP transistor is connected via a series resistor to the terminal 42 connected. The driver unit 40 can input side with the connections 42 and 43 with a secondary coil, for example the secondary coil 22 or the secondary coil 24 of in 1 represented transformer 7 , get connected. The previously described diode of the driver stage 40 has a rectifier function.

The diode also has the advantageous effect that the PNP transistor is protected in the case of the locked state against excessive reverse voltages.

3 shows an embodiment of signals, which of the in 1 shown driver stage have been generated. The signals are each represented by curves and on a common time axis 55 applied. An amplitude axis of the signals in each case represents a signal voltage in volts.

The function of in 1 illustrated driver stage 1 will now be described below in terms of 3 illustrated signals explained:

The curve 50 represents an output signal derived from the pulse width modulator 34 has been generated and the output side for controlling the transistor 12 is issued. The curve 51 represents an output signal derived from the pulse width modulator 34 has been generated and the output side for controlling the transistor 14 is issued. The curve 52 shows a temporal voltage curve of a voltage during the waveform through the curves 51 and 50 represented signals across the capacitor 10 in 1 is applied.

A curve 53 represents one of the switching stage 26 output on the output control voltage, which at the terminals 8th and 11 is applied. The curve 54 represents one from the driver stage 28 generated output signal for controlling a low-side transistor of an output side connected in the driver stage half-bridge.

During a first half-wave of a pulse width modulated control, which by the time interval 57 is represented, the transistor 12 from the pulse width modulator 34 activated for locking. During the time interval 57 in 3 becomes the transistor 14 which acts in the boost converter as a semiconductor switch, controlled by the pulse width modulator 34 via the control connection 17 turned on conductive. This will flow during the time interval 57 from the connection for the supply voltage 38 a primary coil current through the primary coil 20 over the closed switching transistor 14 to the ground connection 19 out. The parasitic diode 16 prevents the from the capacitor 10 stored charge during the switching of the transistor 14 can drain away. During the time interval 57 is the transistor 30 the switching stage 26 blocked. The highside transistor 4 the half bridge 3 can - driven by in the secondary coil 22 induced voltage - to be switched through. The transistor 32 the switching stage 28 is during the time interval 57 connected through. As a result, during the time interval 57 the low side transistor 6 the half bridge 3 blocked. During one on the time interval 57 following time interval 59 is controlled by the pulse width modulator 34 - the semiconductor switch 14 blocked. The parasitic diode 16 then causes the capacitor 10 - especially during a dead time 60 of the transistor 12 and or 14 - can be loaded. The primary coil 20 has during the time interval 57 built up a magnetic field and attempts by breaking the magnetic field, the current flow through the primary coil 20 maintain. The capacitor 10 can continue over the parasitic diode 16 to be charged. The further increase of the voltage of the capacitor 10 can however - controlled by the pulse width modulator 34 - By means of a switching of the transistor 12 in time interval 59 be prevented. During the time interval 59 is in 3 the transistor 12 controlled so that the voltage across the capacitor 10 on the primary coil 20 is switched. The primary coil 20 is so with a negative voltage to the primary coil voltage, which across the capacitor 10 lies, demagnetized.

During the time interval 59 is the transistor 32 the switching stage 28 blocked. The lowside transistor 6 This will happen during the time interval 59 connected through.

Vcs

= Spannung des Kondensators

Vcc

= Betriebsspannung der Eingangsstufe

D

= Tastverhältnis.

The of the pulse width modulator 34 generated pulse widths of the control pulses for driving or blocking the transistors 12 and 14 in this embodiment are each half of a period, comprising the time intervals 57 and 59 , The over the capacitor 10 applied voltage is calculated according to the aforementioned duty cycle, in the aforementioned embodiment, the duty cycle D = 50 percent, to Vcs = Vcc / (1-D) (1), in which mean

cs

= Voltage of the capacitor

Vcc

= Operating voltage of the input stage

D

= Duty cycle.

The operating voltage of the input stage is in the example of 3 15 volts. The voltage across the capacitor is twice the operating voltage, namely 30 volts.

Claims (9)

Driver unit ( 1 ) for driving at least one transistor half-bridge ( 3 ), whereby the driver unit ( 1 ) a transformer ( 7 ), and one with the transformer ( 7 ) input side connected input stage ( 5 ), wherein the input stage is adapted to generate an alternating voltage and a primary coil of the transformer ( 7 ) with the AC voltage, the transformer ( 7 ) on the output side with control outputs ( 8th . 9 . 11 . 13 ) for driving the transistor half-bridge ( 3 ), characterized in that at least part of the input stage ( 5 ) an up-converter with an inductance and a capacitor connected in series with the inductance is formed, wherein the inductance ( 22 ) through the Primary coil ( 22 ) and the capacitance through the capacitor ( 10 ) is formed. Driver unit ( 1 ) according to claim 1, characterized in that the input stage ( 5 ) is formed, for generating a first half-wave of the AC voltage, a terminal of the primary coil ( 57 ) and the capacitor ( 10 ) for a predetermined time interval ( 57 ) to a ground connection ( 19 ) and a charge of the capacitor ( 10 ) and to generate a second half-wave of the alternating voltage opposite the first half cycle, a second terminal of the capacitor ( 10 ) low impedance with the ground connection ( 19 ) and thus to discharge the capacitor via the primary coil. Driver unit ( 1 ) according to one of the preceding claims, characterized in that a first terminal of the capacitor ( 10 ) with the primary coil ( 22 ) and via a first semiconductor switch ( 14 ) with a ground connection ( 19 ) and a second terminal of the capacitor ( 10 ) via a second semiconductor switch ( 12 ) with the ground connection ( 19 ), wherein to the second semiconductor switch ( 12 ) a diode ( 16 ) is connected in parallel so that the capacitor ( 10 ) when switching through the first semiconductor switch ( 14 ) can hold his charge. Driver unit ( 1 ) according to claim 3, characterized in that the driver unit ( 1 ) is formed, that the Kondenstor ( 10 ) during a dead time ( 60 ) at least one of the semiconductor switches via the diode ( 16 ) can be loaded. Driver unit ( 1 ) according to claim 4, characterized in that the first semiconductor switch ( 14 ) is an N-field effect transistor and the second semiconductor switch ( 12 ) is a P-field effect transistor, wherein the source terminals of the field effect transistor ( 12 . 14 ) each with the ground connection ( 19 ), wherein the diode ( 16 ) by a body diode ( 16 ) of the second semiconductor switch ( 12 ) is formed. Driver unit ( 1 ) according to claim 4 or 5, characterized in that the driver unit ( 1 ), the semiconductor switches ( 12 . 14 ) each with a switching time interval ( 57 . 59 ) with the same switching time to control each other alternately. Driver unit ( 1 ) according to one of the preceding claims, characterized in that the transformer ( 7 ) on the secondary side, two secondary windings ( 22 . 24 ), each secondary winding ( 22 . 24 ) with a transistor ( 4 . 6 ) of two transistors ( 4 . 6 ) of a transistor half-bridge ( 3 ), with the secondary windings ( 22 . 24 ) generated voltages each to each other different transistors ( 4 . 6 ) of a transistor half-bridge ( 3 ) can be controlled. Driver unit ( 1 ) according to one of the preceding claims, characterized in that the driver unit ( 1 ) a pulse width modulator ( 34 ), which is formed, a clock signal ( 50 . 51 ) and the driver unit ( 1 ), the semiconductor switches ( 12 . 14 ) depending on the clock signal ( 50 . 51 ) through or block. DC-DC converter with at least one driver unit ( 1 ) according to one of the preceding claims, characterized in that the DC-DC converter comprises at least one full bridge comprising two transistor half-bridges ( 3 ), wherein at least one transistor half-bridge ( 3 ) on the input side with the driver unit ( 1 ) connected is.

Images