DE102012206721A1 - Method for controlling high-side switching element and low-side switching element, involves shortening time period of high state of control signals to duty cycle setting time period by twice guard time and fraction of guard time - Google Patents

Abstract

The method involves assigning control signal (GHSS) of high-side switching element or control signal (GLSS) of low-side switching element in dependence on the flow direction indication or dependent on the current direction specified first fraction of guard time associated with first control signal and the remaining second fraction of guard time associated with second control signal. The time period of the high state of respective control signals to the duty cycle setting time period of high state is shortened by twice the guard time and corresponding fraction of guard time. An independent claim is included for driver for driving high-side switching element and low-side switching element.

Description

The invention relates to the control of switching elements of a substantially balanced push-pull half-bridge in a converter, in particular an inverter or rectifier.

Inverters serve to convert a DC signal into an AC signal, for example for generating polyphase (in particular three-phase) alternating current from a DC voltage source, in order to supply, for example, a polyphase electrical machine in an electric motor driven vehicle with energy. Rectifiers work exactly the other way around, whereby a DC signal is generated from an AC signal (for example, a three-phase alternating current).

In an inverter or active rectifier, for example, a half-bridge is used for each phase. An exemplary half bridge 1 is in 1 shown. A half bridge 1 comprises at least one high-side switching element HSS between the upper high-side potential HSS and the phase connection PH and at least one low-side switching element LSS between the phase connection PH and the lower low-side potential LS. The switching elements HSS and LSS can, for example, as in 1 be realized as a self-blocking n-channel IGBT (insulated-gate bipolar transistor).

Between the upper high-side potential U _ZK / 2 and the phase connection PH and between the phase connection PH and the lower low-side potential -U _ZK / 2, at least one diode HSD or a diode LSD is additionally arranged. The diodes HSD and LSD serve to take over and maintain the current from the low-side switching element LSS or high-side switching element HSS when the low-side switching element LSS or high-side switching element HSS is opened and are no longer conductive.

The switching elements HSS and LSS are controlled by pulse width modulated (PWM) control signals G _HSS and G _LSS at the control inputs of the switching elements HSS and LSS. The control signals G _HSS and G _LSS are in the case of 1 around the gate potentials.

The pulse width modulated signals each change between two signal states, a high state with a higher potential and a low state with a lower potential. The width of a high-pulse and thus the duty cycle dc, d. H. the ratio between the width of the high pulse to the period, are modulated. The duty cycle is also referred to as duty cycle.

The half bridge 1 is essentially driven in push-pull, ie, neglecting any guard times is a control signal in a high state when the other control signal is in the low state, and vice versa.

When using n-channel IGBTs, substantially each switching element in a high state of the respective control signal G _HSS and G _{LSS is} conductive and in a low state of the respective control signal G _HSS and G _LSS not conducting.

It is also possible in each case more than a single high-side switching element HSS or low-side switching element LSS per half-bridge 1 be used. The individual high-side switching elements HSS and low-side switching elements LSS are then connected in series or in parallel and are driven in the same way.

In the following, the output current I _{PH of} the half-bridge 1 evaluated as positive if the output current I _PH from that of the half-bridge 1 flows out and flows for example in an electric machine. Accordingly, the output current I _{PH is} negative when the output current I _PH, for example, from an electric machine in the half-bridge 1 flows.

In 2 is the output current I _ph at positive current direction (ie I _PH > 0) shown at different switching states. In the left illustration in 2 conducts the high-side switching element HSS and the current flows through the high-side switching element HSS. In the right-hand illustration, the high-side switching element blocks HSS and the current flows via the lower diode LSD.

In 3 is the output current I _PH in the negative current direction (ie I _PH <0) shown at different switching states. In the left-hand illustration, the low-side switching element LSS blocks and the current flows via the upper diode HSD. In the right-hand illustration in 3 conducts the low-side switching element LSS and the current flows via the low-side switching element LSS.

4 shows an exemplary control of the switching elements HSS and LSS in a simplified representation. One or more setpoints SW, for example current setpoint values I _{q, soll} and I _{d, should be} in field coordinates, are compared with actual values IW and dependent on the deviation in a controller 2 a required duty factor dc _{CTRL of} the controller 2 certainly. From the required duty cycle dc _CTRL generates the bridge driver (PWM driver) 3 suitable pulse width modulated signals for controlling the control inputs of the switching elements HSS and LSS (in 4 are only the control signals G _HSS and G _LSS for a half-bridge 1 shown).

It must be distinguished between the required duty cycle dc _CTRL , that of the current controller 2 is requested, and the duty cycle dc _PWM , the bridge driver 3 then actually sets to control the high-side switching element HSS. The reason for this is a guard time in which neither the high-side switching element HSS nor the low-side switching element LSS conduct. This is the bridge driver 3 additionally considered, so that the actual from the bridge driver 3 Set duty cycle dc _PWM from the part of the controller 2 required duty cycle dc _CTRL deviates.

Under a duty cycle dc, the ratio of the time duration in which the gate potential G _{HSS has} a high potential (high state) and the high-side switching element HSS conducts, to the PWM period T _PWM understood the driving PWM signal , The duty cycles between 0 and 1. In the case of the controller 2 required duty cycle dc _CTRL is a desired time t _{ON, HSS} *, in the high-side switching element HSS should conduct, ie

In the case of the actually set duty cycle dc _PWM is the time t _{ON, HSS} , in the control input G _{HSS is} actually at a high potential and the high-side switching element HSS conducts, ie

In this case, in the case of the actually set duty cycle dc _PWM, the change in the time duration t _{ON, HSS in} relation to the time duration t _{ON, HSS} * is taken into account by the guard time.

As already mentioned above, a time period during which both the high-side switching element HSS and the low-side switching element LSS do not conduct is defined as the guard time.

In a conventional bridge driver 3 For example, each half of the guard time is assigned to the drive signal G _{HSS of} the high-side switching element HSS and the drive signal G _{LSS of} the low-side switching element LSS independently of the current direction. This has the consequence that the actual time duration t _{ON, HSS} , in which the high-side switching element conducts HSS, compared to the required duty cycle dc _CTRL corresponding time duration t _{ON, HSS} * systematically shortened by a protection time t _protection and the actual Duration t _{OFF, LSS} , in which the low-side switching element LSS blocks, compared to the required time period t _{OFF, LSS} systematically extended by a protection time t _{protection is} extended. This means that the pulse durations of both pulses are falsified by a guard time t _protection . This is in 5 shown.

In the top diagram in 5 the control signal curve G _HSS * of the high-side switching element HSS corresponding to the required duty cycle dc _CTRL is shown. The pulse duration of the high state is minimal here and is t _{ONmin, HSS} *. The diagram below shows the control signal curve G _LSS * of the low-side switching element LSS corresponding to the required duty cycle dc _CTRL . However, these two courses did not correspond to those on the part of the bridge driver 3 output control signal waveforms, as in the bridge driver 3 additional protection times are taken into account. The diagram below shows the actual profile of the control signal G _{HSS of} the high-side switching element HSS. In comparison with the top diagram, it follows that, in view of the assignment of the half guard time, the duration of the high state of the control signal G _HSS is twice the guard time (ie, 2 * t) compared with the high state time corresponding to the required duty cycle dc _{CTRL Protection} / 2) is shortened. The diagram below shows the actual profile of the control signal G _{LSS of} the low-side switching element LSS. In comparison with the second diagram, it follows that, in view of the assignment of the half protection time, the duration of the low state of the control signal G _LSS with respect to the time duration of the low state corresponding to the required duty cycle ds _CTRL by twice half the protection time t _protection (ie · T _protection / 2) is extended. On the other hand, due to the assignment of the half guard time, the time duration of the high state of the control signal G _{LSS is} shortened by twice half the guard time t _protection (ie, 2 * t _protection / 2) from the high state time corresponding to the required duty cycle dc _CTRL .

In 5 the ratios are shown when considering the minimum duty cycle, wherein the pulse width of the actual control signal G _HSS corresponds to the minimum pulse time t _Pmin . When considering the minimum duty cycle, a distinction must be made between that of the controller 2 desired minimum duty cycle dc _{min, CTRL} , that of the bridge driver 3 then set duty cycle dc _{min, PWM} and then arriving at the electric machine voltage U _EM , which depends on the current direction of the output current I _PH .

The one from the regulator 2 desired minimum duty cycle dc _{min, CTRL} is the duty cycle that the controller 2 can pretend, without causing the inverter - ie the hardware - a violation of a minimum pulse time t _Pmin or the protection time t _protection . A minimum pulse time t _Pmin between a rising control signal _edge and a falling control signal _edge or between a falling control signal edge and a rising control signal edge is to be maintained in order to keep the heating of the switching elements low due to the power loss at flank change. It may also be provided to provide a different pulse duration for an on-pulse than for an off-pulse.

In the case of the minimum duty cycle, therefore, the actual actual switch position of the high-side switching element HSS is decisive; this is the switch position that the bridge driver 3 provides. The minimum duty cycle dc _{min, PWM} , the bridge driver 3 without violating the minimum pulse time t _Pmin , the result is:

The minimum duty cycle dc _{min, CTRL} , the current regulator 2 due to the assignment of the guard time can still demand, then by a guard time divided by the switching period T _PWM , greater:

The phase voltage U _EM , which adjusts itself at these conditions at the terminal of the electrical machine, is of the current direction of the output current I _{PH of} the half-bridge 1 dependent. In the penultimate diagram in 5 is the time course of the pulse width modulated phase voltage U _EM for the case I _PH > 0 shown. The current I _PH flows through the high-side switching element HSS or through the lower diode LSD, the potential U _EM during the guard time is _{-U zk} / 2. When you turn on the high-side switching element HSS the potential U _EM changes to U _ZK / 2 and remains during the time period t _Pmin in this state before the potential U _EM effective only when the high-side switching element HSS again -U _ZK / 2 changes. With a minimum duty cycle and a positive current direction, the averaged voltage U _EM at the terminal of the electrical machine with respect to the intermediate circuit voltage U _{ZK is} between the high-side potential U _ZK / 2 and the low-side potential -U _ZK / 2:

In the bottom diagram of 5 is the time course of the pulse width modulated phase voltage U _EM for the case I _PH <0 shown. In the case of I _PH <0, the current flows through the low-side switching element LSS or through the upper diode HSD; the potential U _EM during the guard time is + Uzk / 2.

With a minimum duty cycle and negative current direction, the averaged voltage U _{EM, m} at the terminal of the electrical machine with respect to the intermediate circuit voltage U _ZK between the high-side potential U _ZK / 2 and the low-side potential -U _ZK / 2:

In 6 are the signals off 5 shown in the case of the maximum duty cycle, in which case the pulse duration of the actual bridge driver 3 set control signal G _{LSS of} the minimum pulse width t _Pmin corresponds. The first two diagrams again show the control signals G _HSS and G _LSS , that of the controller 2 correspond to specified duty cycle. The bottom two diagrams actually show the bridge driver 3 generated control signals G _HSS and G _LSS .

When considering the maximum duty cycle, a distinction is again made between that of the controller 2 desired maximum duty cycle, that of the bridge driver 3 then set duty cycle and then arriving at the electric machine voltage, which depends on the current direction.

The one from the regulator 2 desired maximum duty cycle is the duty cycle that the controller 2 can pretend, without causing the inverter - ie the hardware - a violation of the minimum pulse time t _Pmin or the guard time. In the case of the maximum duty cycle, therefore, the actual switch position of the low-side switching element LSS is decisive; this is the switch position that the bridge driver 3 provides.

The maximum duty cycle dc _{max, PWM} , the bridge driver 3 can still set, without the minimum pulse width t _{Pmin is violated} for the actual switch position of the low-side switching element LSS, results in:

The maximum duty cycle dc _{max, CTRL} , the current controller 2 is still a protection time greater than dc _{max, PWM} :

The voltage that occurs at these conditions at the terminal of the electrical machine depends on the current direction.

In the penultimate diagram in 6 is the time course of the pulse width modulated phase voltage U _EM for the case I _PH > 0 shown. The current I _PH flows through the high-side switching element HSS or through the lower diode LSD, the potential U _EM during the guard time is _{-U zk} / 2. When the high-side switching element HSS is switched off, the potential U _{EM changes} to -U _ZK / 2 and remains at this potential during the period t _Pmin plus 2 t _protection before the potential U _EM when the high-side switching element HSS is switched on back to + U _ZK / 2 changes. At maximum duty cycle and positive current direction, the average voltage U _EM at the terminal of the electrical machine with respect to the intermediate circuit voltage U _ZK between the high-side potential U _ZK / 2 and the low-side potential -U _ZK / 2 is:

In the bottom diagram of 6 is the time course of the pulse width modulated phase voltage U _EM for the case I _PH <0 shown. In the case of I _PH <0, the current flows through the low-side switching element LSS or through the upper diode HSD; the potential U _EM during the guard time is + U _zk / 2. At maximum duty cycle and negative current direction, the average voltage U _EM at the terminal of the electrical machine with respect to the intermediate circuit voltage U _ZK between the high-side potential U _ZK / 2 and the low-side potential -U _ZK / 2 is:

The following table summarizes the above results.

der beiden relativen Spannungswerte

bei maximalem Tastgrad dc_max und dem größten relativen Spannungswert

der beiden relativen Spannungswerte

bei minimalem Tastgrad dc_min gebildet:

For calculating the linear usable relative voltage range ΔU _{LINEAR, Relative} becomes the difference between the smallest relative voltage value

the two relative voltage values

at maximum duty cycle dc _max and the largest relative voltage value

the two relative voltage values

formed at minimum duty cycle dc _min :

From this it becomes clear that the linear modulation range ΔU _{LINEAR is relatively} smaller than 1 and the smaller the larger the guard time t _protection is. For example, if the guard time t _{protection is} 1/10 of the PWM period T _PWM , the linear drive range alone is reduced by 40% over the guard time.

Due to the limited linear control range ΔU _{LINEAR, relative to} the inverter, the construction output of an electrical machine controlled by the inverter can not be used completely or only with reduced efficiency. If, for example, 100% of the DC link voltage is available as a relative output voltage, a defined output power can be made available in the case of the design-limited phase current. When the relative output voltage decreases by the percentage described above, the output power is reduced to the same extent.

It is an object of the invention to provide a method and a corresponding control device for controlling the switching elements of a half-bridge in a converter, which or which allows an increase of the linear modulation range.

The object is solved by the features of the independent claims. Advantageous embodiments are described in the dependent claims.

A first aspect of the invention relates to a method for controlling a high-side switching element and a low-side switching element of at least one half-bridge in differential mode in a converter, in particular in an inverter for powering an electric motor driving a vehicle.

In a conventional bridge driver, for example, each half of the guard time is assigned to the drive signal of the high-side switching element and the drive signal of the low-side switching element, regardless of the current direction. In the method according to the invention, in contrast to the conventional method described above, the assignment of the guard time to the control signals of the two switching elements as a function of the current direction.

For this purpose, a current direction specification for the direction of the half-bridge output current of the at least one half-bridge is determined. The current direction indication may, for example, correspond to a current value of the output current of the half-bridge, which is either positive or negative depending on the current direction. For example, the current direction indication may alternatively correspond to a probability value for a positive (or alternatively negative) output current of the half-bridge. The current direction indication may be an indication of a current direction of the output current or, alternatively, an indication of a predicted future direction of the output current.

In the method, a pulse-width modulated first control signal for controlling the high-side switching element and a pulse-width modulated second control signal for controlling the low-side switching element in response to a duty cycle specification and the current direction indication are generated. The duty cycle specification is, for example, the signal dc _CTRL in 4 , The duty cycle specification need not be directly a duty cycle, but may also be, for example, the absolute time duration t _{ON, HSS} *, or another quantity that dictates the duty cycle.

In the method, it is assumed that substantially each switching element conducts in a high state of the respective control signal and does not conduct in a low state of the respective control signal. The switching elements are preferably IGBTs, in particular self-blocking n-channel IGBTs. However, other types of transistors can also be used, for example MOS-FETs.

In contrast to the current direction-independent assignment described in the inventive method in a first variant of the method according to the invention, a guard time during which both the first control signal and the second control signal in the low state, depending on the current direction specification of the first control signal of the high side Completely assigned to the second control signal of the low-side switch.

In an alternative second variant of the method, it can be provided that a first fraction of the guard time dependent on the current direction specification is assigned to the first control signal of the high-side switch and the remaining second fraction of the guard time to the second control signal of the low-side switch.

The assignment of the guard time or the fraction of the guard time to the respective control signal means that the duration of the high state of the respective control signal compared to the duration of the high state corresponding to the duty cycle specification by twice the associated guard time or the associated fraction of the guard time is shortened. However, the time duration is preferably only reduced to the extent that the minimum pulse duration t _Pmin permits. If the resulting time duration would _fall below the minimum pulse duration t _Pmin , preferably no pulse is triggered.

In the first variant of the method, in which either the first or the second control signal, the guard time is completely assigned, so depending on the current direction specification either the duration of the high state of the first control signal or the duration of the high state of the second control signal over the the duty cycle specification corresponding time duration of the high state substantially shortened by twice a guard time.

In the second variant of the method, in which the control signals are assigned two fractions of the guard time dependent on the current direction specification, the duration of the high state of the first control signal is twice the one of the high state of the high state in accordance with the duty cycle specification shortening the current direction dependent fraction of a guard time, while the duration of the high state of the second control signal over the duration of the duty cycle corresponding to the duty cycle of the high state is shortened by twice the remaining second fraction of the guard time.

The method according to the invention is based on the recognition that the low-side switching element is not current-carrying in the positive current direction (s. 2 ), while the high-side switching element in the negative current direction is not energized (s. 3 ). Since, in the case of a positive current direction, the current does not flow via the low-side switching element, in the case of a current direction identified as positive, the entire protection time or at least the greater part of the protection time can be attributed to the low-side switching element. This has the advantage that the high-side switching element can be switched unadulterated or at least with less distortion compared to the duty cycle specification of the controller.

Conversely, in the negative current direction, the high-side switching element is not energized. The entire guard time or at least the greater part of the guard time can therefore be assigned to the high-side switching element.

As will be shown below, increasing the maximum duty cycle, decreasing the minimum duty cycle and thus increasing the linear drive range of the converter can be achieved by the current direction-dependent assignment of the guard time to the two control signals. This leads to the improvement of the efficiency of the converter and an electrical machine controlled by the converter. In addition, the maximum output power of an electric drive system can be increased.

According to a preferred embodiment of the first variant of the method according to the invention, in the case where the half-bridge output current is positive, the guard time is completely assigned to the second control signal of the low-side switch. In the event that the half-bridge output current is negative, the guard time is fully associated with the first control signal of the high-side switch.

According to a preferred embodiment of the second variant of the inventive method is for the case that the half-bridge output current is positive, the second fraction, which is associated with the second control signal of the low-side switch, greater than the first fraction, which the first control signal assigned to the high-side switch. In the event that the half-bridge output current negative is, the first fraction, which is assigned to the first control signal of the high-side switch, greater than the second fraction, which is associated with the second control signal of the low-side switch.

The current direction indication is preferably a probability value for a positive (or negative output current), which is determined, for example, as a function of a probable current value, or the probable current value itself.

For example, when using a probability value, it is in the value range between 0 and 1. The probability value indicates, for example, the probability that the half-bridge output current is positive. In this case, for example, the first fraction (related to the guard time) corresponds to one less by the probability value, and then the second fraction (in terms of the guard time) corresponds to the probability value itself. For example, in the case that the probability value indicates the probability that the half-bridge output current is negative, the second fraction (related to the guard time) corresponds to one less by the probability value, while the first fraction (based on the guard time) corresponds to the probability value itself ,

A second aspect of the invention is directed to a drive device for driving the switching elements of at least one half-bridge. The drive device is set up to determine a current direction specification for the direction of the half-bridge output current of the at least one half-bridge. Furthermore, the drive device is set up to generate a pulse-width-modulated first control signal for controlling the high-side switching element and a pulse-width-modulated second control signal for controlling the low-side switching element as a function of a duty cycle specification and the current direction specification.

In a first variant of the drive device, a guard time is completely assigned to the first control signal of the high-side switch or the second control signal of the low-side switch as a function of the current direction indication. In a second variant, a first fraction of the guard time depending on the current direction is assigned to the first control signal of the high-side switch and the remaining second fraction of the guard time to the second control signal of the low-side switch.

The above statements on the method according to the invention according to the first aspect of the invention also apply correspondingly to the device according to the invention according to the second aspect of the invention; advantageous embodiments of the device according to the invention correspond to the described advantageous embodiments of the method according to the invention.

The invention will be described below with reference to the accompanying drawings with reference to several embodiments. In these show:

1 an embodiment of a conventional half-bridge 1 ;

2 the output current I _PH at positive current direction for two different switching states;

3 the output current I _PH in the negative current direction for two different switching states;

4 a conventional control of the switching elements HSS and LSS in a simplified representation;

5 Signal curves with minimum duty cycle and conventional assignment of guard time;

6 Signal curves at maximum duty cycle and conventional assignment of guard time;

7 Signal curves at maximum duty cycle, I _PH > 0 and assignment of the guard time t _protection to the control signal G _LSS ;

8th Signal curves at maximum duty cycle, I _PH <0 and assignment of the guard time t _protection to the control signal G _HSS ;

9 Signal curves at minimum duty cycle, I _PH > 0 and assignment of guard time t _protection to the control signal G _LSS ;

10 Signal curves at minimum duty cycle, I _PH <0 and assignment of the guard time t _protection to the control signal G _HSS ;

11 Input and output signals of an exemplary bridge driver according to the invention 3 '; and

12 an exemplary implementation of the determination of the control signals G _{HSS, U} and G _{LSS, U} for the switching elements HSS and LSS of the half bridge U.

In the first embodiment, depending on a current direction specification, a guard time is completely allocated to the first control signal G _{HSS of} the high-side switching element HSS or the second control signal G _{LSS of} the low-side switching element LSS.

In this case, use is made of the fact that the low-side switching element LSS is not live when the current direction of the current I _PH is positive (see FIG. 2 ) and the high-side switching element HSS in the negative current direction is not energized (s. 3 ). Since the current I _PH does not flow via the low-side switching element LSS in the case of a positive current direction, in the case of I _PH > 0, the entire guard time t _{protection can be added to} the control signal G _{LSS of} the low-side switching element LSS, without causing it a distortion of the phase voltage U _EM compared to the specification dc _{CTRL of} the controller 2 comes. Conversely, in the negative current direction, the high-side switching element HSS is not energized, so that for I _PH <0, the entire protection time can be assigned to the control signal G _{HSS of} the high-side switching element HSS.

Four different cases are presented below. Here, the current I _{PH is} positive or negative, with either the minimum or the maximum duty cycle are set: maximum duty cycle minimum duty cycle I _PH > 0 CASE I HSS or LSD energized, guard time is assigned to the control signal G _{LSS of} the LSS CASE III HSS or LSD energized, guard time is assigned to the control signal G _{LSS of} the LSS I _PH <0 CASE II LSS or HSD energized, guard time is assigned to the control signal G _{HSS of} the HSS CASE IV LSS or HSD energized, guard time is assigned to the HSS control signal G _HSS

In 7 the corresponding signal curves for case I are shown. Here, the current I _PH > 0 and thus either the high-side switching element HSS or the lower diode LSD conductive (s. 2 ). The first two diagrams show pulse-modulated control signals G _HSS * and G _LSS * of the high-side switching element HSS and the low-side switching element LSS, which would theoretically result in the implementation of the controller default dc _CTRL without consideration of a guard time. The third and fourth diagrams show the actually generated control signals G _HSS and G _{LSS of} the high-side switching element HSS and the low-side switching element LSS.

At maximum duty cycle dc _CTRL = dc _{CTRL, max} the on-time t _{ON, HSS} * of the dc _{ctrl, max} corresponding control signal G _HSS * maximum and the on-time t _{ON, LSS} * of the dc _{ctrl, max} corresponding control signal G _LSS * minimal (see first and second diagram). The on-time t _{ON, LSS} * of the control signal G _LSS * corresponds to the minimum pulse width t _Pmin and the on-time t _{ON, HSS} * of the control signal G _HSS * corresponds to T _PWM - T _Pmin . The on-time duration t _{ON, HSS} * of the control signal G _HSS * must not be increased further, since otherwise the time duration t _{OFF, HSS} * of the _OFF pulse would _fall below the minimum pulse duration t _Pmin . The current direction is detected in accordance with the method and, in the case of a positive current direction, the guard time is completely allocated to the control signal G _{LSS of} the low-side switching element LSS. Accordingly, the on-time duration t _{ON, LSS} (see fourth diagram) of the control signal G _{LSS of} the low-side switching element LSS is opposite to the on-time duration t _{ON, LSS} * corresponding to the duty cycle specification dc _CTRL (see second diagram). shortened by twice the associated protection time t _protection (conversely, the off-time duration of the control signal G _LSS compared to the specification by twice the protection time t _protection extended).

Since the time duration t _{ON, LSS is} less than the minimum pulse width t _Pmin and the low-side switching element LSS is not _{energized anyway} , the _ON pulse can also be suppressed when the minimum pulse width is undershot, without the output voltage U _EM changing ,

By the assignment of the guard time t _protection to the control signal G _{LSS of} the non-current-carrying switching element LSS correspond to 7 (in contrast to 6 ) the actual pulse width t _{ON, HSS of} the pulse width modulated control signal G _HSS (see third diagram) and the pulse width of the pulse width modulated phase voltage U _EM (see fifth diagram) switching in the same way 2 (see first diagram).

In 8th the waveforms for case II are shown. Here, the current I _PH <0 and thus either the low-side switching element LSS or the upper diode HSD conductive (s. 1 ). In addition, the duty cycle is maximum, ie dc _CTRL = dc _{CTRL, max} . The upper two diagrams correspond to those 7 , The current direction is detected in accordance with the method and, in the case of a negative current direction (ie, I _PH <0), the guard time is completely allocated to the control signal G _{HSS of} the high-side switching element HSS. Accordingly, the on-time duration t _{ON, HSS} (see third diagram) of the control signal G _{HSS of} the high-side switching element HSS is opposite to the on-time duration t _{ON, HSS} * corresponding to the duty cycle specification dc _CTRL (see first diagram). shortened by twice the protection time t _protection (conversely, the off-time duration of the control signal G _HSS compared to the specification by twice the protection time t _protection extended).

By the assignment of the guard time t _protection to the control signal G _{HSS of} the non-current-carrying switching element HSS correspond to 8th (in contrast to 6 ) the switching times of the pulse width modulated control signal G _LSS (see third diagram) and the pulse width modulated phase voltage U _EM (see fifth diagram) of the default by the controller 2 (see first and second diagram).

In 9 the corresponding signal curves for case III are shown. Here, the current I _PH > 0 and thus either the high-side switching element HSS or the lower diode LSD conductive (s. 2 ). In addition, the duty cycle is minimal, ie dc _CTRL = dc _{CTRL, min} . At a minimum duty cycle dc _CTRL = dc _{CTRL, min} is the time t _{ON, HSS} * a dc _{ctrl, min} corresponding control signal G _HSS * minimal and the off-time t _{OFF, LSS} * of dc _{ctrl, min} corresponding control signal G _LSS * minimal (see first and second diagram). The on-time duration t _{ON, HSS} * of the control signal G _HSS * corresponds to the minimum pulse width t _Pmin and the off-time duration t _{OFF, LLS} * of the control signal G _LSS * corresponds to t _Pmin . The current direction is detected in accordance with the method and, in the case of a positive current direction (ie, I _PH > 0), the guard time is completely allocated to the control signal G _{LSS of} the low-side switching element LSS. Accordingly, the on-time duration t _{ON, LSS} (see fourth diagram) of the control signal G _{LSS of} the low-side switching element LSS is opposite to the on-time duration t _{ON, LSS} * corresponding to the duty cycle specification dc _CTRL (see second diagram). shortened by twice the protection time t _protection (conversely, the off-time duration of the control signal G _LSS compared to the specification by twice the protection time t _protection extended).

By the assignment of the guard time t _protection to the control signal G _{LSS of} the non-current-carrying switching element LSS correspond to 9 (in contrast to 6 ) the actual pulse width t _{ON, HSS of} the pulse width modulated control signal G _HSS (see third diagram) and the pulse width of the similarly modulated phase voltage U _EM (see fifth diagram) of the specification by the controller 2 (see first diagram).

In 10 the waveforms for case IV are shown. Here, the current I _PH <0 and thus either the low-side switching element LSS or the upper diode HSD is conductive (s. 1 ). In addition, the duty cycle is minimal, ie dc _CTRL = dc _{CTRL, min} . The upper two diagrams correspond to those 9 , The current direction is detected in accordance with the method and, in the case of a negative current direction, the guard time is completely assigned to the control signal G _{HSS of} the high-side switching element HSS. Accordingly, the on-time duration t _{ON, HSS} (see third diagram) of the control signal G _{HSS of} the high-side switching element HSS is opposite to the on-time duration I _{ON, HSS} * corresponding to the duty cycle specification dc _CTRL (see first diagram). shortened by twice the protection time t _protection (conversely, the off-time duration of the control signal G _HSS compared to the specification by twice the protection time t _protection extended).

Since the time duration t _{ON, HSS is} less than the minimum pulse width t _Pmin and the high-side switching element HSS is not _{energized anyway, falls below} the minimum pulse width t _Pmin the on-pulse of the control signal G _{HSS can} also be suppressed without the output voltage U _EM changes.

By the assignment of the guard time t _protection to the control signal G _{HSS of} the non-current-carrying switching element HSS correspond to 10 (in contrast to 6 ) the switching times of the pulse width modulated control signal G _LSS (see fourth diagram) and the pulse width modulated phase voltage U _EM (see fifth diagram) of the default by the controller 2 (see first and second diagram).

• 1. In zwei Fällen (Fall I und Fall IV) würde durch die Zuordnung der Schutzzeit t_Schutz zu dem Steuersignale des jeweils nicht stromführenden Schaltelements eine Verletzung der minimalen Pulszeit t_Pmin auftreten. Da diese Verletzung das nicht stromführende Schaltelement beträfe, kann bei Unterschreiten der minimalen Pulszeit t_Pmin der Puls komplett unterdrückt werden, ohne dass es zu einer Verfälschung der Phasenspannung U_EM gegenüber der Vorgabe dc_CTRL des Reglers 2 kommt. Generell kann für den Fall, dass der Halbbrücken-Ausgangsstrom I_PH positiv ist, ein Ein-Impuls in dem Steuersignal G_LSS unterdrückt werden, wenn die Pulsbreite des Ein-Impuls eine bestimmte Pulsbreite, beispielsweise die minimale Pulsbreite t_Pmin oder die Hälfte der minimalen Pulsbreite t_Pmin, unterschreitet. Für den Fall, dass der Halbbrücken-Ausgangsstrom I_PH negativ ist, kann ein Ein-Impuls des Steuersignals G_HSS unterdrückt wird, wenn die Pulsbreite des Ein-Impuls eine bestimmte Pulsbreite, beispielsweise die minimale Pulsbreite t_pmin oder die Hälfte der minimalen Pulsbreite t_Pmin, unterschreitet.
• 2. Durch die Zuordnung der Schutzzeit t_Schutz zu dem Steuersignal des jeweils nicht stromführenden Schaltelements ergibt sich bei maximalem Tastgrad (s. 7 und 8) unabhängig von der Schutzzeit das folgenden Potential an der elektrischen Maschine bezogen auf die Spannung U_ZK:
  
• 3. Durch die Zuordnung der Schutzzeit t_Schutz zu dem Steuersignal des jeweils nicht stromführenden Schaltelements ergibt sich bei minimalem Tastgrad (s. 9 und 10) unabhängig von der Schutzzeit das folgenden Potential an der elektrischen Maschine bezogen auf die Spannung U_ZK:
  

From the four cases I-IV described above, the following findings can be derived:

• 1. In two cases (case I and case IV) would occur by the assignment of the guard time t _protection to the control signals of each non-energized switching element violation of the minimum pulse time t _Pmin . Since this violation would affect the non-current-carrying switching element, the pulse can be completely suppressed when the minimum pulse time t _{Pmin is undershot} , without the phase voltage U _{EM being} falsified with respect to the specification dc _{CTRL of} the regulator 2 comes. In general, in the case where the half-bridge output current I _{PH is} positive, an on-pulse in the control signal G _{LSS can be} suppressed when the pulse width of the on-pulse is a certain pulse width, for example, the minimum pulse width t _Pmin or half of the minimum _Pulse width t _Pmin , _falls below. In the event that the half-bridge output current I _{PH is} negative, an on-pulse of the control signal G _{HSS can be} suppressed if the pulse width of the on-pulse has a certain pulse width, for example the minimum pulse width t _pmin or half of the minimum pulse width t _Pmin , _falls below.
• 2. The assignment of the guard time t _protection to the control signal of the respective non-current-carrying switching element results in maximum duty cycle (s. 7 and 8th ) regardless of the protection time the following potential on the electrical machine with respect to the voltage U _ZK :
  
• 3. The assignment of the guard time t _protection to the control signal of each non-energized switching element results at a minimum duty cycle (s. 9 and 10 ) regardless of the protection time the following potential on the electrical machine with respect to the voltage U _ZK :
  

In the following table, the relative potential U _{EM is} compared with respect to the voltage U _ZK for two different assignments of protection time, namely on the one hand for the conventional current direction independent assignment of half the guard time t _protection to the control signal of the high-side switching element (as described in the introduction to the description), and on the other hand for the above-described current direction-dependent assignment of the guard time t _protection to the control signal of the non-energized switching element.

From the difference between the respective above-indicated relative potential at the maximum duty cycle and the respective above-indicated relative potential at a minimum duty cycle results in the linear modulation range .DELTA.U _{LINEAR, Relative of} the inverter, as shown in the table below for the conventional current direction independent assignment of the guard time t _protection and _{protection is} indicated for the current direction-dependent assignment of the guard time t according to the invention.

As can be seen from the above table, the current-direction-dependent assignment of the guard time t _protection to the control signal of the respective non-current-carrying switching element increases the linear modulation range ΔU _{LINEAR, relative to} the inverter by 4 t _protection / T _PWM .

The above-described current direction-dependent assignment of the protection time t _protection to the control signal of the non-current-carrying switching element should then be used if the current direction can be clearly determined.

If the amplitude of the current I _{PH is} low, the direction of the current I _{PH can} often not be reliably determined due to a current noise or an offset. In addition, the determined current direction should preferably be valid at the future point in time at which the control signals, which in turn are based on the determined current direction, become effective and actuate the switching elements of the half-bridge accordingly.

If the current sign can not be determined reliably, preferably no exclusive assignment of the guard time t _protection to one of the two switching elements should be made, since the current-carrying switching element can not be clearly identified. Instead, a fraction of the guard time t _{protection is} assigned to the control signal G _{HSS of} the high-side switch HSS and the remaining fraction of the protection time t _{protection to} the control signal G _{LSS of} the low-side switch LSS. The fractions depend on a probability p _SZ that the current I _{PH is} positive (or alternatively negative).

The probability p _SZ is, for example, a factor between 0 and 1, ie 0 ≤ p _SZ ≤ 1

In the following it is assumed that the value p _SZ indicates the probability with which the current I _{PH is} positive (and flows either through the high-side switching element HSS or the lower diode LSD). This value p _SZ , for example, per half-bridge 1 determined and to the bridge driver 3 ' (S. 11 ) to hand over. The bridge driver 3 ' assigns per half-bridge, the protection time t _protection the control signal of the high-side switching element HSS and the control signal of the low-side switching element LSS as a function of the respective half-bridge related probability p _{SZ, U} , p _{SZ, V} , p _{SZ, W,} for example in the following way:
t _{protection, U, HSS} = (1-P _{SZ, U} ) t _protection (assignment of the fraction of the guard time t _protection to the control signal G _{HSS of} the high-side switching element HSS of the half-bridge U as a function of the value p _{SZ, U} )
t _{protection, U, LSS} = p _{SZ, U} · t _protection (assignment of the fraction of the guard time t _protection to the control signal G _{LSS of} the low-side switching element LSS of the half-bridge U as a function of the value p _{SZ, U} )
t _{protection, V, HSS} = (1 -p _{SZ, U} ) t _protection (assignment of the fraction of the guard time t _protection to the control signal G _{HSS of} the high-side switching element HSS of the half-bridge V as a function of the value p _{SZ, V} )
t _{protection, V, LSS} = P _{SZ, V} · t _protection (assignment of the fraction of the guard time t _protection to the control signal G _{LSS of} the low-side switching element LSS of the half-bridge V as a function of the value p _{SZ, V} )
t _{protection, W, HSS} = (1-p _{SZ, W} ) t _protection (assignment of the fraction of the guard time t _protection to the control signal G _{HSS of} the high-side switching element HSS of the half-bridge W as a function of the value p _{SZ, W} )
t _{Protection, W, LSS} = p _{SZ, W} · t _Protection (assignment of the fraction of the guard time t _Protection to the control signal G _{LSS of} the low-side switching element LSS of the half-bridge W as a function of the value p _{SZ, W} ).

The bridge driver 3 ' So is preferably able, the protection time t _protection depending on the respective value p _{SZ, U} , p _{SZ, V} and p _{SZ, W} in the manner indicated above the control signal G _{HSS of} the high-side switching element HSS or the control signal G. _{LSS of} the low-side switching element LSS assign.

In the case of p _{SZ, U} , p _{SZ, V} or p _{SZ, W} is 0.5 for the respective half-bridge, the protection time t _protection in equal parts the control signal G _{HSS of} the high-side switching element HSS and the control signal G _LSS of Low-side switching element associated with LSS. This then corresponds to the conventional assignment, which is discussed in the introduction to the description.

In the case of p _{SZ, U} , p _{SZ, V} or p _{SZ, W} equal to 1, ie the current I _{PH of} the respective phase U, V and W is certainly positive, the protection time t _{protection is} completely the control signal for the respective half-bridge G _{LSS associated with} the low-side switching element LSS, as related to 7 and 9 was discussed.

In the case of p _{SZ, U} , p _{SZ, V} or p _{SZ, W} equal to 0, ie the current I _{PH of} the respective phase U, V and W is certainly negative, the protection time t _{protection is} completely the control signal for the respective half-bridge G _{HSS associated with} the high-side switching element HSS, as related to 8th and 10 was discussed.

For determining the probabilities p _{SZ, U} , p _{SZ, V} or p _{SZ, W} preferably no additional sensors or electronic circuits are used. Instead, the probabilities p _{SZ, U} , p _{SZ, V} and p _{SZ, W are} determined with the already existing information by a suitable method. The probability values p _{SZ, U} , p _{SZ, V} or p _{SZ, W} preferably relate to the output current of the respective half-bridge at a future time at which the assignment of the protection time based on the same probability value is effective, ie at which the control signals in turn based on the determined probability value, become effective and control the switching elements of the respective half-bridge accordingly. Thus, it is preferable to predict a current direction for a future time.

The probability values p _{SZ, U} , p _{SZ, V} and p _{SZ, W} are determined as a function of probable output currents of the respective half-bridges. The probable output currents of the half-bridges are current values, which are preferably determined as a function of nominal values of the current regulation, and which are preferably predicted for a future point in time.

The determination of the probable output currents of the half bridges can, for example _{, be} carried out in field coordinates as a function of the current desired values i _{q, soll} and i _d . In this case, the current setpoint i _{q, is intended to} describe the torque-forming setpoint current and the current setpoint i _{d, soll} describes the field-forming current. The currents in field coordinates result from geometric addition of the currents of the different phases. The coordinate system of i _{d, soll} and i _{q, should} rotate with the electrical angular frequency ω _el , with which rotates the rotor of the electric machine, so that i _{d, soll} and i _{q, should be} constant in the stationary case.

Depending on the instantaneous current setpoint values i _{q, soll} and i _d, in field coordinates, the current position in field coordinates φ _el , the current electrical angular frequency ω _el and optionally the time duration t _delay up to the future point in time for which the prognosis should apply, current setpoint values i _{α, soll} and i _{β, should be} determined whose coordinate system, in contrast to i _{d, soll} and i _{q, should} not rotate with the electrical angular frequency ω _el , but is stationary (thus these quantities are sinusoidal in the stationary case) :

The current current setpoints i _{α, soll} and i _{β, soll} can be transformed into current setpoint values i _{U, soll} , i _{V, soll} , i _{W, soll} for the three phases U, V, W in the following way:

The instantaneous current setpoint values i _{PH, U, soll} , i _{PH, V, should} , i _{PH, W, should} correspond to probable output currents of the half-bridges assigned to the phases U, V and W at a time which is opposite to the underlying instant of the setpoint current values i _{d , should} and i _{q, should be} around the time t _delay in the future.

Based on the current setpoint values i _{PH, U, soll} , i _{PH, V, soll} , i _{PH, W, soll} , the probability values p _{SZ, U} , p _{SZ, V} or p _SZ can be set for the three phases U, V and W. _W , which indicate the probability with which the bridge _output current I _{PH of} the respective phases U, V or W is positive, for example in the following way: p _{SZ, U} = 0.5 + r · i _{PH, U, soll} p _{SZ, V} = 0.5 + r · i _{PH, V, soll} p _{SZ, W} = 0.5 + r * i _{PH, W, soll}

With the factor r> 0, the trustworthiness of the predicted current values i _{PH, U, soll} , i _{PH, V, soll} , i _{PH, W, soll can be} set. In order to prevent the probability values p _{SZ, U} , p _{SZ, V} or p _{SZ, W} becoming greater than 1 or less than 0, they are correspondingly limited, so that the following applies: 0 ≤ p _{SZ, U} ≤ 1 0 ≤ p _{SZ, V} ≤ 1 0 ≤ p _{SZ, W} ≤ 1

The course of the current values i _{PH, U, soll} , i _{PH, V, soll} , i _{PH, W, soll} is in the stationary case sinusoidal around the zero line. For a current value i _{PH, U, soll} , i _{PH, V, soll} , i _{PH, W, soll} of 0, the corresponding probability value p _{SZ, U} , p _{SZ, V} or p _{SZ, W is} 0.5, ie with 50% probability the current direction is positive and with 50% probability the current direction is negative.

Other methods are also conceivable which serve to determine the probability values p _{SZ, U} , p _{SZ, V} , p _{SZ, W.} For example, in a system in which the phase voltages are detected, it would be possible to identify the current zero crossing by changing the effective pulse width. The probability values p _{SZ, U} , p _{SZ, V} , p _{SZ, W} can then be determined from the identified signal.

In 11 is an exemplary bridge driver 3 ' represented, which as input signal the duty cycle specification dc _CTRL on the part of the controller 2 , the period duration T _PWM for the pulse width modulated output signals, the probability values p _{SZ, U} , p _{SZ, V} , p _{SZ, W} and the protection period t receives _protection . The bridge driver 3 ' calculates in response to these input variables control signals G _{HSS, U} and G _{LSS, U} for the half-bridge 1 the phase U, control signals G _{HSS, V} and G _{LSS, V} for the half-bridge 1 the phase V and control signals G _{HSS, W} and G _{LSS, W} for the half-bridge 1 phase W. The probability values p _{SZ, U} , p _{SZ, V} , p _{SZ, W} are in the block 11 depending on the current setpoint values i _{d, soll} and i _{q, should be determined} in the manner described above.

The bridge driver 3 ' , which generates the PWM control signals, assigns the protection time t _protection not current direction independent in each case half the high-side switching element HSS and the low-side switching element LSS the respective phase U, V and W, but performs the assignment depending on the half-bridge-dependent current direction probability p _{SZ, U} , p _{SZ, V} , p _{SZ, W} through. The probability value p _{SZ, U} , p _{SZ, V} , p _{SZ, W} indicates, for example, the probability with which the current flows through the high-side switching element HSS of the respective half-bridge. In the case of p _{SZ, i} = 1 with i ε {U, V, W}, the protection time t _{protection of} the respective half-bridge i is then completely assigned to the low-side switching element LSS of the respective half-bridge; In the case of p _{SZ, i} = 0, the protection time t _{protection is} completely assigned to the high-side switching element HSS of the respective half-bridge i.

In 12 shows an exemplary implementation of the generation of the control signals G _{HSS, U} and G _{LSS, U of} the half-bridge of the phase U. From the part of the controller 2 delivered duty cycle dc _CTRL is a duty cycle dc _{CTRL, LSS} for the low-side switching element LSS according to dc _{CTRL, LSS} = 1 - dc _CTRL calculated. The duty cycle dc _{CTRL, HSS} for the high-side switching element HSS is identical to the duty cycle dc _CTRL , which the controller 2 supplies.

The duty cycle values dc _{CTRL, HSS} and dc _{CTRL, LSS} are modified, according to the division of the protection time t _protection on the two control signals G _{HSS, U} and G _{LSS, U} : From the associated fraction t _{protection, U, HSS} the Protection time t _Protection to the control signal G _{HSS, U of} the high-side switching element HSS and the PWM period T _PWM is according to (t _{protection, U, HSS} / T _PWM ) · 2 a reduction rdc _{HSS, U of} the duty cycle for the high -Side switching element HSS due to the assigned fraction t _{protection, U, HSS} of protection time t _protection calculated. The reduction rdc _{HSS, U of} the duty cycle is subtracted from the duty cycle value dc _{CTRL, HSS} according to dc _{CTRL, HSS} -rdc _{HSS, U} = dc _{PWM, HSS, U.} The resulting duty cycle dc _{PWM, HSS, U} is that of the bridge driver 3 ' then set duty cycle for the high-side switching element HSS phase U on. This duty cycle dc _{PWM, HSS, U} is in the block 10 in a pulse width modulated signal G _{HSS, U} with the duty cycle dc _{PWM, HSS, U} converted.

In a corresponding manner, from the associated fraction t _{protection, U, LSS of} the protection time t _protection to the control signal G _{LSS, U of} the low-side switching element LSS and the PWM period T _PWM according to (t _{protection, U, LSS} / T _PWM ) · 2 a reduction rdc _{LSS, U of} the duty cycle for the low-side switching element LSS due to the associated fraction t _{protection, U, LSS} the protection time t _protection calculated. The reduction rdc _{LSS, U of} the duty cycle is subtracted from the duty cycle value dc _{CTRL, LSS} according to dc _{CTRL, LSS} - rdc _{LSS, U} = dc _{PWM, LSS, U.} The resulting duty cycle dc _{PWM, LSS, U} gives that from the bridge driver 3 ' then set duty cycle for the low-side switching element LSS of the phase U on. This duty cycle dc _{PWM, LSS, U} is in the block 10 in a pulse width modulated signal G _{LSS, U} with the duty cycle dc _{PWM, LSS, U} converted. The pulse width modulated signals G _{HSS, U} and G _{LSS, U} are synchronized with each other so that on a falling edge of the signal G _{HSS, U} or the signal G _{LSS, U} after the time t _{protection, U, LSS} + t _{protection, U , HSS} follows the rising edge of the signal G _{LSS, U} or the signal G _{HSS, U} (except when a pulse is suppressed).

Claims (10)

Method for controlling a high-side switching element (HSS) and a low-side switching element (LSS) of at least one half-bridge which is driven in a differential mode ( 1 ) with the two switching elements and at least two diodes (HSD, LSD) in a converter, with the steps: - determining a current direction specification (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) for the direction of the half-bridge output current ( I _PH ) of the at least one half-bridge ( 1 ); and - generating a pulse width modulated first control signal (G _HSS ) for controlling the high-side switching element (HSS) and a pulse-width modulated second control signal (G _LSS ) for controlling the low-side switching element (LSS) in response to a duty cycle specification (dc _CTRL ) and the current direction indication (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ), wherein substantially each switching element (HSS, LSS) conducts in a high state of the respective control signal and in a low state of the respective control signal does not conduct, wherein - a guard time (t _protection ) during which both the first control signal (G _HSS ) and the second control signal (G _LSS ) are in the low state, the first control signal (G _HSS ) of the high-side switching element (HSS) or the second control signal (G _LSS ) of the low-side switching element (LSS) depending on the current direction indication is fully assigned or - a dependent on the current direction indication first fraction of the guard time (t _protection ) the first control signal (G _HSS ) of the high-side switching element (HSS) and the remaining second fraction of the guard time (t _protection ) associated with the second control signal (G _LSS ) of the low-side switching element (LSS), and the time duration (t _{ON , HSS} , t _{ON, LSS} ) of the high state of the respective control signal (G _HSS , G _LSS ) with respect to the time duration (t _{ON, HSS} *, t _{ON, LSS} *) corresponding to the duty cycle specification (dc _CTRL ) State is shortened by twice the assigned protection time or the associated fraction of the protection period. The method of claim 1, wherein - in the event that the half-bridge output current (I _PH ) is positive, - the guard time (t _protection ) is completely associated with the second control signal (G _LSS ) of the low-side switching element (LSS) - the second fraction is greater than the first fraction, - in the event that the half-bridge output current (I _PH ) is negative, - The guard time is completely associated with the first control signal (G _HSS ) of the high-side switching element (HSS) or - the first fraction is greater than the second fraction. Method according to one of the preceding claims, wherein the current direction specification corresponds to a probability value (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) for a positive or negative half-bridge output current (I _PH ). Method according to claim 3, wherein the probability value (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) is a value in the value range between 0 and 1 and - the probability value (p _{SZ, U} , p _{SZ, V} , p _{SZ , W} ) indicates the probability that the half-bridge output current (I _PH ) is positive, the first fraction - related to the guard time - one minus the probability value (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) and the second fraction - in relation to the guard time - corresponds to the probability value (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ), or - the probability value (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) Probability indicates that the half-bridge output current (I _PH ) is negative, the second fraction - referred to the guard time - equals one minus the probability value (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) and the first fraction - related to the guard time - the probability value (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ). Method according to one of Claims 3 or 4, the probability value (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) being determined as a function of a particularly probable output current, in particular according to the following relationship: p = 0.5 + r · i, where p corresponds to the probability value, i corresponds to the output current and r is a constant or variable quantity and the probability value p is limited to a value range between 0 and 1. Method according to one of the preceding claims, wherein the current direction indication (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) is an indication of a predicted future direction of the half-bridge output current (I _PH ) at a future time at which the the assignment of the protection time based on the current direction indication is effective. Method according to one of the preceding claims, wherein the step of determining a current direction specification (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) comprises: - determining a probable value of the output current as a function of two current setpoint values (i _{d, soll} , i _{q, should} ) in field coordinates. Method according to one of the preceding claims, wherein - in the event that the half-bridge output current (I _PH ) is positive, a high pulse of the second control signal (G _LSS ) is suppressed when the pulse width (t _{ON, LSS} ) of the high Pulse of the second control signal (G _LSS ) is less than a certain pulse width, in particular a minimum allowable pulse width (t _Pmin ), and - in the event that the half-bridge output current (I _PH ) is negative, a high pulse of the first control signal (G _HSS ) is suppressed when the pulse width (t _{ON, HSS} ) of the high pulse of the first control signal (G _HSS ) is less than a certain pulse width, in particular a minimum allowable pulse width (t _Pmin ). Method according to one of the preceding claims, wherein the switching elements are n-channel IGBTs. Control device ( 3 ' . 11 ) for a high-side switching element (HSS) and a low-side switching element (LSS) of at least one essentially half-bridge ( 1 ) with the two switching elements and two diodes (HSD, LSD) in a converter, wherein the drive device is set up, - a current direction indication (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) for the direction of the half-bridge output current ( I _PH ) of the at least one half-bridge ( 1 ), - a pulse width modulated first control signal (G _HSS ) for controlling the high side switching element (HSS) and a pulse width modulated second control signal (G _LSS ) for controlling the low side switching element (LSS) in response to a duty cycle specification (dc _CTRL ) and the current direction indication (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) to produce, wherein substantially each switching element in a high state of the respective control signal conducts and not in a low state of the respective control signal a protection time (t _protection ) during which both the first control signal (G _HSS ) and the second control signal (G _LSS ) are in the low state, the first control signal (G _HSS ) of the high-side switching element ( HSS) or the second control signal (G _LSS ) of the low-side switching element (LSS) in dependence of the current direction indication (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) is completely assigned, or A first fraction of the guard time depending on the current direction specification (p _{SZ, U} , p _{SZ, V} , p _{SZ, W} ) corresponds to the first control signal (G _HSS ) of the high-side switching element (HSS) and the remaining second fraction of the guard time to second control signal (G _LSS ) of the low-side switching element (LSS) is assigned, and the duration (t _{ON, HSS} , t _{ON, LSS} ) of the high state of the respective control signal with respect to the duty cycle command (dc _CTRL ) corresponding The duration (t _{ON, HSS} *, t _{ON, LSS} *) of the high state is shortened by twice the assigned protection time or the associated fraction of the protection time.

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