DE102010039154A1

DE102010039154A1 - Modulation of a PFC in DC mode

Info

Publication number: DE102010039154A1
Application number: DE201010039154
Authority: DE
Inventors: Peter Lampert; Dr. Mitterbacher Andre
Original assignee: Tridonic GmbH and Co KG
Current assignee: Tridonic GmbH and Co KG
Priority date: 2010-08-10
Filing date: 2010-08-10
Publication date: 2012-02-16
Also published as: EP2604097A1; WO2012020047A1; EP2604097B1

Abstract

An operating device for illuminants, in particular an electronic ballast (EVG) for gas discharge lamps, has a power factor correction circuit (PFC) for reducing harmonics in the input current consumption. On the input side, current is only consumed during predetermined time periods (tON). The predetermined time period (tON) of the current consumption is modulated when a DC voltage is present on the input side, the modulation stroke being load-dependent.

Description

The invention relates to methods for operating a control gear for lighting, such as an electronic ballast (ECG) for gas discharge lamps or LEDs. The operating device in this case has an actively clocked power factor correction circuit (PFC, Power Factor Correction) for reducing harmonics in the input current recording, which is formed, for example, in the form of a switching regulator (boost converter) with a clocked switch, wherein the switch is controlled by a control circuit becomes.
The invention further relates to a computer software program product for supporting such a method, to a control module which can support such a method by programming and / or hard wiring, as well as to an operating device for lighting means.
As said, the present invention relates to loads in the form of bulbs having PFC circuits. Such, from the DE 10128588 A1 known operating device is in 1 shown. More specifically, it is in the 1 shown device to an electronic ballast (ECG). This in 1 The ballast shown on the input side via a high-frequency filter 1 connected to a mains supply voltage U 0 . The output of the high frequency filter 1 is with a rectifier circuit 2 connected in the form of a full-bridge rectifier. That of the rectifier circuit 2 rectified AC supply voltage also represents the input voltage U i for the smoothing circuit 3 This is formed in the present example by a smoothing capacitor C1 and an inductance L1, a controllable switch in the form of a MOS field effect transistor S1 and a diode D1 having boost converter. Instead of the boost converter, other switching regulators can be used. The PFC circuit is formed by the selection of the control of the switch S1.
By a corresponding switching of the MOS field-effect transistor S1 is in a conventional manner (see, for example, also WO 99/34647 A1 ) generates an applied over the subsequently arranged storage capacitor C2 intermediate circuit voltage U Z , which the inverter 4 is supplied. The inverter 4 is formed in the present example by two further arranged in a half-bridge arrangement MOS field effect transistors S2 and S3. By high-frequency clocking these two switches S2 and S3, a high-frequency alternating voltage is generated at the center tap, which the load circuit 5 is supplied with the connected gas discharge lamp LA.
The operation of this boost converter is already known in principle and should therefore be summarized in the following only briefly. If the field effect transistor S1 is conductive, the current in the inductance L1 increases linearly. If, however, the field effect transistor S1 blocks, the current discharges into the storage capacitor C2. By selectively controlling the switch S1, the energy consumption of the boost converter and thus also the intermediate circuit voltage (bus voltage) U Z applied to the storage capacitor C2 can be influenced.
The driving of the switch S1 of the boost converter is effected by a control circuit 6 which generates corresponding switching information and to a to the control circuit 6 subsequent driver circuit 7 transmitted. This in turn converts the switching information into corresponding power control signals and controls over the line 14 the gate of the field effect transistor S1. In the same way are from the control circuit 6 and the driver circuit 7 also signals for driving the two field effect transistors S2 and S3 of the inverter 4 generated. All components of the control unit 6 for example, via a central clock 8th be synchronized, which transmits them corresponding clock signals. The control unit 6 is designed as an application-specific integrated circuit (ASIC) and accordingly takes up little space.
The calculation of the switching information for the switch S1 of the boost converter is performed by one within the control circuit 6 arranged digital control loop 9 , For this purpose, the control circuit 2 Analog / digital converters ADC 1 and ADC 2 on which the via the input line 15 supplied input voltage U i and via the input line 16 convert supplied DC link voltage U Z into digital values.
The computational block 12 serves to calculate on the basis of the current value of the intermediate circuit voltage U Z a suitable duty cycle for the switch S1. Before, however, on the basis of the computational block 12 certain duty cycle, a control signal for the switch S1 is generated, the duty cycle is, however, supplemented (extended) by an additional value of the switching time extension block 13 is determined. For this purpose, the switching time extension block 13 a memory having a table which assigns each value of the input voltage U i a certain time interval by which the on-time of the switch S1 is prolonged. The value of this additional interval becomes that of the arithmetic block 12 Calculated duty cycle as I said added and an output block 11 transmitted. This generates a corresponding switching information, that of the driver circuit 7 is fed, which then finally by a corresponding control signal via the line 14 transmitted to the switch S1.
In the most general way, the relationship between the turn-on extension and the input voltage is that the lower the input voltage U i , the greater the turn-on extension. In particular, therefore, the switch-on extension will take place in the region of the zero crossings of the sinusoidal alternating voltage which is present at the input.
In addition, it should be noted that the control circuit 6 also for operating the two switches S2 and S3 of the inverter 4 is used. For this purpose, one or more - not shown - analog / digital converter may be provided, which the load circuit 5 convert extracted operating parameters into digital values and the digital control loop 9 respectively. Shown is a rule block 10 which calculates control information for the switches S2 and S3 in response to the input signals and the driver circuit 7 transmitted. The driver circuit 7 in turn generates corresponding control signals and transmits them via the lines 17 and 18 to the gates of the two field effect transistors S2 and S3 of the inverter 4 ,
The described known from the prior art circuit is well suited for AC operation, after all, yes, the switch-on time extension is dependent on a detection of the zero crossings of the applied sinusoidal AC voltage U 0 .
Generally, however, when a DC voltage is applied to such a circuit, the on-time extension is disabled. The concern of a DC voltage, for example, in emergency mode. The known circuit thus operates in emergency mode without duty cycle extension and thus with a constant frequency. This fixed operating frequency of the power factor correction circuit (PFC) 3 thus generates interference at a substantially fixed frequency. This can cause problems with the EMC regulations that also apply to emergency lighting operation (DC operation).
WO 2006/042640 A2 Removes this problem by teaching that, even with a DC supply, the PFC, which would then actually switch with a constant switching frequency, specifically detects a frequency change (a so-called "sweep mode", also known as "wobbling", ie cyclically recurring acceleration and deceleration of a frequency) is performed.
In the practical embodiment, this is particularly such that, starting from a nominal T on value for the switch of the converter, the T on time is gradually increased, and then reduced again until it has fallen symmetrically below the nominal T on value is. This is repeated cyclically.
This means that for the AC operation the off 1 known circuit can continue to be used. Meanwhile, in DC operation, the operating frequency of the PFC is modulated so as to "dilute" the noise spectrum of the circuit to sub-bands outside the center operating frequency. This allows compliance with EMC regulations. The modulation may be a change in the modulation depth (ie extension / shortening of the switch-on time of the clocked switch) and / or the change of the switching frequency.
Of course, at low dimming levels and / or low load, the nominal value for the on time of the switch of the PFC is reduced. Thus, of course, there is only a reduced frequency swing for reducing the on- time below the nominal value. Thus, there is the risk with this method that impermissible switch-on times for the switch are achieved in the case of the symmetrical lowering of the on- time.
The present invention has therefore set itself the task of providing a method for operating a control device for lighting means, which ensures reliable operation of the lighting means.
The invention further forms the idea that the sweep mode, also known as "wobble", is adaptively adjustable depending on the load, the load being able to be connected, for example, to multi-lamp devices, to lamps of different wattages, or even to different ones Dimming levels can change.
Therefore, with reduced load and / or reduced tone time for lower dimming values, the frequency sweep is reduced so that the deviation above / below the nominal value is reduced. Thus, in particular it is prevented that impermissible (too short) switch-on times for the switch were achieved in the case of the symmetrical lowering of the sound time.
More specifically, the object is solved by the features of the independent claims.
The dependent claims further form the central idea of the invention in a particularly advantageous manner.
According to the invention, therefore, a method for operating an operating device for loads in the form of bulbs, in particular an electronic ballast (ECG) for Gas discharge lamps provided. The operating device in this case has a power factor correction circuit (PFC) for reducing harmonics in the input power consumption. In this case, the operating frequency of the power factor correction circuit is modulated at the input-side concern of a DC voltage. The modulation stroke is load-dependent.
The modulation stroke preferably depends on the wattage of the connected lamps and / or the current dimming level.

– Modulation eines Sollwerts der Ausgangsspannung,
– Beaufschlagung einer Modulation auf einen direkt oder indirekt erfassten Istwert der Ausgangsspannung, und/oder
– Modulation der Steuergrösse der Regelung.

- Modulation of a setpoint of the output voltage,
- Applying a modulation to a directly or indirectly detected actual value of the output voltage, and / or
- Modulation of the control variable of the control.

The switch-on time t ON of the switch is preferably modulated stepwise.
It may also be provided that upon reaching a predetermined lower threshold of the load, the timing of the switch of the power factor correction circuit is no longer modulated.
In the invention, it is further desired to first calculate a nominal value for the on period of the switch, accordingly setting a certain desired bus voltage at the output of the PFC and then modulating the timing of the switch of the power factor correction circuit.
It can also be provided that, when a predetermined upper threshold of the load is reached, the timing of the switch of the power factor correction circuit is modulated normally, ie without a restriction. This means that, as of a certain power, the sweep mode is carried out without restriction by the method according to the invention and accordingly the nominal amplitude of the frequency sweep is not restricted. Thus, with stronger performance, the even stronger EMC load is effectively limited, identical to that of the WO 2006/042640 A2 known methods.
The power factor correction circuit (PFC) may be in the form of a switched-mode switching regulator. In order to reduce interference, the switch can be clocked in such a way that its switch-on time duration and / or its switching frequency is modulated on the input-side presence of a DC voltage.
The modulation frequency of the power factor correction circuit (PFC) can be selected such that adjusts a corresponding ripple in the output voltage of the power factor correction circuit (PFC). In other words, the modulation of the PFC circuit is not controlled by this or a Zwischenbusregelung. Rather, the compensation of this "ripples" in the bus voltage (that is, the intermediate circuit voltage, which is output by the power factor correction circuit and applied to the storage capacitor) to keep constant the power consumption of the lamps by frequency variation of the inverter. For this purpose, the control unit can detect an operating parameter such as, for example, the lamp current and the lamp voltage in a manner known per se and vary the frequency of the inverter depending on this detection and a deviation from a desired value.
The modulation frequency of the power factor correction circuit may be selected, for example, in a range between 15 Hz and 500 Hz, preferably between 90 and 130 Hz. In the prior art, the modulation is known to be associated with the zero crossings of the AC voltage, so that a modulation frequency of 100 Hz (Europe) and 120 Hz (USA) may result. In the invention, however, the modulation frequency is freely adjustable and optimized.
Of course, if a DC voltage is applied, the modulation can no longer be triggered by the zero crossings of the input voltage. According to the invention, it can therefore be provided that the modulation of the PFC circuit takes place by means of a timer circuit, by means of which values are read out from a look-up table.
As in the prior art, these values are extension values that are added to the actual controller value T ON_controller of the control circuit . The controller value T ON_controller is the switch-on time for the switch, which was calculated by a controller to keep the output voltage of the PFC constant.
According to the invention can be automatically switched to the modulation by means of the timer circuit and the look-up table as soon as the operating device detects the concern of a DC voltage. Basically, the automatic detection of the emergency light operation (concern of a DC voltage) is already out of the EP 490329 B1 known. It gets to the local 4 , Reference numerals C25 and R21.
The power factor correction circuit (PFC) can be operated in the so-called borderline mode.
According to the invention, a computer software program product is further provided, which supports such a method when it runs on a computing device in an operating device or is implemented by hard wiring (ASIC).
Furthermore, according to the invention, a control module (microcontroller, ASIC, etc.) is also provided for a lighting apparatus which is designed to support such a method.
Finally, the invention also proposes an operating device for lighting means.
Further features, aspects and advantages of the present invention will now be made apparent from the explanation of an embodiment. In the accompanying figures show
1 one of the prior art DE 101 28 588 A1 known circuit,
2a a circuit according to the invention,
2 B another circuit according to the invention, and
3 a diagram for explaining the method according to the invention.
It is understood that according to the invention for the AC operation, the circuit of 1 can be maintained. 2a and 2 B additionally shows the components that may be necessary for operation according to the invention with DC mains voltage. For the rest, those components which bear the same reference numerals in the two figures correspond.
In order to improve the interference spectrum of the circuit in emergency mode (DC network operation), the inventive circuit as in 2a shown, a control circuit 6 on, by means of a signal 15 representing the rectified input voltage U i and a circuit 20 detects the presence of an AC or DC voltage. In this case, for example, a circuit can be used which 4 of the EP 490329 A1 is basically known. This DC detection circuit 20 controls a clock generator 8th at. This clock generator 8th replaces, so to speak, the zero crossings of the mains voltage which is no longer present at DC. The clock generator 8th thus controls the reading of the extension values for the switch-on period of the switch S1 from a look-up table.
As is generally known from the prior art, if necessary, the bus voltage U Z is measured and the control unit 6 returned (bus voltage signal 16 ) to control by varying the switching frequency of the switch S1, the bus voltage U Z to a target value U REF . The control of the bus voltage thus results in a controller value T ON_regulator for the on and off duration of the switch, which controller value T ON_regulator is also applied during DC operation with a periodically changing additional value T ON_ADD to the modulation depth and / or the switching frequency to improve the To modulate the interference spectrum.
When applying an AC voltage, this control of the bus voltage U Z by means of detection of the bus voltage 16 and through the control loop 9 Meanwhile, relatively slow compared to the modulation frequency or change the turn-on time t on of the switch S1, so that this modulation in the bus voltage U Z is not compensated and the bus voltage will have a corresponding in relation to the switching frequency of the switch S1 low-frequency ripple.
However, this ripple of the bus voltage can be compensated by the return of a parameter representing the luminous power 19 (Lamp voltage, light source current, detection of the light output via an optical sensor or the like.) As the actual value and the control of the switching frequency of the inverter 4 be compensated for maintaining the illuminant power to a predetermined setpoint. The compensation of the ripple of the bus voltage can alternatively also by a so-called "feed forward" setting the switching frequency of the inverter 4 respectively. In particular, with increasing height of the current bus voltage, the switching frequency of the inverter 4 be increased and the switching frequency can be lowered with decreasing bus voltage.
When a DC voltage is applied, the additional values T on_add read from the look-up table are stored in a memory of the ASIC 6 loaded. Then these T on_add values from the switching time extension block become 13 to the regular T on_regulator from the controller 12 added: T on = T on_add + T on_regulator
Each T on index is set for an adjustable period of time ('sweep value') and then the next index is selected from the look-up table. By changing the sweep value, the modulation frequency can be adjusted.
In the practical embodiment, this in particular looks like that starting from a nominal T on value for the switch of the converter is incremented incrementally the on time, and then reduced again until it has dropped symmetrically below the nominal T on value. This is repeated cyclically. The modulation of the T on value ensures that the T off value is also modulated, since the PFC is operated in borderline mode, ie switching on at a throttle current = 0. Thus, the PFC frequency is modulated with a frequency sweep, which is proportional to the T on modulation.
It should be emphasized that first the control loop, which is to set a certain setpoint bus voltage at the output of the PFC, calculates a nominal value for the switch-on time duration, and then this nominal value is temporally changed in time. The temporal change does not result as an effect of the control algorithm, but is only applied after calculation of the nominal value. Thus, there is also a cyclic frequency change or T on -teitveränderung even if supply voltage and load are constant.
In order to prevent inadmissible switch-on times with reduced load, the "sweep mode" is thus set adaptively according to the invention, wherein the load can be changed, for example, in multi-lamp devices to which lamps of different wattages can be connected, or also at different dimming levels can. In particular, the frequency range for the "sweep mode" of the PFC is thus adjusted to be load-dependent adaptive. 2a shows, for example, another, a lamp information reproducing parameters 22 , which provides information about the connected load to the output block 11 supplies. This information can be, for example, data about the connected load (such as via detection of the lamp type or wattage and / or their nominal power).
2 B shows an interface 20 , which via a control line 21 receives a preset for the desired dimming level. the interface 20 can also be in the control unit 6 be integrated. The default of the dimming level can be present as a digital or analog control signal. This preset dimming level (dimming value) is set via the parameter 23 the starting block 11 fed. The parameter 23 Thus contains information about the load, in particular information about the deviation from the nominal load. This output block 11 With this information, as described above, the so-called "sweep mode" can be adaptively adjusted depending on the load. In 2 B not shown is the influence of the interface on the control of the operating device to change the brightness. For example, this can be done in a known manner by changing the frequency of the inverter or by changing the turn-on of the switch of the inverter.
3 shows in a time-time diagram four examples (from left to right) of sweep mode cycles (each with nominal, rising, falling, and rising step changes in switch on duration and a nominal amplitude of 200 ns) different loads, in which the three right are limited due to a low load by the inventive method in amplitude. The X-axis represents the basic time course without scaling, while the Y-axis represents the time duration of the switch-on time of the switch and thus corresponds to the level of the output voltage of the PFC. Thus, it will be understood that the left example corresponds to a higher load, higher power, or higher dimming level than the others.
Ultimately, therefore, the frequency deviation depends on the nominal value for the on- time. The nominal value results from the control algorithm and corresponds to 300, 200, 100 and 250 ns in the four examples.
Of course, at low dimming levels and / or low load, the nominal value for the on time of the switch of the PFC is reduced, as shown in the three right hand examples. Therefore, with reduced load and / or reduced T on time for lower dimming values, the frequency deviation is reduced so that the deviation above / below the nominal value is reduced. The nominal amplitude of the sweep mode, in this case 200 ns, which results from the frequency sweep, is therefore limited by the method according to the invention depending on the load and thus on the nominal switch-on duration of the switch. Thus, in particular it is prevented that impermissible (too short) turn-on times for the switch were achieved in the case of the symmetrical lowering of the on- time.
The second and fourth examples show that the modulation by the "sweep mode" partially prevented, that can be "cut off" when the duty cycle drops below the critical value. In a stepwise change in the duty cycle, as shown in the examples, it is possible that individual stages are "cut off". The levels that would thus be in the impermissible range are prevented and instead the turn-on time period is set to the lowest permissible value. Thus, in the second example, the two stages prescribed by "sweep mode" are cut off or prevented with T ON = 50 ns and 0 ns, in which the duty cycle remains at the still permitted value T ON = 100 ns. As soon as the duty cycle prescribed by "sweep mode" rises again in the permitted range, ie above 100 ns, the actual duty cycle is set again accordingly. So that the nominal value is not distorted, the upper peaks of the modulation are adjusted according to the lower peaks, so cut off, so that the average value is not distorted.
The determination at which stage a cycle of the "Sweep Mode" should be cut off, can be made at the beginning of the cycle of the "Sweep Mode" or as soon as the current nominal value of the duty cycle has been determined.
At particularly low load, as shown in the third example, even the frequency deviation can be completely prevented. However, because of the correspondingly reduced power and the EMC load is low, such a limitation does not constitute a significant limitation in terms of EMC compatibility. At very low Dimmwerten and thus very low T on time (nominal value) so the stroke can be reduced to zero, ie at certain dimming levels or low loads, the "sweep mode" is canceled.
As already mentioned, in the case of the invention there is also a cyclical frequency change or on-time change if the supply voltage and the load are constant. Just then, the sweep mode with unrestricted modulation due to the higher power has to be chosen to reduce the EMC load of the PFC. This is represented by the left (ie first) example.
It can be specified in the control unit of the PFCs a minimum value T on-min , this is in 3 at 100 ns. Thus, the control unit can determine the allowable frequency deviation even without knowledge of any existing dimming value specifications (dimming level) or loads due to the value determined by the control algorithm for T on and the resulting difference to T on-min .
However, it is also conceivable that if the nominal value of T on reaches a predetermined minimum value, for example 250 ns, the "sweep mode" is suspended. This would mean that only in the first example would an unchanged "sweep mode" be applied, while the "sweep mode" would be exposed to the others.
Basically, the "sweep mode" can be achieved by a modulation of the feedback signal (actual value signal for the output voltage), so that then due to this 'falsification' the PFC controller will undertake a modulation of the T on time with the attempt to regulate it varying appearing output voltage constant. If the chosen solution is chosen, namely a calculation of the T on -nominal value with subsequent modulation, it must be ensured that the modulation is so fast that the controller can not compensate. Thus, in fact, a constant tone nominal value with subsequent fast modulation can be assumed.
Alternatively, of course, the setpoint specification for the output voltage can be modulated. When modulating the setpoint specification or the actual value specification, it must be ensured that this is done in a frequency range that the control algorithm can compensate.
It should be noted that the method according to the invention for use in operating devices for lighting means in addition to the electronic ballasts (ECG) for gas discharge lamps described in the examples also in control gear for inorganic and organic light-emitting diodes (LED) is applicable.
QUOTES INCLUDE IN THE DESCRIPTION
This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.
Cited patent literature

DE 10128588 A1 [0003, 0040]
WO 99/34647 A1 [0004]
WO 2006/042640 A2 [0013, 0028]
EP 490329 B1 [0034]
EP 490329 A1 [0045]

Claims

A method of operating an operating device for loads in the form of light bulbs, in particular an electronic ballast (EVG) for gas discharge lamps, wherein the operating device comprises a switch means active clocked power factor correction circuit (PFC) for reducing harmonics in the input power receiving, - the timing of the switch of the power factor correction circuit is modulated at the input side of a DC voltage between two limit values, so that the limits define a modulation stroke, and - The modulation stroke is adjusted by changing the lower and / or the upper limit load dependent.
The method of claim 1, wherein the modulation of the wattage of the connected lamps and / or the current dimming level depends.
Method according to claim 1 or 2, wherein the output voltage of the PFC is controlled and the modulation of the frequency is performed by one or more of the following steps: - Modulation of a setpoint of the output voltage, - Applying a modulation to a directly or indirectly detected actual value of the output voltage, and / or - Modulation of the control variable of the control.
Method according to one of the preceding claims, wherein the switch-on time t ON of the switch is preferably modulated stepwise.
Method according to one of the preceding claims, characterized in that on reaching a predetermined lower threshold of the load, the timing of the switch of the power factor correction circuit is no longer modulated.
Method according to one of the preceding claims, characterized in that first a nominal value for the switch-on period of the switch is calculated, and accordingly a certain desired bus voltage is set at the output of the PFC, and then the modulation of the timing of the switch of the power factor correction circuit.
Method according to one of the preceding claims, characterized in that upon reaching a predetermined upper threshold of the load, the timing of the switch of the power factor correction circuit normal, d. H. is modulated without a restriction.
Method according to one of the preceding claims, characterized in that the modulation frequency of the power factor correction circuit (PFC) is selected such that adjusts an unregulated ripple in the output voltage of the power factor correction circuit (PFC).
A method according to claim 8, characterized in that the ripple of the output voltage for constant maintenance of the power of the lighting means is compensated in a following lighting control circuit.
A method according to claim 9, characterized in that the lighting means control circuit compensates for the ripple of the supplied output voltage by varying the operating frequency of the lighting means.
Method according to one of the preceding claims, characterized in that the modulation frequency of the power factor correction circuit (PFC) in a range between 50 Hz and 500 Hz, preferably 90 Hz to 130 Hz is selected.
Method according to one of the preceding claims, characterized in that the modulation of the power factor correction circuit (PFC) takes place by means of a timer circuit, by means of which values are read out of a look-up table.
A method according to claim 10, characterized in that automatically switched to the modulation by means of timer circuit and look-up table as soon as the concern of a DC voltage is detected by the operating device.
Method according to one of the preceding claims, characterized in that the power factor correction circuit (PFC) is operated in the so-called limit mode.
Computer software program product, characterized in that it supports a method according to one of the preceding claims, when it runs on a computing device in an operating device or is implemented by hardwiring.
Control module for a lamp operating device, in particular integrated circuit such as. ASIC, microcontroller or hybrid version thereof, characterized in that it is designed to support a method according to one of claims 1 to 14.
Operating device for loads in the form of bulbs, in particular electronic ballast (ECG) for gas discharge lamps, wherein the operating device, a power factor correction circuit (PFC) for reducing input signal current harmonic distortion, characterized in that the operating frequency of the power factor correction circuit is modulated at the input side of a DC voltage between two thresholds of the clock, such that the thresholds define a modulation swing, and - the modulation swing Change in the lower and / or upper limit is set load-dependent.
Operating device according to one of Claims 17, characterized in that the modulation frequency of the power factor correction circuit (PFC) is selected such that a corresponding ripple occurs in the output voltage of the power factor correction circuit (PFC).
Operating device according to claim 18, characterized in that the ripple afflicted output voltage is supplied to a lighting control circuit which varies the operating frequency of the lighting means for keeping constant the power of the lighting means.
Operating device according to one of claims 17 to 19, characterized in that the modulation frequency of the power factor correction circuit (PFC) is selected in a range between 50 Hz and 500 Hz, preferably 90 Hz to 130 Hz.
Operating device according to one of Claims 17 to 20, characterized in that the modulation of the power factor correction circuit (PFC) takes place by means of a timer circuit, by means of which values are read out of a look-up table.
Operating device according to claim 20, characterized in that it is designed for automatically activating the modulation by means of timer circuit and look-up table when a DC voltage is applied.
Operating device according to one of Claims 17 to 22, characterized in that the power factor correction circuit (PFC) is designed for limit mode operation.