DE102008014111A1 - Test structures for checking the positioning accuracy in manufacturing processes of microelectronic circuits - Google Patents

Abstract

Test structures for checking the positioning accuracy in the process steps of the production of the metallization levels of integrated circuits are given, which include an electrical short-circuit measurement which is easy to perform and can be reliably assessed (good / bad statement). Several test structures of similar construction with modified detail dimensions allow the positioning accuracy to be determined in stages.

Description

The The invention relates to the verification of Positioning accuracy in the overlap of assigned Circuit structures of integrated circuits through test structures for the process steps of the production of metallization levels in conjunction with simple electrical measurements.

The production of integrated circuits (IC's) consists of a variety of individual process steps such. As the deposition or generation of layers of diverse materials and their subsequent structuring by means of different etching processes or the doping of defined areas on the semiconductor wafer. As a masking layer for the etching and doping processes, a photoresist layer is used in many cases, into which the structures are transferred from a mask by optical exposure. A criterion for the functionality of the finished circuit is the position of the individual structured elements of the Schakltkreises each other, or their maximum tolerable deviation. Since the process of circuit fabrication consists of a plurality of manufacturing steps, in which the exact position assignment of the respective circuit details is realized in each case by means of a photomask step, the defined position of the corresponding photoresist masks is of crucial importance. Therefore, there are also a variety of requirements for the positioning of the individual photomasks each other. This is especially true for the metallization processes that are at the end of a chain of individual processes, with a considerable manufacturing effort has already been invested in the semiconductor wafers. As a positioning problem is for example called a sequence consisting of contact; metallization 1 (Metal 1 ); Transition from the metallization level (metal 1 ) to the metallization level 2 (Metal 2 ) in the form of a metal-filled opening of an insulating intermediate layer (contact junction: via). Here must be the metal 1 cover the contact hole. The contact junction / via must be inside the metal 1 lie and metal 2 must in turn cover the contact transition. To ensure this, certain overlaps are defined in the design rules, e.g. For example, the metal needs 1 occupy a larger area than the contact hole. The larger this supernatant is, the less critical is the coverage accuracy to be maintained. However, this has the disadvantage that this makes such individual detailed structures of the circuit larger, which makes the entire circuit larger and thus more expensive. By a precisely maintained positioning so the geometric size of the detailed structures of a circuit can be reduced. Thus, the entire circuit structure is smaller and consequently the whole circuit, which has a positive effect on the manufacturing cost. The circuit is thereby cheaper. From this it becomes apparent that the verification of the positioning accuracy, in particular for metallization processes, is of enormous importance.

In US 5,998,226 describes a method and a test structure in which the position of a stacked row of vias can be assessed optically to an underlying step-shaped metal conductive pathway. However, this structure can not be judged by electrical measurement for sufficient coverage accuracy.

In US 6,242,757 An electrical evaluation method is described in which a quadratic reference structure on all four sides is overlapped by a part of a measuring plate. The overlapping part of the reference structure and the measuring plate form a capacitor structure. Such a capacitor structure is located on all four sides of the reference structure and with exact positioning, all capacitances are equal. In the case of inaccurate positioning, the areas of the capacitor structures become larger or smaller. From the electrical measurement of the four capacitances and the comparison of the measured values, the positioning accuracy can be determined.

adversely It is that the test structures should be very small. In order to the capacities become very small and thus very difficult and inaccurate to measure.

In US 5,699,282 a structure is described which consists of a first, common long interconnect. On each side a via (transition hole to another metallization level) is attached and each of the vias is in turn electrically connected by its own second interconnect. The distance between the two vias is slightly less than the width of the first common interconnect. In the case of exact positioning, the electrical resistance between the left, second interconnect, the left via and the first common interconnect is equal to the resistance formed by the right, second interconnect, the right via and the first common interconnect. In the case of incorrect positioning, the electrical resistances become unequal and the positioning accuracy can be calculated from the deviation of the electrical resistances. Another disadvantage is the small size of the electrical contact surfaces. The differences in the resistances are very small and thus it is very difficult and expensive to perform an exact measurement.

Also in US 6,383,827 . US 6,380,554 . US 5,770,995 and US 6,393,714 contact resistances are evaluated which, if not exactly positioned, become unequal and thus give information about the positioning accuracy. A disadvantage of the up The method described here is that these structures described in the prior art provide only one result with respect to the geometric position of two planes to each other, ie, as a result, there is a certain length, z. In micrometers or nanometers. These structures do not provide information about the functionality of the structure to be measured. For example, it is determined that the via has some deviation from the underlying metal, and a maximum value to be met must be defined. In this approach, in the calculation of the maximum permissible mispositioning z. B. a systematic edge shift of the affected structures or the edge shape are taken into account.

It is not metrologically determined with these structures whether the via far enough outside the underlying metal 1 The structure is that, for example, the etch process in the via plane (which is normally stopped on the underlying metal) is etched deeper than desired, and thus harmful short circuits between metal and underlying conductive structures can be created. A further disadvantage is that the measurement result is determined in the form of an analogous result (eg different high resistance or different sized capacitance).

purpose The invention is to provide test structures that in connection with an electrical measuring method a clear, simple and quick statement about the accuracy of the positioning the photolithographic masks in the process steps of the production metallization levels of IC's during wafer production processes.

Of the Invention is based on the object with the existing in the process flow Process sequence of the production of metallization levels to design a test structure to give an indication of Positioning accuracy in conjunction with a simple electrical Measurement directly, d. H. without special evaluations, about allows a statement in the form of a yes / no result and above the functionality of the structures under consideration.

Solved This object is achieved with the specified in claims 1 to 6 Features.

The objects of claims 1 to 6 have the advantages that it is possible to check the positioning accuracy with these test structures by a simple electrically measurable digital information. It is not necessary to evaluate the size of a measured electrical resistance or a capacitance, but the result is directly due to the information short circuit or no short circuit between the electrically conductive background layer ( 1 ) and the electrically conductive connection layer ( 6 ) is displayed. These are easy-to-collect, easy-to-process, and easy-to-interpret signals, each obtained with the test structures of a small footprint. Another advantage is that not only the geometric positioning accuracy is checked, but their electrical effect, ie it results in their effect on the functionality of the relevant structure of the circuit.

Of the Objects of claims 3 to 6 offer about it In addition, the advantage that possible edge shifts be determined when positioning by direction and amount can, in the semiconductor wafer process in the corresponding detail structures of the circuit in the for the production of the metal layers relevant work processes can occur.

The Objects of claims 2, 4 and 6 further have the advantage that the positioning accuracy graduated quantitatively can be determined.

The Invention will now be based on an embodiment below With the help of the drawing explained. Show it

1 2 shows the cross section of a test structure according to the invention for checking the positioning accuracy, in the ideal case of exact positioning,

2 schematically the top view of the test structure according to 1 .

3 2 shows schematically the cross section of a test structure according to the invention for checking the positioning accuracy in the limiting case of still tolerable mispositioning;

4 schematically the top view of the test structure according to 3 .

5 2 shows schematically the cross section of a test structure according to the invention for checking the positioning accuracy in the case of an insufficient, ie incorrect positioning,

6 schematically the top view of the test structure according to 5 .

7 2 shows schematically the cross section of an embodiment of the test structure according to the invention for checking the positioning accuracy with which a statement about the direction of the incorrect positioning can be obtained,

8th schematically the top view of the test structure according to 7 .

9 schematically the cross section of the detail of an embodiment of the test structure according to the invention for checking the positioning accuracy, with which a statement on the direction of the mispositioning and a statement on the size of the mispositioning is achieved, and

10 schematically the top view of a detail of an embodiment of the test structure for determining the size and direction of a mispositioning based on the representation in 9 ,

In 1 is the cross-section of a test structure for checking the positioning accuracy of contact / via ( 4 ) with respect to an electrically conductive layer to be contacted ( 3 ). Below the electrically conductive layer ( 3 ) is an electrically conductive background layer ( 1 ) through a first electrically insulating layer ( 2 ) of the electrically conductive layer to be contacted ( 3 ) is electrically isolated. The contacts / vias ( 4 ) are formed by the electrically conductive connection layer ( 6 ) electrically connected. The top view in 2 shows that with exact positioning the contacts / vias ( 4 ) symmetrically on the electrically conductive layer to be contacted ( 3 ) are located. When applying a voltage between the electrically conductive background layer ( 1 ) and the electrically conductive connection layer ( 6 ), due to the first electrically insulating layer ( 2 ), a very high resistance can be measured. This is also the case with a still acceptable mispositioning, as in 3 and 4 is shown. The contacts / vias ( 4 ) sit asymmetrically but still completely on the electrically conductive layer to be contacted ( 3 ).

The 5 and 6 show a situation with an unacceptable misalignment. The contacts / vias ( 4 ) no longer sit completely on the electrically conductive layer to be contacted ( 3 ). When etching the holes for the contacts / vias ( 4 ) in the second electrically insulating layer ( 5 ) is therefore the lower lying first electrically insulating layer ( 2 ), whereby an electrically conductive connection of the electrically conductive background layer ( 1 ) he follows. When applying a voltage between the electrically conductive background layer ( 1 ) and the electrically conductive connection layer ( 6 ), a very low resistance (short circuit) will now be measured due to the resulting conductive connection.

So Only two measurement results are possible: short circuit or no short circuit that matches "bad" and "good".

Another embodiment of the test structure is in the 7 and 8th shown. In the division of the conductive background layer ( 1 ) into four electrically isolated, square or rectangular electrically conductive background layers ( 70 . 71 . 72 . 73 ), each of the contacts / vias ( 4 ), the edges of the contacts / vias ( 4 ) have parallel edges and are electrically isolated from each other, an indication of the direction of the mispositioning can be obtained in the case of incorrect positioning, depending on which faces are affected by the short circuit.

The same possibilities arise when, instead of the electrically conductive connection layer ( 6 ) four correspondingly positioned partial surfaces are present (not shown).

A further embodiment variant consists in that a plurality of identically constructed test structures each having different distances of the edges of the contacts / vias (FIG. 4 ) from the edges of the layer to be contacted ( 3 ) are present in the x and the perpendicular y-direction, as in the 9 and 10 is shown. Based on the known distance measurements, the size and direction of the positioning accuracy can be determined from the position and number of short circuits. This result can also be obtained by the simple measurement signals in digital form.

1

electrical conductive background layer

2

first electrically insulating layer

3

to contacting electrically conductive layer

4

Contact transition from one to the other electrically conductive layer: Via

5

second electrically insulating layer

6

electrical conductive connection layer

70 71, 72, 73

Electrically isolated base layers electrically insulated from one another analogously to the electrically conductive background layer ( 1 )

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• US 5998226 [0003]
• - US 6242757 [0004]
• US 5699282 [0006]
• - US 6383827 [0007]
• - US 6380554 [0007]
• US 5770995 [0007]
• - US 6393714 [0007]

Claims (6)

Test structure for checking the positioning accuracy of the metallization process steps in the production of microelectronic circuits, consisting of a geometrically rectilinearly limited electrically conductive background layer ( 1 ) of square or rectangular shape, a first electrically insulating layer ( 2 ), an overlying lying to be electrically conductive layer ( 3 ) with respect to the predetermined positioning accuracy and size of four square contact junctions / vias ( 4 ) matched, geometrically limited surface area in square shape, a second electrically insulating layer located above ( 5 ) with four square contact junctions / vias ( 4 ), which are equidistant and symmetrical about the center of the electrically conductive layer to be contacted ( 3 ), an overlying electrically conductive connection layer ( 6 ), wherein the edges of the electrically conductive background layer ( 1 ), the electrically conductive layer to be contacted ( 3 ), the square contact transitions / vias ( 4 ) and the electrically conductive connection layer ( 6 ) run parallel. Test structure for checking the positioning accuracy of the metallization processes in the production of microelectronic circuits, consisting of several similar test structures, each consisting of a geometrically rectilinearly limited electrically conductive background layer ( 1 ) of square or rectangular shape, a first electrically insulating layer ( 2 ), an overlying lying to be electrically conductive layer ( 3 ) with respect to the predetermined positioning accuracy and size of four square contact junctions / vias ( 4 ) matched, geometrically limited surface area in square shape, a second electrically insulating layer located above ( 5 ) with four square contact junctions / vias ( 4 ), which are equidistant and symmetrical about the center of the electrically conductive layer to be contacted ( 3 ), an overlying electrically conductive connection layer ( 6 ), wherein the edges of the electrically conductive background layer ( 1 ), the electrically conductive layer to be contacted ( 3 ), the square contact transitions / vias ( 4 ) and the electrically conductive connection layer ( 6 ) run parallel, wherein the identically constructed test structures differ in that the distances between the edges of the square contact junctions / vias ( 4 ) and the electrically conductive layer to be contacted ( 3 ) in one or in two mutually perpendicular directions x and y systematically change. Test structure for checking the positioning accuracy of the metallization process steps in the production of microelectronic circuits, consisting of four mutually insulated, electrically conductive background layers ( 70 . 71 . 72 . 73 ), which have a square shape and their size and location on the size and location of four square contact junctions / vias ( 4 ), a first electrically insulating layer ( 2 ), an overlying lying to be electrically conductive layer ( 3 ), with respect to the given positioning accuracy and size of four square contact transitions / vias (FIG. 4 ) matched, geometrically limited surface area in square shape, a second electrically insulating layer located above ( 5 ) with four square contact junctions / vias ( 4 ), which are equidistant and symmetrical about the center of the electrically conductive layer to be contacted ( 3 ), an overlying electrically conductive connection layer ( 6 ), wherein the edges of the electrically conductive background layers ( 70 . 71 . 72 . 73 ), the electrically conductive layer to be contacted ( 3 ), the square contact transitions / vias ( 4 ) and the electrically conductive connection layer ( 6 ) run parallel. Test structure for checking the positioning accuracy of the metallization process steps in the production of microelectronic circuits, consisting of a plurality of identically constructed test structures, each consisting of four mutually insulated, electrically conductive background layers ( 70 . 71 . 72 . 73 ), which have a square shape and their size and location on the size and position of four square contact junctions / vias ( 4 ), a first electrically insulating layer ( 2 ), an overlying lying to be electrically conductive layer ( 3 ) with respect to the predetermined positioning accuracy and size of the four square contact transitions / vias (FIG. 4 ), geometrically inclined surface extent in a square shape, a second electrically insulating layer ( 5 ) with four square contact junctions / vias ( 4 ) which are equidistant from each other symmetrically to the center of the electrically conductive layer to be contacted ( 3 ), an overlying electrically conductive connection layer ( 6 ), wherein the edges of the electrically conductive background layers ( 70 . 71 . 72 . 73 ), the electrically conductive layer to be contacted ( 3 ), the square contact transitions / vias ( 4 ) and the electrically conductive connection layer ( 6 ) run parallel, wherein the identically constructed test structures differ in that the distances between the edges of the square contact junctions / vias ( 4 ) and the electrically conductive layer to be contacted ( 3 ) in one or in two mutually perpendicular directions x and y systematically change. Test structure for checking the positioning accuracy of the metallization process steps in the production of microelectronic circuits, consisting of a geometrically limited electrically conductive background layer ( 1 ) of square or rectangular shape, a first electrically insulating layer ( 2 ), an overlying lying to be electrically conductive layer ( 3 ) with respect to the predetermined positioning accuracy and the size of four square contact transitions / vias ( 4 ) matched, geometrically limited surface area in square shape, a second electrically insulating layer located above ( 5 ) with the four square contact junctions / vias ( 4 ), which are equidistant and symmetrical about the center of the electrically conductive layer to be contacted ( 3 ), four overlying isolated, preferably square electrically conductive connection layers, wherein the position and size of the four connection layers with respect to the predetermined positioning accuracy on the position and size of the four square contact junctions / vias ( 4 ) and the edges of the four electrically conductive connection layers, the four square contact junctions / vias (FIG. 4 ) of the electrically conductive layer to be contacted ( 3 ), and the electrically conductive background layer ( 1 ) run parallel. Test structure for checking the positioning accuracy of the metallization process steps in the production of microelectronic circuits, consisting of a plurality of similarly constructed test structures, each consisting of a geometrically limited electrically conductive background layer ( 1 ) of square or rectangular shape, a first electrically insulating layer ( 2 ), an overlying lying to be electrically conductive layer ( 3 ), with respect to the given positioning accuracy and size of four square contact transitions / vias (FIG. 4 ) matched, geometrically limited surface area in square shape, a second electrically insulating layer located above ( 5 ) with the four square contact junctions / vias ( 4 ), which are equidistant and symmetrical about the center of the electrically conductive layer to be contacted ( 3 ), four overlying isolated, preferably square, electrically conductive connection layers, wherein the position and size of the four electrically conductive connection layers with respect to the predetermined positioning accuracy on the location and size of the four square contact junctions / vias ( 4 ) and the edges of the four electrically conductive connection layers, the four square contact junctions / vias (FIG. 4 ), the electrically conductive layer to be contacted ( 3 ), and the electrically conductive background layer ( 1 ) run parallel, wherein the identically constructed test structures differ in that the distances between the edges of the square contact junctions / vias ( 4 ) and the electrically conductive layer to be contacted ( 3 ) in one or in two mutually perpendicular directions x and y systematically change.