DE102008013900A1 - Method for producing a multiplicity of optoelectronic semiconductor chips and optoelectronic semiconductor chip - Google Patents

Method for producing a multiplicity of optoelectronic semiconductor chips and optoelectronic semiconductor chip

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Publication number
DE102008013900A1
DE102008013900A1 DE102008013900A DE102008013900A DE102008013900A1 DE 102008013900 A1 DE102008013900 A1 DE 102008013900A1 DE 102008013900 A DE102008013900 A DE 102008013900A DE 102008013900 A DE102008013900 A DE 102008013900A DE 102008013900 A1 DE102008013900 A1 DE 102008013900A1
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Germany
Prior art keywords
layer
doped layer
wafer
doped
electrically conductive
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DE102008013900A
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German (de)
Inventor
Adrian Stefan Dr. Avramescu
Karl Dr. Engl
Martin Dr. Straßburg
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Osram Opto Semiconductors GmbH
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Osram Opto Semiconductors GmbH
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Priority to DE102008013900A priority Critical patent/DE102008013900A1/en
Publication of DE102008013900A1 publication Critical patent/DE102008013900A1/en
Withdrawn legal-status Critical Current

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0756Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus peculiar to the manufacture or treatment of these devices or of parts thereof
    • H01L31/1892Processes or apparatus peculiar to the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus peculiar to the manufacture or treatment of these devices or of parts thereof
    • H01L31/186Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864Annealing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0095Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H01L33/325Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0201Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0206Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0215Bonding to the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0206Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0217Removal of the substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/52Manufacturing of products or systems for producing renewable energy
    • Y02P70/521Photovoltaic generators

Abstract

The invention relates to a method for producing a multiplicity of optoelectronic semiconductor chips with buried p-side, comprising the following method steps: a) producing a wafer (1, 2, 3) having a semiconductor layer sequence (100, 200, 300) which is an n doped layer (12, 22, 32), an active layer (13, 23, 33) and a p-doped layer (14, 24, 34), wherein the actir p-doped layer is arranged and the p-doped B) electrically activating the acceptors in the exposed p-doped layer (14, 24, 34) by a thermal activation method, c) covering the p-doped layer (14, 24, 34) and d) dicing the wafer (1, 2, 3) in a plurality of optoelectronic semiconductor chips.

Description

  • It be a method of producing a variety of optoelectronic Semiconductor chips and an optoelectronic semiconductor chip indicated.
  • The publication WO 2007/012327 describes an optoelectronic semiconductor chip.
  • A The problem to be solved is to provide a method for the production indicate a multiplicity of optoelectronic semiconductor chips, which have improved electrical properties.
  • At least An embodiment of the method relates to the method the production of a plurality of optoelectronic semiconductor chips with buried p-side.
  • at the optoelectronic semiconductor chips are, for example by LED chips such as laser diode chips or LED chips. However, it can also be in the optoelectronic semiconductor chips to act detector chips such as photodiode chips. The means, during operation of the optoelectronic semiconductor chips Electromagnetic radiation is generated in their active layer, amplified or detected.
  • "Buried p-side "means that the p-side of the of the method produced optoelectronic semiconductor chip not exposed, but that more semiconductor layers or a Carrier of the optoelectronic semiconductor chip of the p-side follow the semiconductor chip. This means further that on one p-doped layer of the optoelectronic semiconductor chip further Layers are applied, which are not for example is a mere pass layer. On the p side of the Semiconductor chips are thus further semiconductor layers or a carrier arranged, with a stable mechanical connection of the other Elements to the p-side is important.
  • At least An embodiment of the method comprises the method a first method step, in which a wafer with a semiconductor layer sequence which is an n-doped layer, an active layer and a p-doped layer. The layers are preferably epitaxially grown layers, each several monolayers of an epitaxially deposited material. Preferably, the layers are in a III-nitride semiconductor system educated. That is, the layers contain compounds nitrogen with, for example, aluminum, gallium and / or indium, which n- or p-doped with donors or acceptors could be.
  • The active layer is between the n-doped layer and the arranged p-doped layer. Form N- and p-doped layers preferably a cladding layer for the active layer and then stand out against the active layer increased band gap. The p-doped layer is exposed. "Uncovered" means that the p-doped layer has a main surface, at which of the p-doped layer no further material, that is no further semiconductor layer, no support and no growth substrate follows. The main surface is, for example, by formed an outer surface of the p-doped layer, which is perpendicular to the growth direction of the p-doped layer. In other words, the p-doped layer is freely accessible and, for example, a carrier or a growth substrate opposite to the semiconductor layer sequence arranged.
  • At least a further embodiment of the method described here followed by a further process step in which the acceptors in the exposed p-doped layer by a thermal activation method be electrically activated. Preferably, this is an exclusively thermal activation process such as annealing, rapid thermal annealing (RTA), heating in a tube furnace. The activation temperature is thereby preferably between 300 ° C and 950 ° C.
  • At least an embodiment of the method for producing a Variety of optoelectronic semiconductor chips is followed by a further process step, in which the p-doped layer is covered. "Covering" means in that the p-doped layer is provided with an adhesion-promoting layer and / or an electrically conductive layer and / or a carrier and / or a semiconductor layer sequence is covered. After covering of the p-doped layer, the wafer has a semiconductor layer sequence with it buried p-side up.
  • At least an embodiment of the method is subsequently the wafer thus produced into a plurality of optoelectronic Isolated semiconductor chips. The singulation can for example by Sawing, breaking or laser cutting done.
  • In accordance with at least one embodiment of the method described here for producing a plurality of p-side buried optoelectronic semiconductor chips, the method comprises the following method steps:
    • a) producing a wafer having a semiconductor layer sequence, which comprises an n-doped layer, an active layer and a p-doped layer, wherein the active layer between the n-doped layer and the p-doped layer ange is assigned and the p-doped layer is exposed,
    • b) electrically activating the acceptors in the exposed p-doped layer by a thermal activation method,
    • c) covering the p-doped layer, and
    • d) separating the wafer into a plurality of optoelectronic semiconductor chips.
  • The electrical activation preferably involves heat input via a period of the order of several Minutes. The dopant - an acceptor - for The p-doped layer, usually can not be in a pure Form are introduced into the semiconductor. Instead, the dopant is located in a complex with at least one other substance. This another substance often acts as a donor for the semiconductor material, which compensates the acceptor in its electrical effect. The activation step is suitable, the electrical effect at least to produce a portion of the acceptors within the semiconductor material permanently. This means that the electrical activation causes the p-conductivity increased in the p-doped layer. For example, it acts it is the dopant for the p-doped layer around magnesium. The magnesium is for example in a complex with Hydrogen incorporated into the semiconductor material of the p-doped layer. Through the activation step, the electrical effect of at least one Part of the magnesium as a p-type dopant produced.
  • The The method described here is based inter alia on the knowledge that that it is possible by exposing the p-doped layer is, the p-dopant in the p-doped layer already at the wafer level, that is, before separating the wafer into individual ones optoelectronic semiconductor chips, to activate. this makes possible a particularly simple and therefore inexpensive activation of the p-type dopant.
  • At least an embodiment of the method for producing a Variety of optoelectronic semiconductor chips with buried p-side at least two are produced according to the method Wafer in a further process step above the other stacked such that a wafer stack with at least two active Layers arise.
  • For example is a first and a second wafer according to the prepared above and covering the p-doped layer first of the first wafer, a radiation-transmissive, electrically conductive layer on the activated, p-doped Layer of the first wafer applied. In the radiation-transmissive, electrically conductive layer is, for example a layer of a TCO (Transparent Conductive Oxide) material. For example, contains or consists of radiation-transmissive, electrically conductive layer of at least one of the following Materials: ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO.
  • Further is on the n-doped layer of the second wafer another radiation-transmissive, electrically conductive Layer applied. In the case of the further radiation-transmissive, electrically conductive layer is, for example around a layer of a TCO (Transparent Conductive Oxide) material. For example, contains or is the other radiation-transmissive, electrically conductive layer of at least one of the following Materials: ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO. The other radiation-transmissive, electrically conductive Layer and the radiation-transmissive, electrically conductive Layer can be constructed identically.
  • Subsequently is the second wafer on its n-side by means of the two radiation-transmissive, electrically conductive layers connected to the first wafer. That is, the radiation-transmissive, electric conductive layers are used in addition to their property as Contact layers for establishing an electrical contact between first and second wafers also as adhesion layers between first and second wafers. The radiation-transmissive, electrically conductive layers impart a mechanical Adhesion between the wafers.
  • Of Further, it is possible besides a second wafer as well still third, fourth and also further wafers in the described Way stack on top of each other, making a wafer composite arises with more than two active layers. The wafers are there all prepared by the method described above.
  • The active layers of the stacked wafers can differ in terms of their composition, so that of different active layers electromagnetic Generates or detects radiation of different wavelengths becomes.
  • In accordance with at least one embodiment of the method, when the p-doped layer of the second wafer is covered, a carrier is first applied to the p-doped layer, and then the n-doped layer of the second wafer is exposed. In this case, the n-doped layer is applied, for example, to a growth substrate. The n-doped layer follows the active layer on its side facing away from the growth substrate, and the active layer of the second wafer follows the p-doped layer. After electrical activation the acceptors in the exposed p-doped layer are supported on them and the growth substrate is released from the n-doped layer so that the n-doped layer of the second wafer is exposed. With the n-doped layer thus exposed, the second wafer can then be applied to the radiation-transmissive, electrically conductive layer and thus electrically and mechanically connected to the first wafer. In this case, a further radiation-transmissive, electrically conductive layer is preferably located on the n-doped layer of the second wafer.
  • At least An embodiment of the method becomes the second wafer with the carrier by means of a planarized layer Connected to silicon dioxide. That is, on the p-doped Layer of the second wafer, a layer of silicon dioxide is applied. This layer is planarized so that it is flat and essentially Plan-parallel to the layers of the semiconductor layer sequence of second wafer passes. "Essentially plan-parallel" means that the course up to production-related fluctuations plan-parallel is. The layer of silicon dioxide serves as a bonding layer, which mechanically connects the second wafer to the carrier.
  • At least An embodiment of the method is used in the manufacture of the wafer with a semiconductor layer sequence comprising an n-doped layer, an active layer and a p-doped layer comprises, the semiconductor layer sequence manufactured with inverted polarity. This means, for the production of the semiconductor layer sequence is first epitaxially depositing the p-doped layer onto a growth substrate, on the p-doped layer, the active layer is epitaxially deposited and on the active layer, the n-type doped layer becomes epitaxial deposited, wherein the epitaxial growth takes place in the so-called Ga-face growth mode. The growth direction is preferably parallel to the crystallographic c-axis. For example, for a GaN based crystal this, that at the Ga-N double layers that make up the crystal is formed, the gallium atoms in the direction of the growth substrate remote surface of the crystal lie. The crystallographic c-axis and electric field show in Ga-face growth mode grown crystals, where the growth direction parallel to the crystallographic c-axis, from the growth substrate away to the crystal surface. The polarization of the piezoelectric Fields due to the stresses in the active layer has the opposite direction. Those induced by polarization Lattice charges are negative at the crystal surface facing side of the active layer and positive at the interface substrate and grown crystal facing side of the active Range.
  • It It was found that the inverted polarity of the Semiconductor layer sequences to a significant improvement of internal quantum efficiency of the semiconductor chip can result. In conventional semiconductor chips falls the internal Quantum efficiency with increasing density of the semiconductor chip impressed current strongly. In contrast, in a semiconductor chip With inverted polarity can be achieved that the internal Quantum efficiency significantly less impressed by the strength of the embossed Current depends. Ideally, the internal quantum efficiency of the Semiconductor chips almost independent of the current density.
  • For example, the publication WO 2007/012327 describes an optoelectronic semiconductor chip in which a semiconductor layer sequence with inverted polarity has grown in the Ga-face growth mode. With respect to this semiconductor chip and its manufacturing method, the disclosure of this document is hereby expressly incorporated by reference.
  • At least an embodiment of the method is used in this wafer, in which the semiconductor layer sequence with inverted polarity is prepared, then a first carrier Applied to the n-side of the wafer and finally the p-doped side exposed. That is, for example, will the growth substrate removed from the p-doped side.
  • At least an embodiment of the method is after the exposure the p-doped layer and their electrical activation these again covered by a second carrier on the p-doped Layer of the wafer is applied. The second carrier can also by means of a planarized layer of silicon dioxide be connected to the p-doped layer of the wafer.
  • About that In addition, an optoelectronic semiconductor chip is specified. Prefers is the optoelectronic semiconductor chip with one of the described here Process produced or produced.
  • At least an embodiment of the optoelectronic semiconductor chip the optoelectronic semiconductor chip comprises at least two active ones Zones. The optoelectronic semiconductor chip is, for example, by the stacking of two wafers, as described above is manufactured.
  • In accordance with at least one embodiment of the optoelectronic semiconductor chip, the optoelectronic semiconductor chip comprises a carrier and a first n-doped layer, which is arranged on an upper side of the carrier. The top of the carrier is, for example, by a major surface of the Carrier formed. Furthermore, the optoelectronic semiconductor chip comprises a first active layer following the first n-doped layer on its side facing away from the carrier, a first p-doped layer following the first active layer on its side facing away from the first n-doped layer, and a second active layer radiation-transmissive, electrically conductive layer, which follows the first p-doped layer on its side facing away from the first active layer.
  • Of the radiation-transmissive, electrically conductive Layer follows on its side facing away from the first p-doped layer Site another radiation-transmissive, electrically conductive Shift to. The other radiation-transmissive, electric conductive layer is followed by a second n-doped layer After, a second active layer follows the second n-doped layer at its the other radiation-transmissive, electrically conductive layer facing away from. Further is a second p-doped layer, that of the second active layer follows on its side facing away from the second n-doped layer, present.
  • At least an embodiment of the optoelectronic semiconductor chip contains or consists of the radiolucent, electrically conductive layer of an electrically conductive Oxide, preferably from a TCO material.
  • In accordance with at least one embodiment of the optoelectronic semiconductor chip, the first and the second p-doped layer each have a dopant concentration of at least 10 19 cm -3 , preferably of at least 10 20 cm -3 .
  • The first and the second p-doped layer preferably have a charge carrier concentration of at least 10 18 cm -3 , preferably of at least 10 19 cm -3 . Such a high concentration of charge carriers can be achieved by exposing the p-doped layers in the course of the production of the optoelectronic semiconductor chip and subsequently thermally activating them. By exposing the p-doped layers, they can be thermally activated particularly effectively, which leads to a high charge carrier concentration in the p-doped layers.
  • At least an embodiment of the optoelectronic semiconductor chip is the forward voltage per active layer at most 3.5 volts. This is for example through activation the exposed p-doped layers during fabrication of the optoelectronic semiconductor chip.
  • At least an embodiment of the optoelectronic semiconductor chip the semiconductor chip is free of a tunnel junction. This is achieved, for example, by the first p-doped layer and the second n-doped layer by means of a TCO material electrically are conductively connected to each other.
  • in the Following are the method described here as well as this one described component based on embodiments and the associated figures explained in more detail.
  • In conjunction with the 1A to 1E is explained with reference to schematic sectional views of a first embodiment of a method described herein.
  • In conjunction with the 2A to 2E is explained with reference to schematic sectional views of a second embodiment of a method described herein.
  • In conjunction with the 3A to 3E is a schematic sectional views of a third embodiment of a method described here explained.
  • In The embodiments and figures are the same or like-acting components each with the same reference numerals Mistake. The illustrated elements are not to scale On the contrary, individual elements can be better Understanding shown exaggeratedly large be.
  • In conjunction with the 1A to 1E is a schematic sectional views of a first embodiment of a method described herein for producing optoelectronic semiconductor chips described.
  • The 1A shows a first wafer 1 and a second wafer 2 , The first wafer 1 comprises a first growth substrate 11 , In the first growth substrate 11 For example, it is a sapphire substrate.
  • On top of the first growth substrate 11 is a first n-doped layer 12 epitaxially deposited. For example, the first n-doped layer is located 12 in direct contact with the first growth substrate 11 , On the first growth substrate 11 opposite side of the first n-doped layer 12 follows a first active layer 13 which comprises, for example, a pn junction, a double heterostructure, a single quantum well structure or a multiple quantum well structure suitable for radiation generation. On the first n-doped layer 12 opposite side of the first active layer 13 follows a first p-doped layer 14 to.
  • On the first growth substrate 11 is thus a first semiconductor layer sequence 100 which comprises a first n-doped layer, a first active layer and a first p-doped layer. The semiconductor layers of the semiconductor layer sequence 100 are preferably based on the material system In y Ga 1-xy Al x N with 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and x + y ≦ 1. As an n-type dopant, for example, silicon is suitable. For example, magnesium is used as the p-type dopant.
  • The second wafer 2 comprises a second growth substrate 21 , In the second growth substrate 21 For example, it is a sapphire substrate.
  • On top of the second growth substrate 21 is a second n-doped layer 22 epitaxially deposited. For example, there is the second n-doped layer 22 in direct contact with the second growth substrate 21 , On the second growth substrate 21 opposite side of the second n-doped layer 22 follows a second active layer 23 which comprises, for example, a pn junction, a double heterostructure, a single quantum well structure or a multiple quantum well structure suitable for radiation generation. On the second n-doped layer 22 opposite side of the second active layer is followed by a second p-doped layer 24 to.
  • On the second growth substrate 21 is therefore a second semiconductor layer sequence 200. which comprises a second n-doped layer, a second active layer and a second p-doped layer. The semiconductor layers of the semiconductor layer sequence 200. are preferably based on the material system In y Ga 1-xy Al x N with 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and x + y ≦ 1. As an n-type dopant, for example, silicon is suitable. For example, magnesium is used as the p-type dopant.
  • In a next process step, an electrical activation of the acceptors takes place in the exposed p-doped layers 14 . 24 of the first wafer 1 and second wafers 2 by a thermal activation method. For example, the thermal activation process is carried out by rapid thermal annealing (RTA) or in a tube furnace.
  • In conjunction with the 1B a subsequent process step is described. In this process step, the first wafer 1 on its exposed thermally activated first p-doped layer 14 with a radiation-transmissive, electrically conductive layer 15 coated, which consists for example of a TCO material. The first p-doped layer 14 opposite side of the radiation-transmissive, electrically conductive layer 15 can then be optionally polished smooth.
  • On the second p-doped layer 24 of the second wafer 2 becomes at its second active layer 23 side facing away from an adhesive layer 25 applied, which may for example contain silicon dioxide or preferably consists of silicon dioxide. By means of the adhesive layer 25 becomes a carrier 26 mechanically connected to the second wafer. The carrier 26 may be formed of sapphire, for example. At the adhesion mediation layer 25 it is preferably a planarized adhesion-promoting layer. For example, the planarization is carried out by means of a chemical-mechanical polishing.
  • In conjunction with the 1C a further method step is described. In this process step, the second wafer 2 the second growth substrate 21 for example, removed by means of a laser separation process. The thus exposed second n-doped layer 22 is polished smooth. The second n-doped layer 22 is preferably with a further electrically conductive layer 115 coated, which consists for example of a TCO material. The second n-doped layer 22 opposite side of the other radiation-transmissive, electrically conductive layer 115 can then be optionally polished smooth. For example, the electrically conductive layer 15 and the further electrically conductive layer 115 identical in composition.
  • In conjunction with the 1D a further method step is described. In this process step, the second wafer with its n-side, that is, with the smoothly polished second n-doped layer 22 applied further radiation-transparent, electrically conductive layer 115 on the radiation-transmissive, electrically conductive layer 15 applied and mechanically connected to the first wafer by means of the two radiation-transmissive, electrically conductive layers. That is, the second wafer is applied to the first wafer by bonding the radiation-transmissive, electrically conductive layer 15 and the other radiation-transmissive electrically conductive layer 115 bonded.
  • In conjunction with the 1E a further method step of the method presented here is described. In this process step, the adhesion-promoting layer 25 as well as the carrier 26 away. Like through the dividing lines 5 indicated, the wafer composite from the first wafer 1 and second wafer 2 then along the dividing lines 5 separated into individual semiconductor chips. The result is thus stacked optoelectronic semiconductor chips, each without tunnel junction zwi two semiconductor layer sequences, each comprising an active layer. For example, when fabricating a stacked LED structure with two active layers in a single epitaxy process, the use of tunnel junctions could not be avoided.
  • The optoelectronic semiconductor chips produced by the method described here are distinguished by a high dopant concentration of at least 10 18 per cm 3 , preferably at least 10 19 per cm 3 , particularly preferably at least 10 20 cm -3 in the p-doped layers or layers. The p-doped layers preferably have a charge carrier concentration of at least 10 18 cm -3 , preferably of at least 10 19 cm -3 . Such a high concentration of charge carriers can be achieved by exposing the p-doped layers during the production of the optoelectronic semiconductor chip and subsequently thermally activating them. By exposing the p-doped layers, they can be thermally activated particularly effectively, which leads to a high charge carrier concentration in the p-doped layers.
  • Further For each active layer, apply a very small forward voltage of <3.5 volts on. Such a low forward voltage is due to the thermal Activating exposed p-doped layers allows.
  • By appropriate repetition and combination of in conjunction with the 1A to 1E described manufacturing process by means of this method, the production of multiple staples is conceivable. A combination of active zones with different emission wavelengths is also possible, which can be achieved by first, second and further active zones having different material compositions. In this way, for example, a light emitting diode with an active zone that emits red light, an active zone that emits green light and an active zone that emits blue light can be produced.
  • In conjunction with the 2A to 2E is a further embodiment of a method described here explained in more detail. Unlike in conjunction with the 1A to 1E described in this method in conjunction with the 2 B described process step on the second wafer no bonding layer 25 on the exposed, thermally activated p-doped layer 24 applied, but a replacement carrier 26 , which may for example be formed by a foil or by a metal, is connected to this layer. Im in conjunction with the 2E described method step is the replacement carrier 26 removed again.
  • In conjunction with the 3A to 3E is a further embodiment of a method described here explained in more detail. In this embodiment, first, a growth substrate 31 provided. In the growth substrate 31 For example, it is a sapphire substrate. On the top of the growth substrate 31 is a p-doped layer 34 epitaxially deposited. The p-doped layer 34 follows an active layer 33 to. The active layer 33 follows an n-doped layer 32 to. Unlike in conjunction with the 1A to 1E The methods described are the semiconductor layers of the semiconductor layer sequence 300 in this case with inverted polarity in the Ga-face growth mode on the growth substrate 31 epitaxially deposited.
  • Im in conjunction with the 3B described subsequent process step is an adhesion promoting layer 25 on the n-doped layer 32 applied, optionally planarized and then with a support 26 , which may for example consist of sapphire, connected by means of bonding. The adhesive layer 25 consists preferably of silicon dioxide.
  • Im in conjunction with the 3C described method step is the growth substrate 31 for example, by means of a laser separation method of the p-doped layer 34 separated. This is then thermally activated. The thermal activation preferably takes place at temperatures between 300 ° C and 950 ° C. Due to the connection of the semiconductor layer sequence 300 with the sapphire carrier 26 about the adhesive layer 25 is the connection to the carrier 26 Stable enough not to be damaged by the temperatures during the thermal activation process.
  • Im in conjunction with the 3D described method step, that of the active layer 33 remote surface of the p-doped layer 34 optionally polished smooth and with a second carrier 27 , which may be formed by a foil or a metal, for example. For example, the carrier becomes 27 on the p-doped layer 34 glued.
  • The following is in conjunction with the 3E described method step of the carrier 26 as well as the adhesion mediation layer 25 away. Subsequently, the wafer along the dividing lines 5 separated into individual semiconductor chips.
  • All in all is in this way a polarization inverted optoelectronic Semiconductor chip produced, in which a tunnel junction is omitted.
  • The The invention is not by the description based on the embodiments limited. Rather, the invention includes every new feature as well any combination of features, especially any combination includes features in the claims, also if this feature or combination itself is not explicit specified in the patent claims or exemplary embodiments is.
  • QUOTES INCLUDE IN THE DESCRIPTION
  • This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
  • Cited patent literature
    • - WO 2007/012327 [0002, 0025]

Claims (9)

  1. Method for producing a multiplicity of optoelectronic semiconductor chips with buried p-side, comprising the following method steps: a) producing at least one wafer ( 1 . 2 . 3 ) with a semiconductor layer sequence ( 100 . 200. . 300 ) containing an n-doped layer ( 12 . 22 . 32 ), an active layer ( 13 . 23 . 33 ) and a p-doped layer ( 14 . 24 . 34 ), wherein the active layer is disposed between the n-doped layer and the p-doped layer and the p-doped layer is exposed, b) electrically activating the acceptors in the exposed p-doped layer ( 14 . 24 . 34 ) by a thermal activation method, c) covering the p-doped layer ( 14 . 24 . 34 ), and d) separating the at least one wafer ( 1 . 2 . 3 ) into a plurality of optoelectronic semiconductor chips.
  2. Method according to the preceding claim, wherein - a first ( 1 ) and a second wafer ( 2 ) are produced according to claim 1, - in process step c) first a radiation-transmissive, electrically conductive layer ( 15 ) on the activated, p-doped layer ( 14 ) of the first wafer is applied, - on the n-doped layer of the second wafer, a further radiation-transmissive, electrically conductive layer ( 115 ), and then the second wafer ( 2 ) on the further radiation-transmissive, electrically conductive layer ( 115 ) with the radiation-transmissive, electrically conductive layer ( 15 ) with the first wafer ( 1 ) is connected.
  3. Method according to the preceding claim, wherein in method step c), first of all, the p-doped layer ( 24 ) of the second wafer ( 2 ) A carrier ( 26 ) and then the n-doped layer ( 22 ) of the second wafer ( 2 ) is exposed.
  4. Method according to the preceding claim, wherein the second wafer ( 2 ) with the carrier ( 26 ) by means of a planarized adhesion-promoting layer ( 25 ) is made of silicon dioxide.
  5. The method of claim 1, wherein in step a) - first a wafer ( 3 ) with a semiconductor layer sequence ( 300 ) is produced with inverted polarity, - then a carrier ( 26 ) on the n-side of the wafer ( 3 ) and finally the p-doped layer ( 34 ) is exposed.
  6. Method according to the preceding claim, wherein in method step c) a further carrier ( 27 ) on the p-doped layer ( 34 ) of the wafer ( 3 ) is applied.
  7. Optoelectronic semiconductor chip with - a carrier ( 11 ), - a first n-doped layer ( 12 ), which is arranged on an upper side of the carrier, - a first active layer ( 13 ), which follows the first n-doped layer on its side facing away from the carrier, - a first p-doped layer ( 14 ), which follows the first active layer on its side facing away from the first n-doped layer, - a radiation-transmissive, electrically conductive layer ( 15 ), which follows the first p-doped layer on its side facing away from the first active layer, - another radiation-transmissive, electrically conductive layer ( 115 ), the radiation-transmissive, electrically conductive layer ( 15 ) follows on its side facing away from the first p-doped layer, - a second n-doped layer ( 22 ), which follows the further radiation-transmissive, electrically conductive layer, on its side facing away from the first p-doped layer, - a second active layer ( 23 ), which follows the second n-doped layer on its side facing away from the radiation-transmissive, electrically conductive layer, - a second p-doped layer ( 24 ), which follows the second active layer on its side facing away from the second n-doped layer, the radiation-transmissive, electrically conductive layer containing an electrically conductive oxide and the first and second p-doped layer each having a dopant concentration of at least 10 19 cm -3 exhibit.
  8. Optoelectronic semiconductor chip after the previous one Claim, wherein the per-active layer, the forward voltage at most 3.5 volts.
  9. Optoelectronic semiconductor chip according to one of Claims 7 or 8, free from a tunnel junction is.
DE102008013900A 2008-03-12 2008-03-12 Method for producing a multiplicity of optoelectronic semiconductor chips and optoelectronic semiconductor chip Withdrawn DE102008013900A1 (en)

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