DE102007015915A1 - Computer system-assisted electronic data processing device testing method, involves continuously writing data in unused portion of passive storage area, and comparing data with reference data to conclude functional capability of memories - Google Patents

Computer system-assisted electronic data processing device testing method, involves continuously writing data in unused portion of passive storage area, and comparing data with reference data to conclude functional capability of memories

Info

Publication number
DE102007015915A1
DE102007015915A1 DE200710015915 DE102007015915A DE102007015915A1 DE 102007015915 A1 DE102007015915 A1 DE 102007015915A1 DE 200710015915 DE200710015915 DE 200710015915 DE 102007015915 A DE102007015915 A DE 102007015915A DE 102007015915 A1 DE102007015915 A1 DE 102007015915A1
Authority
DE
Germany
Prior art keywords
memory area
memory
data
test method
method according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE200710015915
Other languages
German (de)
Inventor
Mihaly Dr. Nemeth-Csoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE102006050607.3 priority Critical
Priority to DE102006050607 priority
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE200710015915 priority patent/DE102007015915A1/en
Publication of DE102007015915A1 publication Critical patent/DE102007015915A1/en
Application status is Withdrawn legal-status Critical

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52Protection of memory contents; Detection of errors in memory contents
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24Accessing extra cells, e.g. dummy cells or redundant cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409Online test

Abstract

The method involves continuously writing test data e.g. bit-pattern, in a current unused portion of a passive storage area during operation of a computer system-assisted device (1). The test data are checked and compared with reference data to conclude the functional capability of a RAM memory (5), ROM memory (7) e.g. electrically programmable ROM memory, data memory and a program memory, where the test data vary during the operation. A CPU and the memories are realized in physically separated components.

Description

  • The The invention relates to a test method for electronic data processing equipment, in which a memory for holding program and data information is provided. This is a reliable detection of impending Errors of memory guaranteed become.
  • In such computer systems Errors in the storage of data or program code occur. Such errors can already at a new device occur if the memory modules at least partially defects exhibit. However, it may also be that over time of aging phenomena the memory chips more and more defects exhibit. Furthermore, it happens that certain manufacturing batches of memory chips are faulty.
  • The Automation technology is widely used in all areas of industry and also kept in the private sector. Especially in the industrial environment a memory error can have fatal consequences if e.g. a safety-related Automation system stops working reliably. In production plants introduces Production loss also serious consequences, at least financial.
  • at Memory module errors are especially those errors difficult recognizable, which occur only sporadically. Such non-deterministic Errors can can hardly be detected with a punctual troubleshooting. The reason for this is usually founded in that while the operation of the EDP or automation system addressing the memory is not static, but at least partially dynamic is so unpredictable which memory areas during the Operating constantly be used.
  • Consequently It can happen that defective memory cells only sometimes addressed and therefore a memory error only sometimes occurs.
  • at known methods, for example, the entire memory area completely checked when switching on or after a reset of the device. Later in the normal Operation then only the so-called active memory area, that is the area of the memory in which during the Operating data is written, checked. For this purpose, e.g. so-called checksum tests known.
  • adversely here is that a detected error in the active memory area usually also leads to an operating error of the device, as just in the active memory area the processing of the current automation solution takes place. such Error detections are therefore usually very late or even too late, to a failure of the device still to prevent.
  • The The invention therefore has the object of providing a test method for EDP and Specify automation systems, by means of which memory error as possible early can be recognized causing a failure of the device preferably is prevented.
  • The Invention is based on the consideration, that a test of those memory areas, which does not use become, valuable conclusions on the functionality of the entire memory including the active memory areas allows. With great Likelihood can be an unused one with a recognized error Memory area also on possible Errors of the used memory area are closed as both Memory areas are physically realized in the same hardware.
  • The Invention leads therefore a test procedure for computer-assisted system equipment with at least one memory area, where one currently not used part of the memory area written test data written Test data checked and with Target data are compared to the functionality to close the memory area.
  • The Inventive test method disturbs thus the operation of the device not because it is on the unused part of the memory area limited. For example, the test data can be bit patterns, which specifically in the unused part of the memory area to be written. Such test patterns may be suitably predetermined in advance to be at a later Comparison of the written test data with the expected score preferably good evidence of a possible present or imminent source of error.
  • Of the currently unused part of the memory area can parts of memory area include, which during the operation of the device not be used or which may only be used intermittently during operation of the device be used.
  • Prefers the test data will be kept running during the operation of the device written to the currently unused part of the memory area.
  • Hereby, the unused part of the memory area is constantly tested by preferably writing an always different test bit pattern into the area and constantly checking whether the written content meets the expectations. The current writing of the test data should mean that not only unique test data in the unused part of the memory area are written, but that this happens several times during operation.
  • Should to bring the comparison to light, that there is a memory error, that is the written test data does not match the expected writing result (target data), so can the device Nevertheless, continue to be easily operated as the test method of the invention refers to the unused part of the memory area and thus the processing of program code and data is not affected.
  • Yet give such recognized memory problems in the unused part the memory area hints that sooner or later also in the active area the memory error could occur. Such probability statements are a valuable basis for predictive maintenance.
  • In According to an advantageous embodiment, the memory area comprises a active and a passive memory area, where the active memory area that part of the memory area which is provided for this purpose is, sometime during of the operation to record and read data. Farther includes the currently unused part of the memory area at least part of the passive memory area.
  • at this embodiment In the invention, the test method is applied to an unused one Memory area, the passive memory area. This will check if this unused part of the memory is working properly or whether there faulty memory cells are present.
  • Of the Active and the passive memory area are in the same Hardware realized, with a distinction in active and passive only regarding memory usage is defined by a program. If so found faulty memory cells in the passive memory area It may also indicate possible problems in the active memory area be closed because, as already mentioned, both memory areas physically not different. For example, aging processes cause that some memory cells over time become memory errors tend. A detection of a memory error in the passive memory area may therefore be an indication of a possible memory error as well in the active area, which for the program execution is used. Will now be at a memory area in the passive memory area defective memory cells found by means of the test method according to the invention, For example, the entire storage area can be renewed, to possible future problems, which can also affect the active memory area, to prevent.
  • In a further preferred embodiment The currently unused part of the memory area comprises at least a part of the active memory area, which currently not used is.
  • During the Program runtime often happens before that, although an active memory area for the execution of the program is provided, but not at all times, all parts of the active memory area indeed to be used. The test method according to the invention can now also such parts of the active memory area are used which not be used at a current time and therefore for the execution the test method according to the invention can be used.
  • There this currently unused Part of the active memory area during the program runtime can be used once, a detection of a Memory error in this area a valuable indication provide that a memory problem could be imminent, which would affect the operation of the equipment immediately endangered. If you look at a detected error fast enough responds, for example, refreshing the memory area a failure of the device be prevented before e.g. a loss of production or a hazard occurs.
  • alternative or in addition is it possible, for example, to define test memory areas between active memory areas and these as currently unused parts of the memory area for execution the test method according to the invention to use. Here, the detection of an optionally existing memory error in this currently unused part the memory area between active memory areas a particular good measure for eventual imminent memory problems because of a closeness of this currently unused one Memory part to the active memory area is present, usually in physically, allowing an overriding of the memory error to the active memory area is likely.
  • at becomes a memory problem identified by the comparison prefers an indication of this memory problem to a user computer system-supported equipment output.
  • In the case of a number of computer system supported devices, the test method may preferably be applied in parallel to this number and the output hints collected and be evaluated together.
  • On this way it is possible Correlations between the detected memory problems of different equipment to determine, for example, using stochastic methods. So, a prediction about possibly upcoming memory problems even more accurate.
  • From Therefore, the evaluation of the output hints to a forecast to lead, which indicates an imminent failure of the storage area at least one of the devices shut down leaves.
  • Prefers will be the writing of the test data and the comparison by a processor carried out and the processor is with the at least one memory area via a Data bus connected.
  • in the In the case of a decentralized arrangement of a plurality of devices, the test method according to the invention can thus have a Datenbus be made, which the respective devices with the Processor connects. The data bus is a means of doing this Distribute test data from the processor to the devices and the memory results to read out for the Comparison. So it does not have to be a test procedure separately in each device but the test procedure is also physical separate units applicable.
  • In a particularly preferred embodiment will the test data during of operation varies, for example, one used as test data Bit pattern, which is in the currently unused memory area should be written, constantly changing.
  • Thereby Is it possible, one maybe to predict the upcoming memory error even better, because under circumstances undetected systematic memory errors caused by a rigid test bit pattern can not be revealed, undetected stay.
  • in the Following are two embodiments closer to the invention shown.
  • It demonstrate:
  • 1 a computer-assisted device with RAM and ROM memory for carrying out the method according to the invention, and
  • 2 an example of a memory area comprising a RAM and ROM memory with active and passive memory parts for carrying out the method according to the invention.
  • ROME should also be representative of erasable ROMs such as EPROMs, EEPROMs, etc.
  • In the 1 is a computer-aided device 1 represented, which is a central unit 3 comprising a Prozes sensor and a RAM memory 5 and a ROM memory 7 includes. The central unit 3 , the RAM memory 5 and the ROM memory 7 are here by means of a data bus 9 connected, which can also be designed redundant.
  • The inventive method is now carried out by means of the central unit 3 over the data bus 9 Test data, for example a test bit pattern, in the RAM memory 5 and / or in the ROM memory 7 to be written. The said memory can also be present several times. In RAM memory 5 it can be a data store and ROM 7 may include, for example, a program memory with the program code.
  • The central unit 3 again reads via the data bus 9 the memory results resulting from the writing of the test data to the memories 5 and 7 have resulted. The writing of the test data happens in currently unused memory areas of the memory 5 and or 7 ,
  • Now deviates the readout result from at least one of the memory 5 and or 7 from the original written test data, then a user note 11 which indicates a possible memory problem.
  • In essence, it is therefore checked here whether test data is error-free in the unused memory area of the memory 5 and or 7 were written. In the case of a negative result of this comparison is by means of the user information 11 a memory problem is displayed.
  • During operation of the device 11 the test method is preferably performed continuously, wherein the test data is continuously written, read and evaluated in the current unused memory area.
  • In the 2 is a data store 13 and a program memory 15 a computer-aided device 1 shown, the data memory 13 for example as RAM and the program memory 15 for example, as a ROM.
  • The data store 13 In this example, it has three active memory areas 17 and two passive memory areas 19 on. The program memory 15 includes four active memory parts 17 so like two passive memory parts 19 ,
  • For the passive memory areas 19 These may be memory areas that occur during operation of the device 1 not at all or around such memory areas that are not used at any time (in each processing cycle).
  • By means of the test method according to the invention, the test data now becomes at least one of the passive memory areas 19 at least one of the memories 13 and or 15 written, read out and evaluated.
  • A defect of one of the passive memory areas 19 , in which test data was written, is expressed by the fact that when reading this passive memory area another data pattern is read than previously written using the test data.
  • This discrepancy leaves on a memory problem of the memory 13 respectively. 15 shut down.
  • Since at least currently unused memory areas are used by means of the test method according to the invention, a detected memory problem usually does not (yet) lead to a failure of the device 1 Rather, it is an indication of a potential imminent memory problem. A timely initiated maintenance measure can therefore prevent bad consequences usually targeted.
  • Furthermore, in the case of an active memory area recognized as defective 17 this recognized by a recognized as error-free passive memory area 19 be replaced. This allows the device to remain in operation despite a memory error.

Claims (11)

  1. Test Method for Computer System Supported Devices ( 1 ) with at least one memory area ( 5 . 7 . 13 . 15 ), in particular for detecting errors in the data storage, wherein in a currently unused part of the memory area ( 19 ) Written test data, the written test data is checked and compared with target data to the operability of the memory area ( 5 . 7 . 13 . 15 ) close.
  2. The test method according to claim 1, wherein the test data is continuously during operation of the device ( 1 ) into the currently unused part of the memory area ( 19 ) to be written.
  3. Test method according to claim 1 or 2, wherein - the memory area ( 5 . 7 . 13 . 15 ) an active ( 17 ) and a passive memory area ( 19 ), wherein the active memory area ( 17 ) is that part of the memory area which is intended to receive and read data at some point during operation, and - the currently unused part of the memory area ( 5 . 7 . 13 . 15 ) at least part of the passive memory area ( 19 ).
  4. Test method according to one of claims 1 or 2, wherein - the memory area ( 5 . 7 . 13 . 15 ) an active ( 17 ) and a passive memory area ( 19 ), wherein the active memory area ( 17 ) is that part of the memory area which is intended to receive and read data at some point during operation, and - the currently unused part of the memory area ( 5 . 7 . 13 . 15 ) at least part of the active memory area ( 17 ), which is currently not in use.
  5. Test method according to one of claims 1 to 4, wherein in case of a memory problem determined on the basis of the comparison, a reference ( 11 ) to the memory problem to a user of the computer system supported device ( 1 ) is output.
  6. The test method of claim 5, wherein the test method is parallel to a number of computer system supported devices ( 1 ) and the notes ( 11 ) and evaluated together.
  7. The test method according to claim 6, wherein the evaluation comprises a prognosis which is based on an imminent failure of the memory area. 5 . 7 . 13 . 15 ) at least one of the computer system supported devices ( 1 ).
  8. Test method according to one of claims 1 to 7, wherein the writing of the test data and the comparison by a processor ( 3 ) and the processor ( 3 ) with the at least one memory area ( 5 . 7 . 13 . 15 ) via a data bus ( 9 ) connected is.
  9. A test method according to claim 8, wherein the processor ( 3 ) and the at least one memory area ( 5 . 7 . 13 . 15 ) are realized in physically separate units.
  10. Test method according to one of claims 2 to 9, where the test data during vary in operation.
  11. Test method according to one of claims 1 to 10, wherein in one recognized as defective active memory area of this by one as error-free recognized passive storage area is replaced.
DE200710015915 2006-10-26 2007-04-02 Computer system-assisted electronic data processing device testing method, involves continuously writing data in unused portion of passive storage area, and comparing data with reference data to conclude functional capability of memories Withdrawn DE102007015915A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE102006050607.3 2006-10-26
DE102006050607 2006-10-26
DE200710015915 DE102007015915A1 (en) 2006-10-26 2007-04-02 Computer system-assisted electronic data processing device testing method, involves continuously writing data in unused portion of passive storage area, and comparing data with reference data to conclude functional capability of memories

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE200710015915 DE102007015915A1 (en) 2006-10-26 2007-04-02 Computer system-assisted electronic data processing device testing method, involves continuously writing data in unused portion of passive storage area, and comparing data with reference data to conclude functional capability of memories
PCT/EP2007/060603 WO2008049719A1 (en) 2006-10-26 2007-10-05 Test method for computer system-assisted devices with at least one memory area

Publications (1)

Publication Number Publication Date
DE102007015915A1 true DE102007015915A1 (en) 2008-04-30

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DE200710015915 Withdrawn DE102007015915A1 (en) 2006-10-26 2007-04-02 Computer system-assisted electronic data processing device testing method, involves continuously writing data in unused portion of passive storage area, and comparing data with reference data to conclude functional capability of memories

Country Status (2)

Country Link
DE (1) DE102007015915A1 (en)
WO (1) WO2008049719A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175300A (en) * 1987-01-16 1988-07-19 Hitachi Ltd Semiconductor integrated circuit device
US6742148B1 (en) * 2000-03-06 2004-05-25 Pc-Doctor Inc. System and method for testing memory while an operating system is active
US6763444B2 (en) * 2001-05-08 2004-07-13 Micron Technology, Inc. Read/write timing calibration of a memory array using a row or a redundant row
US6671645B2 (en) * 2001-09-28 2003-12-30 Ciena Corporation Method for in-service RAM testing
US7107493B2 (en) * 2003-01-21 2006-09-12 Hewlett-Packard Development Company, L.P. System and method for testing for memory errors in a computer system

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