DE102005000809A1 - Integrated semiconductor memory, for control circuits, has volatile memory cells refreshed with production and operating parameter data from non-volatile memory cells - Google Patents

Abstract

Integrated semiconductor memory, with a non-volatile data storage, has an initial memory cell field (SF1) with volatile and non-volatile memory cells. A second memory cell field (SF2a) is composed entirely of volatile memory cells. The non-volatile cells of the first field are used to plot operating parameters while the memory is in use, where one parameter refreshes the volatile memory cells in the second field from storage in the non-volatile cells in the first field. The integrated semiconductor memory, with a non-volatile data storage, has an initial memory cell field (SF1) with volatile memory cells (SZT,SZC) and non-volatile cells (WZ). A second memory cell field (SF2a) is composed entirely of volatile memory cells. The non-volatile cells of the first field are used to plot operating parameters while the memory is in use, where one parameter refreshes the volatile memory cells in the second field from storage in the non-volatile cells in the first field. The integrated memory can store data in the volatile memory cells and hold production and parameter data in the non-volatile cells within the same control circuit. To input and read data at the two types of cells, the scanning amplifiers (SA) are each linked to external data connections (DQ) by a data bus (LDQ).

Description

The The present invention relates to an integrated semiconductor memory, in the data on non-volatile Way are storable.

at integrated semiconductor memories, such as DRAM (dynamic random access memory), the failure rate is in the first hours of operation relatively high. To faulty components be sorted out after the production, the integrated Semiconductor memory after completion of the manufacturing process for a few Operating hours stressed. Within this short operating time let yourself already a large part sort out defective blocks. It further shows that on a statistical average only after a long period of operation, such as several years, the failure rate increases again. To analyze such long-term failures to be able to would it be desirable; if while the operation of a semiconductor memory operating parameters, such as the duration of operation or the number of specific events, such as Memory accesses to a specific memory area permanently and could be permanently recorded.

at a semiconductor memory with volatile memory cells, such as dynamic random access memory (DRAM) memory cells the memory contents at the latest refreshed after a data retention period has expired. Unlike nonvolatile Semiconductor memory, such as Flash, FeRAM (ferroelectric random access memory) or MRAM (magnetic random access memory) semiconductor memories There is thus the problem with DRAM semiconductor memories that production- and test-relevant long-term information such as test results, sort criteria, production-relevant data, but also operating parameters, the while the operation of the integrated semiconductor memory do not occur can be stored irreversibly and permanently.

Around to permanently store data in a DRAM semiconductor memory therefore electrical fuses (e-fuses) or laser fuses are used. Laser fuses can only while the production of the integrated semiconductor memory can be programmed. About e-fuses can also be housed State of a DRAM memory permanently storing data by the E-fuses can be programmed by applying a programming voltage. One small field of e-fuses is generally still easily evaluable. If, however, larger quantities to permanently store data must have a fuse array structure be provided. Within the fuse array structure, the e-fuses are like the volatile ones DRAM cells in the memory cell array, generally in a matrix shape arranged by column and row lines. For reading the programming state each of the e-fuses requires a row / column decoder architecture. by virtue of of the big one Space requirements for such circuits become large e-fuse memory areas generally not in semiconductor memory with volatile memory cells integrated.

Of Furthermore, e-fuses have the disadvantage that they are programmed only once can be. Thus, changes can be made of data, as for example in the operating parameters in Over the operating time occur, not stored in the same e-fuses changed become.

The The object of the present invention is an integrated semiconductor memory indicate where it allows is to reliably store manufacturing and operating data over a longer period. Another object of the present invention is a method specify with which in an integrated semiconductor memory Manufacturing and operating data about a longer period reliable save.

The Task concerning the integrated semiconductor memory is solved by an integrated semiconductor memory having a first memory cell array with fleeting Memory cells and with non-volatile Memory cells, with a second memory cell array with volatile Memory cells and with a control circuit for controlling a Access to one of the memory cells of the first and second memory cell array. According to the invention Control circuit designed such that they are in an access to one of the fleeting ones Memory cells of the second memory cell array write access at least one of the non-volatile Memory cells of the first memory cell array performs for storage one of the current operation of the integrated semiconductor memory determined date in at least one of the non-volatile Memory cells of the first memory cell array.

By using a memory cell array with both volatile and nonvolatile memory cells, the same drive circuits as row decoders, column decoders, and sense amplifiers can be used, which also serve to write information to the volatile memory cells and to read information from the volatile memory cells. As a result, the space requirement is significantly reduced, since additional storage space is to be provided only for the non-volatile memory cells. The date determined in the current operation of the integrated semiconductor memory may be For example, to act on an operating parameter that has occurred in the context of a test operation of the integrated semiconductor memory. This can be, for example, a lot number or the name of a test program. However, it may also be an operating parameter that indicates an operating state of the semiconductor memory. This includes, for example, the number of accesses to a specific memory area or the operating temperature that has occurred during operation of the integrated semiconductor memory.

According to one Further development of the integrated semiconductor memory are the volatile ones Memory cells of the first and second memory cell array, respectively designed such that after storage of a memory state in one of the volatile memory cells to preserve the stored memory state, the memory state at the latest after The course of a data retention period must be refreshed. The control circuit is designed such that it to preserve the stored memory state in one of the memory cells of the second memory cell array the refreshes stored in one of the memory cells memory state and doing so in the current operation of the integrated semiconductor memory determined date in one of the nonvolatile memory cells of the first memory cell array stores.

at another embodiment of the integrated semiconductor memory are in the first and second Memory cell array sense amplifier provided, each to a bit line pair with a first and a second bit line are connected. The fleeting ones Memory cells and the nonvolatile memory cells of the first memory cell array are each connected to a bit line pair connected. The fleeting ones Memory cells and the nonvolatile memory cells are each designed such that they read a potential difference during reading between the first and the second bit line of the bit line pair (BLP) to which they are respectively connected produce. The sense amplifiers are each designed such that they are in the reading of one of the volatile memory cells and one of the non-volatile Memory cells each the potential difference between the first and the second bit line of the bit line pair to which they respectively are connected, evaluate and evaluated depending on the evaluated Potential difference a date with a first or second level produce.

According to one Development of the integrated semiconductor memory are the non-volatile Memory cells for a reading and Write access via Addresses selectable. The control circuit is designed such that it at a first Enabling the integrated semiconductor memory an address position the last described nonvolatile memory cell determined and that in the current operation of the integrated semiconductor memory determined date at the address position last described following next higher Stores address position.

at an embodiment of the integrated semiconductor memory are the nonvolatile ones Memory cells each as a single irreversible programmable Components designed. The non-volatile memory cells can also each formed as an electrically programmable fuse or antifuse be. According to one another embodiment of the integrated semiconductor memory include the nonvolatile ones Memory cells at least one controllable resistor. The fleeting ones Memory cells are preferably each with memory cells trained random access.

One Method for recording manufacturing and operating data of a integrated semiconductor memory sees the use of an integrated semiconductor memory with a first memory cell array with nonvolatile memory cells and volatile memory cells and a second memory cell array with volatile memory cells, where the non-volatile Memory cells first non-volatile memory cells and second non-volatile Memory cells include, wherein in the first non-volatile memory cells an information about the configuration of the second non-volatile Memory cells is stored. After booting up the integrated Semiconductor memory become the memory states of the first non-volatile Memory cells evaluated to provide information about the configuration the second non-volatile To get memory cells. Subsequently, an address position a last described second nonvolatile memory cell in the first Memory cell field determined. After that, one will go to the address position the last described second nonvolatile memory cell following next higher Adresspostion determined. That in the current operation of the integrated Semiconductor memory determined date is in a second non-volatile Memory cell of the first memory cell array, over the selected next higher Adresspositon is addressable, in a configuration depending from the evaluated memory state of the first non-volatile Memory cells stored when one of the volatile memory cells of the the second memory cell array is refreshed.

According to one Further development of the method for recording operating data of a integrated semiconductor memory is stored in the current Operation of the integrated semiconductor memory ascertained date Setting a bit in a register of the integrated semiconductor memory read from the one of the second non-volatile memory cells.

A other embodiment the method of operating an integrated semiconductor memory provides the integrated semiconductor memory in a test mode to operate. In the test mode, each of the first and second non-volatile Memory cells by applying a control signal to the integrated Semiconductor memory read out.

Further Forms of training concerning the integrated semiconductor memory for recording operating data and the method for recording Operating data can be found in the dependent claims.

The Invention will be described below with reference to figures, the embodiments of the present invention, explained in more detail. Show it:

1 an integrated semiconductor memory for storing operating data according to the invention,

2 a semiconductor memory chip with memory banks for storing operating data according to the invention,

3 a memory bank of an integrated semiconductor memory for storing operating data according to the invention,

4 a section of a memory cell array of a memory bank with volatile and nonvolatile memory cells according to the invention,

5A an address organization of a memory bank according to the invention,

5B an address organization of a memory area with nonvolatile memory cells according to the invention,

5C first nonvolatile memory cells according to the invention for storing configuration data,

6 a binary address search in a memory cell array with nonvolatile memory cells for finding a start address for storing operating data according to the invention,

7 a flowchart for storing operating data in nonvolatile memory cells according to the invention.

1 shows an integrated semiconductor memory 100 with a memory cell array 10 , Within the memory cell array 10 volatile and non-volatile memory cells are arranged in a first memory cell array SF1 and volatile memory cells in a second memory cell array SF2. As an example of a non-volatile memory cell, a DRAM memory cell SZ is arranged in the second memory cell array SF2, which is arranged between a word line WL and a bit line BL. The DRAM memory cell includes a selection transistor AT and a storage capacitor SC. In the case of a read or write access, the memory cell is activated by the selection transistor AT being conductively controlled by a corresponding signal on the word line WL, so that the storage capacitor SC is connected to the bit line BL in a low-resistance manner.

For controlling read, write and precharge processes within the memory cell array 10 is a control circuit 20 intended. For controlling read and write accesses, control signals are applied to a control terminal S20. For selecting one of the memory cells of the first or second memory cell array, an address signal ADS is applied to an address terminal A30. The applied address has an x and a y address part. The address part X becomes a row decoder 70 and the address part Y becomes a column decoder 80 fed. On the basis of the x and y address of the address signal ADS, a memory cell SZ can be selected for a read or write access. For writing information, a data D is applied to a data terminal DQ. When reading a date D is generated at the data terminal DQ.

2 shows a semiconductor chip HC comprising memory banks B1, B2, B3 and B4. Inside the memory banks are, as in 1 shown, volatile and nonvolatile memory cells in a first memory cell array SF1 and only volatile memory cells, such as DRAM memory cells, arranged in a second memory cell array SF2. In the 1 shown remaining circuit components, such as the control circuit 20 or the address register 30 are arranged between the memory banks, in the so-called spin region SP, of the semiconductor chip.

3 shows an enlarged view of a section of a memory bank. At the edge of the memory bank is the first memory cell array SF1, which contains the volatile and nonvolatile memory cells. Subsequently, second memory cell arrays SF2a, SF2b, SF2c and SF2d are arranged. The memory cell arrays are each separated by sense amplifier strips SAS in which reader amplifiers for amplifying the memory contents of a selected memory cell or for amplifying the data applied to the data terminal DQ for writing in an out chose memory cell located.

4 shows a section A of the memory bank B from 3 , The bit lines BL are formed within the first memory cell array SF1 and the second memory cell array SF2a as Bitleitungswist. At crossing points of word lines WL and bit lines BL, true memory cells SZT or complement memory cells SZC are arranged. The bit lines are each connected in pairs to a sense amplifier SA. A bit line pair includes a true bit line BLT and a complement bit line BLC. Within the first memory cell array SF1, nonvolatile memory cells WZ are arranged between the true bit line BLT and the complement bit line BLC. In the second memory cell array SF2a only volatile memory cells are present. These are also arranged along word line WL and bit lines BLC and BLT. A true bit line BLT and a complement bit line BLC are also arranged here as a bit line pair and in each case connected to a sense amplifier SA. Along the true bit line BLT are true memory cells SZT and along the complement bit line BLC are complement memory cells SZC arranged.

For writing or reading information from the volatile memory cells or the nonvolatile memory cells, the sense amplifiers are each connected to the external data terminal DQ via a data bus LDQ. The sense amplifiers connected to the bit lines of the first memory cell array SF1 selectively store information in the volatile memory cells SZ or the nonvolatile memory cells WZ. The nonvolatile memory cells WZ are also assigned row and column addresses as well as the volatile memory cells. Advantageously, the nonvolatile memory cells as well as the volatile memory cells can be passed through the row and column decoders 70 and 80 choose. The nonvolatile memory cells include, for example, a programmable resistor. Depending on the programmed resistance value, a potential shift occurs on the bit lines of a bit line pair which is evaluated by the connected sense amplifier. The non-volatile memory cells may also be designed as MRAM, FeRAM or SRAM memory cells. For selecting one of the volatile and non-volatile memory cells and for reading and writing information from or into the volatile and non-volatile memory cells, the same drive circuits can be used. Thus, for the non-volatile memory cells no separate memory cell array needs to be provided with its own control logic.

5A shows a logical address space of a memory bank with x and y addresses X0, ..., X31 and Y0, ..., Y255. The low-order x address range includes the addresses X0,..., X15. The higher-order x address range includes the addresses X16,..., X31. Via the addresses can be selected word lines which are connected to the volatile memory cells in the first o of the second memory cell array. Nonvolatile memory cells within the first memory cell array can be selected via the addresses X _w 0,..., X _w 3.

The Distribution of the address space in address ranges that are volatile Memory cells are linked and in address areas associated with nonvolatile memory cells, can over Area definition or bit injection. In the area definition can be non-volatile Address memory cells with address values above a certain value. Address values below this value are addressed by volatile memory cells. at The bit injection is used to access the nonvolatile memory cells an address bit at a particular position of a bit address For example, the logical value "1" is set choose then a non-volatile one Memory cell in the first memory cell array off.

5B shows the address space of the nonvolatile memory cells. First non-volatile memory cells WZa are located in an address area KB, which is addressable via the addresses X _w 0 and the addresses Y0, ..., Y15. In the first nonvolatile memory cells, configuration data for configuring second nonvolatile memory cells WZb, in which the actual operating data are stored, can be stored. The second non-volatile memory cells WZb are located at the address positions X _w 0 and Y16, ..., Y255; X _w 1 and Y0, ..., Y255; X _w 2 and Y0, ..., Y255; X _w 2 and Y0, ..., Y255; X _w 3 and Y0, ..., Y255. In the second non-volatile memory cells WZb operating data of the integrated semiconductor memory are preferably stored.

5C shows a possible assignment of the first non-volatile memory cells WZa with configuration information. Shown are the first nonvolatile memory cells WZa0, ..., WZa15 that can be selected via the addresses X _w 0, Y0,..., Y15. The memory cell WZa0 of the first nonvolatile memory cells contains information as to whether the operating data in the second nonvolatile memory cells are stored in a prefix mode. When storing an operating parameter in the prefix mode, several of the second nonvolatile memory cells are described when storing an operating parameter. Some of the second non-volatile memory cells provided for storing a particular operating parameter are used to identify the operation save sparameters. A storage of operating data in the prefix mode is particularly useful if within the memory area of the second non-volatile memory cells of 5B various operating parameters are stored. Another advantageous application of the prefix mode is when the occurrence of an error is logged within the non-volatile memory area. In addition to the occurrence of the actual error event can be, for example, the error address of a memory cell, the prevailing temperature at the occurrence of the error and store reference currents or reference voltages.

The memory cell WZa1 of the first nonvolatile memory cells of the configuration area contains information as to whether the memory area of the second nonvolatile memory cells should be used to store an operating parameter. A possible operating parameter is, for example, the operating life of the integrated semiconductor memory. For logging the operating time is a counter circuit on the integrated semiconductor memory 60 intended. The counter circuit 60 contains a register whose current counter reading is increased every six minutes, for example. The counter reading is at regular intervals from the control circuit 20 stored in the nonvolatile second memory cells of the first memory cell array SF1.

The memory cell WZa2 of the first nonvolatile memory cells within the configuration area contains information as to whether the operating parameter to be stored is to take place during background storage during operation of the integrated semiconductor memory, for example during a refresh operation of memory cells located in the second memory cell array SF2. There, as in 4 As shown, nonvolatile memory cells are arranged only in the first memory cell array SF1, the storage of operating parameters in the nonvolatile memory cells can take place in parallel with the refresh operation of the volatile memory cells of the second memory cell array SF2a.

If programmed the memory cell WZa3 of the first non-volatile memory cells is, the second nonvolatile memory cells WZb can be externally describe the first memory cell array, or it can be externally an operating parameter for storage in the non-volatile memory cells choose. Describing the nonvolatile Memory cells takes place in a so-called Appending mode. This means that already described non-volatile second memory cells are not overwritten can be. Instead becomes the nonvolatile second memory cell described last determined and in the address space next higher non-volatile second memory cell for the Save operation selected.

The memory cell WZa4 of the first nonvolatile memory cells within the configuration area indicates whether only read access to the nonvolatile second memory cells is permitted. If the read access is permitted, operating data can be read from the nonvolatile second memory cells WZb in an application. As an operating parameter can be, for example, from a temperature sensor 50 in 1 determine an operating temperature in a register 40 is cached. The operating temperature is out of the register 40 in a refresh process of volatile memory cells of the second memory cell array read and stored in the second nonvolatile memory cells of the first memory cell array.

If the read access to the nonvolatile memory cells is allowed evaluate the operating temperature of a memory controller. Of the Memory controller can then, for example, at a high operating temperature reduce the operating frequency of the semiconductor memory.

Of the Memory state in the first nonvolatile memory cells WZa5 and WZa6 within the configuration area indicates whether the storage an operating parameter within the non-volatile second memory cells bit, byte or wordwise should be done. For a byte or wordwise storage of a Operating parameters is the information encoded in several bits. In the bitwise storage, however, is the information of the stored Operating parameters encoded in a single bit. If, for example the operating time is to be stored bit by bit, so in certain Intervals, for example, every six minutes, once a refresh process for memory cells takes place within the second memory cell array, one of second non-volatile Memory cells WZb described.

At the beginning of the operating period, for example, the non-volatile second memory cell associated with the address X _w 0, Y16 is described as having a "1" level. Every six minutes later, a memory cell following the last-described non-volatile memory cell in the address space, that is, the memory cell associated with the address X _w 0, Y17 at the second memory, is written at the logical "1" level Storage duration over a 10-year period requires 876,000 non-volatile memory cells, compared to typical 512 Mb DRAM memory cells, which only require 0.163% additional memory necessary.

The memory cells WZa6, ..., WZa14 of the first nonvolatile memory cells contain information about the number of logical memory areas into which the second nonvolatile memory cells are divided. Furthermore, the first non-volatile memory cells WZa6,..., WZa14 contain information about the operating parameters to be stored within a memory area. This makes it possible, for example, the logical address space of nonvolatile memory cells of 5B into two different areas, wherein in a first nonvolatile memory area the number of activations of sense amplifiers in a particular reader amplifier strip is logged over an operating period and in a second nonvolatile memory area the operating temperature is recorded over a longer period of time.

The Memory cell WZa15 of the first nonvolatile memory cells includes a Information as to the storage capacity of the second non-volatile memory cells already complete exhausted is because all second nonvolatile Memory cells are already described with information data. If the non-volatile Memory cell WZa15 is programmed with a logical "1" level, for example, is the available Memory space exhausted and logging an operating parameter into the second non-volatile one Memory cells is interrupted.

Of the Memory state of the first nonvolatile memory cells is either already during production or only later in operation of the integrated semiconductor memory. So, for example the later one Use of the second non-volatile Memory cells for storing an operating parameter by a Pre-programming of the first non-volatile memory cells in the configuration area already determined by the manufacturer. A specific area the second non-volatile Memory cells WZb can, for example, for logging the operating time be provided of the integrated semiconductor memory.

If a memory area with non-volatile memory cells is first configured in an application, then, for example, the logging of the operating temperature can be started by a signaling bit in a register 21 , such as the mode register or the extended mode register. When the control circuit 20 detects the set bit in one of the two registers, for example, it selects a non-volatile memory area for recording the operating temperature and sets by programming the first non-volatile Speicherzel len the configuration of the second non-volatile memory cells independently. When accessing the nonvolatile memory cells via the mode / extended mode register, preferably only access in appending mode, ie without overwriting of already programmed nonvolatile memory cells, is permitted. As a further restriction, it may be provided that the user of the integrated semiconductor memory can only read access to certain shared non-volatile memory areas in an application.

In addition to the possibility of accessing the nonvolatile memory cells by setting a bit in a mode register or an extended mode register, it is also possible to apply a characteristic test mode signal TM or one or more characteristic key bit sequences to the control terminal S20 of the control circuit 20 to access the nonvolatile memory cells. If, for example, the integrated semiconductor memory has failed in one application and is sent back to the manufacturer as a customer return, the manufacturer can read out the entire nonvolatile memory area via the characteristic key bit sequences. This makes it possible to draw conclusions about possible causes of failure of a memory module. It is also possible to store various manufacturing and test data such as trim modes, test program names, lot assignments and assignments to production machines in the nonvolatile memory cells via the test mode signal even before delivery of the component. Thus, a failed module can be assigned to a production period and a production line. On the basis of the knowledge of the production parameters, it is also often possible to draw conclusions about the cause of the failure in the case of a failed component.

If a storage area of second nonvolatile memory cells continuously continuously from low to high address positions becomes, so at each startup of the semiconductor memory within the memory area of the non-volatile Memory cells determines the address position, starting from during the following operating time the storage of operating parameters continues can be. This prevents that already described nonvolatile Memory cells overwritten become.

6 shows the address space AB1 of the nonvolatile memory cells. In the example of 6 All nonvolatile memory cells which belong to an address y <143 have already been programmed by already storing operating data there. When the nonvolatile memory area continuously progresses from low to high hen address position is described, so after the startup of the integrated semiconductor memory, the address of the next free to be described non-volatile memory cell is determined by a binary address search. In the following, the determination of a free memory cell will be described on the basis of its assigned y-address. If the nonvolatile address space has the address positions y = 0 to y = 255, the memory state of a nonvolatile memory cell at the address position y = 255 is examined at the beginning of the binary address search algorithm. In the example of 6 are stored in the nonvolatile memory cells associated with the address y = 255, no operating parameters. Subsequently, the address space is halved and carried out at the address position y = 127 an evaluation of the memory state of the associated non-volatile memory cells. Since the nonvolatile memory cells are described here, the next free nonvolatile memory cell must be in the address space between the addresses y = 127 to y = 255. After halving this address space, the address position y = 191 is examined. Since no operating parameter is stored at the memory cells at this address position, the last described nonvolatile memory cell must lie in the address space y = 127 to y = 191. By continuously halving the address intervals, the address y = 143, at which the last described non-volatile memory cell is located, is finally found. Thus, in the following, the logging of an operating parameter can be continued at the address position y = 144.

7 shows a flowchart for logging an operating parameter. In the example of 7 For example, in the manufacture of the integrated semiconductor memory, a non-volatile memory area has been provided in which the occurrence of an error event during the operating time of the integrated semiconductor memory is recorded. After starting up the semiconductor memory evaluates the control circuit 20 the first nonvolatile memory cells within the configuration area of the nonvolatile memory area. When the nonvolatile memory cell WZa15 has the logic state "0", the memory area is not fully described. In this case, the end address of the non-volatile memory area is determined by a binary address search. The control circuit 20 subsequently activates the event counter, in the example the occurrence of a specific error event. When the error occurs, an event register is programmed accordingly. The event register serves as a buffer. When volatile memory cells within the second memory cell array are refreshed, the current value of the event register can be stored in the nonvolatile memory cells of the first memory cell array. As long as the non-volatile memory cell WZa1 has the logical memory state "1", each time the error event occurs, a non-volatile memory cell in the first memory cell array is programmed when refreshing volatile memory cells in the second memory cell array. By a state change of the non-volatile memory cell WZa1 from the logical "1" state to the logic "0" state, the logging of the error event can be interrupted at any time.

10

Memory cell array

20

control circuit

21

Mode Register

30

address register

40

memory register

50

temperature sensor

60

Hour meter

70

row decoder

80

column decoder

AT

selection transistor

B

memory bank

BL

bit

BLP

bit line

D

date

DQ

data port

SA

sense amplifier

SAS

Wordline strips

SC

storage capacitor

SF

Memory cell array

SP

Spine-area

SZ

volatile memory cell

WL

wordline

WZ

non-volatile memory cell

X, Y

addresses

Claims (25)

Integrated semiconductor memory with nonvolatile storage of data, - with a first memory cell array (SF1) with volatile memory cells (SZ) and nonvolatile memory cells (WZ), - with a second memory cell array (SF2) with volatile memory cells (SZ), - with a control circuit ( 20 ) for controlling access to one of the memory cells (SZ, WZ) of the first and second memory cell arrays (SF1, SF2), - in which the control circuit ( 20 ) is designed such that during a write access to one of the volatile memory cells (SF1) of the second memory cell array (SF2) for storing at least one datum determined in the current operation of the integrated semiconductor memory in at least one of the nonvolatile memory cells (WZ) of the first memory cell array is performed on the at least one of the nonvolatile memory cells of the first memory cell array. Integrated semiconductor memory according to claim 1 - wherein the volatile memory cells (SZ) of the first and second memory cell array are each formed such that after storing a memory state in one of the volatile memory cells to maintain the stored memory state, the memory state must be refreshed at the latest after the expiration of a data retention period In which the control circuit ( 20 ) is designed such that, in order to maintain the stored memory state in one of the memory cells of the second memory cell array (SF2), it refreshes the memory state stored in one of the memory cells, thereby determining the datum in one of the nonvolatile memory cells of the one determined in the current operation of the integrated semiconductor memory first memory cell array stores. Integrated semiconductor memory according to one of Claims 1 or 2, in which a drive circuit (SA, SA) for carrying out a read or write access to one of the volatile memory cells (SZ) of the first memory cell array (SF1). 20 . 30 ), in which the non-volatile memory cells (SZ) are each designed in such a way that for carrying out a read or write access to one of the non-volatile memory cells, the drive circuit (SA, 20 . 30 ), which is provided for carrying out the read or write access to one of the volatile memory cells (SZ) of the first memory cell array, is usable. Integrated semiconductor memory according to one of claims 1 to 3, - at the sense amplifier (SA) in the first and second memory cell array are provided, each to a bit line pair (BLP) with a first and a second bit line (BLT, BLC) are connected, - in which the fleeting ones Memory cells (SZ) and the non-volatile memory cells (WZ) of the first memory cell array (SF1) are each connected to a bit line pair are, - at the fleeting ones Memory cells (SZ) and the non-volatile memory cells (WZ) are each designed such that when reading a potential difference between the first and the second bit line of the bit line pair (BLP) to which they are respectively connected, - in which the sense amplifiers (SA) are each designed such that they when reading a the volatile one Memory cells (SZ) and one of the non-volatile memory cells (WZ) each the potential difference between the first and second bit line of the bit line pair to which they are respectively connected, evaluate and depending from the evaluated potential difference a date (D) with a first or second level. Integrated semiconductor memory according to one of claims 1 to 4, - with first of the nonvolatile memory cells (WZa), - second of the nonvolatile memory cells (WZb), - in which the control circuit ( 20 ) is designed such that it evaluates the memory state of the first of the non-volatile memory cells (WZa), - in which the control circuit ( 20 ) is designed such that, depending on the memory state of the first of the nonvolatile memory cells (WZa), the datum determined in the current operation of the integrated semiconductor memory is stored in the second of the nonvolatile memory cells (WZb) with an operating parameter identifier, on the basis of which this is the current operation of the integrated semiconductor memory can be distinguished from other data determined in the current operation of the integrated semiconductor memory. Integrated semiconductor memory according to Claim 5, in which the control circuit ( 20 ) is designed such that it interrupts the storage of the date determined in the current operation of the integrated semiconductor memory in one of the second of the non-volatile memory cells (WZb) as a function of the memory state of the first of the nonvolatile memory cells (WZa). Integrated semiconductor memory according to one of Claims 5 or 6, in which the control circuit ( 20 ) is designed such that it accesses the second of the non-volatile memory cells (WZb) in read-only fashion as a function of the memory state of the first of the nonvolatile memory cells (WZa). Integrated semiconductor memory according to one of Claims 5 to 7, in which the control circuit ( 20 ) is designed such that, depending on the memory state of the first of the nonvolatile memory cells (WZa), the data determined in the current operation of the integrated semiconductor memory are stored in bitwise, bytewise or wordwise manner in the second of the nonvolatile memory cells (WZb). Integrated semiconductor memory according to one of Claims 5 to 8, in which the control circuit ( 20 ) is configured such that it assigns the second of the nonvolatile memory cells (WZb) different memory areas depending on the memory state of the first of the nonvolatile memory cells (WZa) and in a first of the different memory areas a first in the current loading operation of the integrated semiconductor memory determined date and stores in a second of the different memory areas a second date determined in the current operation of the integrated semiconductor memory. Integrated semiconductor memory according to one of Claims 1 to 9, - in which the non-volatile memory cells (WZ) can be selected for read and write access via addresses (X _w , Y _w ), - in which the control circuit ( 20 ) is designed such that it determines an address position of the last-described nonvolatile memory cell (WZ) upon initial activation of the integrated semiconductor memory and stores the data determined in the current operation of the integrated semiconductor memory at the next higher address position following the address position last described. Integrated semiconductor memory according to one of Claims 1 to 10, - having a register ( 40 ) for the intermediate storage of the date determined in the current operation of the integrated semiconductor memory, - in which the control circuit ( 20 ) is designed in such a way that, when the memory state of one of the volatile memory cells (SZ) of the second memory cell array (SF2) is refreshed, the register ( 40 ) for buffering the date determined in the current operation of the integrated semiconductor memory and stores the buffered data determined in the current operation of the integrated semiconductor memory in one of the nonvolatile memory cells (WZ) of the first memory cell array (SF1). Integrated semiconductor memory according to one of Claims 1 to 11, in which the register ( 40 ) is designed for latching the date determined in the current operation of the integrated semiconductor memory date as a register for storing an operating temperature of the integrated semiconductor memory. Integrated semiconductor memory according to one of Claims 1 to 12, in which the control circuit ( 20 ) is designed such that it changes the storage state of the nonvolatile memory cells (WZ) of the first memory cell array (SF1) as a function of the operating time of the integrated semiconductor memory. Integrated semiconductor memory according to one of claims 1 to 13, in which the non-volatile memory cells (WZ) each as a single irreversible programmable devices are formed. Integrated semiconductor memory according to one of claims 1 to 14, in which the non-volatile memory cells each formed as an electrically programmable fuse or antifuse are. Integrated semiconductor memory according to one of claims 1 to 15, in which the nonvolatile memory cells (WZ) comprise at least one controllable resistor (SR). Integrated semiconductor memory according to one of claims 1 to 16, in which the volatile Memory cells each as memory cells (SZ) with random access are formed. Method for operating an integrated semiconductor memory, comprising the following steps: - Provide an integrated Semiconductor memory with a first memory cell array (SF1) with nonvolatile Memory cells (WZ) and volatile Memory cells (SZ) and a second memory cell array (SF2) with volatile Memory cells (SZ), in which the non-volatile memory cells (WZ) first non-volatile Memory cells (WZa) and second non-volatile memory cells (WZb) comprising in the first non-volatile memory cells (WZa) an information about the configuration of the second non-volatile Memory cells (WZb) is stored, - Evaluation of memory states of first non-volatile Memory cells (WZa), - below Determining an address position of a last described second nonvolatile Memory cell (WZb) in the first memory cell array (SF1), - below Choose one to the address position of the second non-volatile memory cell described last following next higher Adresspostion, - below Storing one in the current operation of the integrated semiconductor memory determined date in a second non-volatile memory cell (WZb) of the first memory cell array (SF1), which can be addressed via the selected next higher address position is in a configuration depending on the evaluated one Memory state of the first non-volatile memory cells (WZa), if one of the volatile Memory cells (SZ) of the second memory cell array (SF2) refreshed becomes. Method for operating an integrated semiconductor memory according to claim 18, comprising the following step: Putting one Bits in the first non-volatile Memory cells (WZa0) for storing the current operation of the integrated semiconductor memory detected date in the second nonvolatile Memory cells (WZb) with a Betriebsparameterkennung, based This is the case in the current operation of the integrated semiconductor memory determined date of others in the current operation of the integrated Semiconductor memory determined data can distinguish. A method of operating a semiconductor integrated memory according to one of claims 18 or 19, comprising the step of: setting a bit in the first nonvolatile memory cells (WZa4) to configure the second nonvolatile memory cells (WZb) for one Read-only access. Method for operating an integrated semiconductor memory according to one of the claims 18 to 20, comprising the following step: Set a bit in the first non-volatile Memory cells (WZa5) to configure the second non-volatile Memory cells (WZb) for a bitwise, bytewise or wordwise storage of the in the current Operation of the integrated semiconductor memory determined date. Method for operating an integrated semiconductor memory according to one of the claims 18 to 21, comprising the following step: Set a bit sequence in the first non-volatile memory cells (WZa8, ..., WZa14) for subdivision of the second nonvolatile Memory cells (WZ) in at least a first memory area for Storage of a first in the current operation of the integrated semiconductor memory determined date and in at least a second memory area to store a second in the current operation of the integrated Semiconductor memory determined date. Method for operating an integrated semiconductor memory according to one of Claims 18 to 22, comprising the following step: reading the stored data determined in the current operation of the integrated semiconductor memory from the one of the second nonvolatile memory cells (WZb) by setting a bit in a register ( 21 ) of the integrated semiconductor memory. Method for operating an integrated semiconductor memory according to one of the claims 17 to 21, comprising the following steps: - operate the integrated semiconductor memory in a test mode, - Readout each of the first and second nonvolatile memory cells (Wza, WZb) in test mode by applying a control signal (TM) to the integrated semiconductor memory. Method for operating an integrated semiconductor memory according to one of Claims 18 to 24, comprising the following steps: - Providing an integrated semiconductor memory with a counting unit ( 60 ) for detecting an operating time of the integrated semiconductor memory, - incrementing the counting unit ( 60 ) for detecting the operating time of the integrated semiconductor memory at a defined time interval during the operation of the integrated semiconductor memory, - after the counting unit has been incremented ( 60 ) each storing a first logic state in one of the second nonvolatile memory cells, wherein the one of the second nonvolatile memory cells with respect to one of the second nonvolatile memory cells, which has been described last with the first logical state, is addressable via a next higher address.