DE102004044815A1 - Data processing device with clock recovery from different sources - Google Patents

Data processing device with clock recovery from different sources

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Publication number
DE102004044815A1
DE102004044815A1 DE200410044815 DE102004044815A DE102004044815A1 DE 102004044815 A1 DE102004044815 A1 DE 102004044815A1 DE 200410044815 DE200410044815 DE 200410044815 DE 102004044815 A DE102004044815 A DE 102004044815A DE 102004044815 A1 DE102004044815 A1 DE 102004044815A1
Authority
DE
Germany
Prior art keywords
data stream
receive data
characterized
unit
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE200410044815
Other languages
German (de)
Inventor
Eberhard Boehl
Reiner Schnitzer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE200410044815 priority Critical patent/DE102004044815A1/en
Publication of DE102004044815A1 publication Critical patent/DE102004044815A1/en
Application status is Withdrawn legal-status Critical

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/22Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • H04L7/0083Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0004Initialisation of the receiver
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033Correction by delay
    • H04L7/0041Delay of data signal

Abstract

The invention provides a data processing device (100) having a first receive data input unit (103) for inputting a first receive data stream (101) into the data processing device (100), at least one second receive data input unit (203) for inputting at least one second receive data stream (201). and clock recovery means (301) for recovering a clock signal (302) from the first receive data stream (101) and / or the at least one second receive data stream (201), wherein a controller (316) controls the clock recovery means (301) in response to either the first receive data stream (101) or one of the at least one second receive data streams (201) and a delay unit (308) delays the at least one second receive data stream (201) from the first receive data stream (101) such that the first receive data stream (101) is connected to the at least one second receive data stream (101) Receive data stream (201) sy is nchronisiert.

Description

  • The The present invention relates to a data processing apparatus. which is designed to be a clock signal from different sources recover. In particular, the present invention relates to a data processing apparatus with a clock recovery device based on a phase-locked loop (PLL), the information from a first receive data stream and at least receives a second receive data stream, wherein between two receive data streams after Need can be switched.
  • Specific The present invention relates to a data processing apparatus with a first reception data input unit for inputting a first one Receive data stream in the data processing device, at least a second receive data input unit for inputting at least one second receive data stream in the data processing device and a clock recovery device for recovery a clock signal from the first receive data stream and / or the at least one second receive data stream.
  • Clock recovery facilities become common connected to a data source and gain a data source own clock back. Usually become such clock recovery facilities operated with phase locked loops (PLL = Phase Locked Loop).
  • in this connection the clock is recovered, with which the relevant data streams were sent. For safety-critical Applications have duplicate networks. For security reasons for such Duplicated networks used different timing recovery devices. A data transfer is then done by means of two separate systems that share their data change.
  • Data processing systems, the multiple data streams can process be driven by the same clock signal. Since then the at least two streams be processed by a common clock signal, and there this Clock signal by means of a clock recovery device with phase locked loop is recovered from the data streams is it is necessary that the clock signal is still available or can be recovered if one of the at least two streams due to an error in the data system fails.
  • to solution this problem put conventional Data processing systems switching devices which ensure that in case of failure of a data stream clock recovery by means of the clock recovery device is shifted to the at least one second data stream. In disadvantageous However, there is a difference between the first data stream and the at least one a data stream generally a phase shift such a settling time is required when the clock recovery device recovers and synchronizes a clock signal from another data stream. Such settling times can in the order of magnitude from 10 to 20 milliseconds (ms), with such a transient time for safety critical Applications is intolerable.
  • Especially for X-by-wire systems such clock recovery devices can be for safety reasons do not use.
  • It It is therefore an object of the present invention to provide a data processing device to create which on different data streams at low Settling times can be synchronized.
  • These The object is achieved by a Data processing device having the features of the patent claim 1 solved.
  • Further The object is achieved by a specified in claim 8 data processing method solved.
  • Further Embodiments of the invention will become apparent from the dependent claims.
  • One essential idea of the invention is an intervening different data streams, with which the data processing device is charged, existing phase shift before any necessary switching the clock recovery device provided in the data processing device compensate.
  • One Essence of the invention is a delay signal, a temporal Delay between a first receive data stream and at least a second receive data stream represents in advance, i. before a failure of one of the two data streams to determine and store in a storage unit.
  • Thus, there is the advantage that when one of the two receive data streams fails, a switching of a clock recovery between the data streams with negligible transient time can be done.
  • According to a general aspect, the data processing device according to the invention for processing at least two data streams substantially comprises:
    • a) a first reception data input unit for inputting a first reception data stream into the data processing apparatus;
    • b) at least one second receive data input unit for inputting at least one second receive data stream into the data processing device; and
    • c) a clock recovery device for recovering a clock signal from the first receive data stream and / or the at least one second receive data stream, wherein a control device for controlling the clock recovery device in response to either the first receive data stream or one of the at least one second receive data streams and a delay unit for delaying the at least one second receive data stream relative to the first receive data stream are provided, such that the first receive data stream is synchronized with the at least one second receive data stream.
  • Furthermore, the method according to the invention for processing data and for clock recovery in a data processing device essentially has the following steps:
    • a) inputting a first receive data stream into the data processing device by means of a first receive data input unit;
    • b) inputting at least one second received data stream into the data processing device by means of at least one second received data input unit; and
    • c) recovering a clock signal from the first receive data stream and / or the at least one second receive data stream by means of a clock recovery device, wherein the clock recovery device is controlled in dependence on either the first receive data stream or one of the at least one second receive data streams by means of a control device, and the at least one second receive data stream is delayed relative to the first receive data stream by means of a delay unit such that the first receive data stream is synchronized with the at least one second receive data stream.
  • In the dependent claims find advantageous developments and improvements of respective subject of the invention.
  • According to one preferred embodiment of the present invention comprises the Clock recovery device a Phase Locked Loop (PLL), which is a recovered clock signal synchronized to the clock of one of the data processing device supplied data streams.
  • One Another aspect of the present invention is directed to a determination unit for determining a time shift between the first Receive data stream and the at least one second receive data stream directed. The determination of a time shift provides advantageously a delay signal, with which one of the supplied Receive data streams such delayed can be that the data streams supplied to the data processing device synchronized are. Thus, the clock recovery device advantageously quickly between a synchronization by use different receive data streams.
  • In expedient manner is the storage unit for storing at least one delay value provided, wherein the at least one second receive data stream according to the delay value delayed becomes.
  • Yet Another aspect of the present invention is a calibration switching unit directed, with which of a normal mode, in which the clock signal from the first receive data stream or the at least one second Receive data stream, in a calibration mode, in which by means of the determination unit a delay value for the at least one second receive data stream is determined, is switched.
  • It is advantageous to the delay unit for Providing a variable delay of the at least one second receive data stream relative to the first receive data stream form in series connected inverter units. Preferably if the number of inverter units connected in series can be varied, such that a variable delay adjusted by means of the delay unit can be. The size of the variable delay will be in an appropriate manner dependent on from the delay value stored in the storage unit set.
  • According to one more Another preferred embodiment of the present invention can a generated clock signal obtained by means of the clock recovery device is alternately with the first receive data stream and the at least a second receive data stream are synchronized.
  • Furthermore, it is advantageous that a first Sen dedatenstrom is provided to a first transmission data output unit of the data processing device in response to the first receive data stream. Similarly, a second transmission data stream is provided to a second transmission data output unit of the data processing apparatus in response to the second reception data stream.
  • In expedient manner can the second receive data stream and the second transmit data stream multiple times to be provided.
  • It is advantageous if the first receive data stream from a reference data stream for the at least a second receive data stream is used. In the calibration mode the received second receive data stream is unchanged a second output unit of the data processing device for Output forwarded as a second transmit stream.
  • Consequently the data processing device according to the invention a switch between a first receive data stream and at least a second receive data stream to a fast and efficient Manner provide such that at a clock recovery the clock signal by means of a clock recovery device none Settling times or time delays occur which data processing in the data processing device would prevent by a not exactly synchronized clock signal.
  • embodiments The invention is illustrated in the drawings and in the following Description closer explained.
  • DRAWINGS
  • In show the drawings:
  • 1 an overall block diagram of the data processing device according to the invention to illustrate the principles of the invention;
  • 2 a detailed block diagram of the data processing device according to a preferred embodiment of the present invention, wherein the operation of the data processing device is illustrated in a calibration mode; and
  • 3 a detailed block diagram of the data processing device according to a preferred embodiment of the present invention, wherein an operation of the data processing device in a normal mode, that is shown in a working phase.
  • In the same reference numerals designate the same or functionally identical Components or steps.
  • DESCRIPTION THE EMBODIMENTS
  • 1 shows an overall block diagram of a data processing device according to a preferred embodiment of the present invention. As in 1 is shown, the data processing device 100 with a first receive data stream 101 which of a first receive data input unit 103 the data processing device 100 is supplied. At least one second receive data stream 201 becomes a second reception data input unit 203 the data processing device 100 fed.
  • It should be noted that although this is in the 1 not illustrated, multiple receive data streams can be supplied. In general, the data processing device 100 at least one first receive data stream 101 and at least a second receive data stream 201 fed. In the in 1 illustrated example, the first receive data stream is used 101 as a reference data stream for the second receive data stream 201 , In a data processing system, multiple (at least two) computing devices 100 to be able to switch in succession, the respective first and second receive data streams must 101 . 201 also as first or second transmission data streams 102 respectively. 202 be dispensable.
  • For this purpose, in the data processing apparatus, a first transmission data output unit 104 for the output of the first transmission data stream 102 during a second transmission data output unit 204 for the output of the second transmission data stream 202 is provided.
  • The first receive data stream 101 becomes a synchronization unit 305 supplied, which, in response to a supplied clock signal 302 ensures that the first receive data stream 101 according to the supplied clock signal 302 to the first transmission data output unit 104 as the first transmission data stream 102 is supplied.
  • In the same way, the second receive data stream (at least one second receive data stream 201 is available) 201 a synchronization unit 305 is supplied from which via the second transmission data output unit 204 the second transmission data stream 202 is issued. In the signal path of the second transmission data stream 201 is further a delay unit 308 which is designed, the second receive data stream 201 by a predetermined amount, ie by one of the delay units 308 supplied delay value 309 to delay. The delay value 309 is in a storage unit 311 stored and read out if necessary from this. Like such a delay value 309 determined and in the storage unit 311 is stored below with reference to 2 be explained.
  • From a clock recovery device 301 become clock signals 302 supplied to the different units. Thus, the clock signal becomes 302 the respective synchronization units 305 in the signal path of the first receive data stream 101 and the second receive data stream 201 are arranged, supplied. Furthermore, the clock signal 302 via a clock signal output 303 to units outside the data processing device 100 be issued.
  • The clock recovery device 301 is from one of a control device 316 output control signal 318 controlled. That is, a synchronization to one of the two receive data streams 101 respectively. 201 is by the control signal 318 causes.
  • The control device 316 has a switching unit 313 and an activity detection unit 314 on. Both the activity detection unit 314 as well as the switching unit 313 become the two receive data streams 101 respectively. 201 fed. In a normal mode, the below with reference to 3 described, it allows the switching unit 313 the control device 316 in that it is determined to which receive data stream, ie the first receive data stream 101 or the second receive data stream 201 , the clock signal to be recovered 302 is synchronized. In a normal mode of operation, the clock recovery device is 301 first to the first receive data stream 101 synchronized. The activity detection unit 314 detects an activity in the first receive data stream 101 and in the delayed, second receive data stream 201 ' ,
  • If one of the two receive data streams falls 101 . 201 from, so sends the activity detection unit 314 a corresponding selection signal 319 to the switching unit 313 , The switching unit 313 can now immediately, ie switch without settling time in case of failure of a receive data stream to the other receive data stream. The two receive data streams 101 and 201 are by virtue of the delay unit 308 synchronized to each other, so that the clock recovery device 301 a corresponding control signal 318 can be supplied for synchronization with a data stream without a time delay.
  • Thus, a phase locked loop of the clock recovery device operates 301 even in case of failure of a receive data stream, without a corresponding settling time (settling period) is required.
  • 2 shows the in 1 illustrated data processing device switched into a calibration mode. In the calibration mode, as described above with reference to FIG 1 described, the delay value 309 determines which of the delay units 308 for delaying the at least one second receive data stream 201 must be supplied. As in 2 illustrates, the first receive data stream 101 via the first receive data input unit 103 a synchronization unit 305 fed, which via their clock signal input 304 the clock signal 302 receives. It should be noted that this synchronization unit 305 can be optionally provided.
  • Subsequently, the already synchronized first receive data stream 101 a multiplexing unit 306 which allows both the first receive data stream 101 as well as a first internal data stream 307 to a second synchronization unit 305 which can be forwarded via their respective clock signal input 304 also the clock signal 302 receives. Finally, the first receive data stream 101 as a first transmission stream 102 from the second synchronization unit 305 via the first transmission data output unit 104 output. The clock recovery device 301 receives a synchronization signal 312 which is derived from the first receive data stream.
  • The following is a phase shift between the second receive data stream 201 and the first receive data stream 101 determined. For this purpose, a determination unit 310 that from the clock recovery device 301 provided clock signal 302 fed. Further, the determination unit becomes 310 by the delay unit 308 (with reference to above 1 described) delayed second receive data stream 201 ' fed.
  • The determination unit 310 now determines a time delay between the clock signal 302 and the second delayed receive data stream 201 ' and sets a delay value 309 , which is the delay unit 308 is supplied, such that a time delay between the clock signal 302 and the delayed second receive data stream 201 ' becomes zero. In this Calibration mode becomes the delay value 309 measured over a longer period and it is examined whether the delay value for delaying the second receive data stream 201 to the delayed second receive data stream 201 ' to maintain, remains stable. Does the delay value change? 309 over a longer period of time, so this is the delay value 309 in a storage unit 311 stored, such that this delay value 309 at any time for delaying the supplied second receive data stream 201 can be used. It should be noted that, depending on an application, different delay values 309 in the storage unit 311 can be stored. During the calibration phase is a calibration switch unit 317 switched such that the second receive data stream 201 unchanged via a synchronization unit 305 which is the clock signal 302 via its clock signal input 304 is supplied to the second transmission data output unit 204 is issued.
  • By the calibration mode provided by the preferred embodiment of the present invention, it is thus possible by a data processing device 100 directed first and second receive data streams 101 respectively. 201 in such a way that a synchronization of a clock recovery device by any of the data processing device 100 supplied data streams 101 . 201 can be provided. In particular, it is possible with the above with reference to 1 described switching unit 313 a switchover of the synchronization between the two receive data streams 101 . 201 without requiring a transient period. Thus, clock recovery is fast and efficient from one of the two receive data streams 101 . 201 allows.
  • 3 shows the data processing device according to the invention 100 in an overview block diagram. As in 3 is shown, the delayed second receive data stream 201 ' now no longer to the second transmission data output unit 204 via the synchronization unit 305 passed through.
  • It should be noted that in the figures, the same reference numerals designate the same or functionally identical components or steps, so that in 3 already described components or steps in the explanation are omitted in order to avoid an overlapping description.
  • The calibration switch unit 317 is in 3 switched to a normal mode, such that the second receive data stream 201 with a fixed delay value 309 by virtue of the delay unit 308 is delayed. This delayed second receive data stream 201 ' is via a synchronization unit 305 , which via a clock signal input 304 the clock signal 302 is supplied, is synchronized. It should be noted that this first synchronization unit 305 in the signal path of the second receive data stream 201 . 201 ' is optional.
  • In a similar manner as above with reference to 2 for the first receive data stream 101 also described is the delayed second receive data stream 201 ' a multiplexing unit 306 which provides the possibility of a second internal data stream 315 or the delayed second receive data stream 201 ' to a second synchronization unit 305 which is the clock signal 302 via an associated clock signal input 304 is supplied to the second transmission data output unit 204 issue.
  • By the control device according to the invention 316 which the switching unit 313 (please refer 1 ), it is now possible for the clock recovery device 301 either synchronization information (synchronization signal 312 ), that of the first receive data stream 101 is derived, or the clock recovery device 301 a synchronization signal 312 ' that of the delayed second receive data stream 201 ' is derived, supply. Now falls one of the two receive data streams 101 respectively. 201 off, so allows the controller 316 a rapid switching between the synchronization information received from the first receive data stream 101 and the synchronization information supplied by the second receive data stream 201 is supplied.
  • According to the preferred embodiment of the present invention, in a network having a plurality of receive data streams of the same fundamental frequency, first a receive data stream is selected with which the phase locked loop of a clock recovery device 301 is synchronized. This receive data stream is referred to as a reference data stream. After the phase locked loop of the clock recovery device 301 has settled, ie when a lock signal has been received and the data of the data stream are recognized as error-free. become the data of the at least one second receive data stream 201 received and evaluated. A determination of whether the data is recognized without errors is determined, for example, by means of a code, a frame structure and the number of bytes per frame.
  • Due to the existing phase shift between the two receive data streams that of the at least one second receive data stream 201 received data may not be error free. The data of the second receive data stream 201 are now using the delay unit 308 delayed from a fixed initial value, such that the phase positions of the two receive data streams are adjusted until the data of the second receive data stream 201 can be received error-free and reliable with the generated from the reference data stream clock.
  • In the calibration mode (referred to above with reference to FIG 2 described) such a network-dependent delay is determined. The data of the second receive data stream during the calibration mode by means of the calibration switching unit 317 unchanged to the second transmission data output unit 204 , ie forwarded to a subsequent node. Before the first or second receive data streams 101 . 201 via the corresponding output units as transmission data streams 102 . 202 output causes synchronization in respective synchronization units 305 , respectively by the clock signal 302 be switched, that even after opening the Kalibrierschalteinheit 317 , ie after switching to a normal mode, the phase position remains unchanged. For this reason, it is possible to calibrate all the nodes simultaneously in the case of data processing devices connected in series. Thus, all nodes go into a working phase at the same time. The information for switching is transmitted as status information over the reference data stream.
  • To realize a variable delay by the delay unit 308 This is formed, for example, of a variable number of inverters.
  • Alternatively, it is possible to directly measure the phase shift between the two receive data streams and eliminate them by the delay element. A direct measurement can be implemented by conventional measuring circuits known to those skilled in the art, for example by an edge of the reference data stream starting the measuring unit and an edge of the second receiving data stream 201 the measuring unit switches off. Thus, the measuring unit generates a voltage proportional to a time difference (phase difference) between the two reception data streams 101 . 201 increases. With such a voltage, the delay element can be 308 to control or switch, wherein the delay value is given voltage-dependent.
  • Once in the calibration mode for a definable longer period of time also from the second receive data stream 201 Stable data is received, the calibration value, ie the delay value 309 for the delay unit 308 saved. The storage or the indication of the number of linked inverters is easily possible in a register. In the alternative case, the voltage value for the delay element must be stored. This can be realized by providing a digital representation of this voltage value in a register, and providing a digital-to-analog converter to obtain the required analog voltage value for the delay unit 308 to create.
  • The one in the storage unit 311 stored delay value 309 retains its validity until the system is completed by the calibration unit 317 again switched to a calibration mode. This is necessary, for example, when the delay conditions in the network into which the data processing device 100 is involved, change. Such changes may result, for example, from power on or off of subscribers (ie, data processing devices), reconfigurations, and errors.
  • Furthermore, it is possible that in the clock recovery device 301 provided phase locked loop PLL in the working phase, ie in the normal mode edge information of both receive data streams 101 and 201 receives. Due to the set delay, the edge information is now received at the same time. As long as the reference data stream is received without errors, initially only the edge information of this node is evaluated.
  • If a failure of the reference data stream by, for example, the activity detection unit 314 in the control device 316 is provided (see 1 ), or is detected by codes or the frame structure, the phase locked loop switches to the edge detection of the second receive data stream 201 around. Since the processing method according to the invention in addition to the equality of the frequency now also a phase equality of the two receive data streams 101 . 201 is for the phase locked loop of the clock recovery device 301 no settling time or transient period required. Advantageously, the clock signal remains 302 when switching a synchronization from the first receive data stream 101 (Reference data stream) to the at least one second receive data stream 201 received unchanged without interference.
  • Although the present invention prevailed Hend was described with reference to preferred embodiments, it is not limited thereto, but modifiable in many ways.
  • Also the invention is not limited to the aforementioned applications limited.

Claims (19)

  1. Data processing device ( 100 ), comprising: a) a first receive data input unit ( 103 ) for inputting a first receive data stream ( 101 ) into the data processing device ( 100 ); b) at least one second received data input unit ( 203 ) for inputting at least one second received data stream ( 201 ) into the data processing device ( 100 ); and c) a clock recovery device ( 301 ) for recovering a clock signal ( 302 ) from the first receive data stream ( 101 ) and / or the at least one second receive data stream ( 201 ); characterized in that the data processing device ( 100 ) further comprises: d) a control device ( 316 ) for controlling the clock recovery device ( 301 ) depending on either the first receive data stream ( 101 ) or one of the at least one second receive data streams ( 201 ); and e) a delay unit ( 308 ) for delaying the at least one second receive data stream ( 201 ) compared to the first receive data stream ( 101 ) such that the first receive data stream ( 101 ) with the at least one second receive data stream ( 201 ) is synchronized.
  2. Apparatus according to claim 1, characterized in that the clock recovery device ( 301 ) is formed as a phase locked loop (PLL).
  3. Apparatus according to claim 1, characterized in that further comprises a determination unit ( 310 ) for determining a time shift between the first receive data stream ( 101 ) and the at least one second receive data stream ( 201 ) provided.
  4. Device according to claim 1, characterized in that a memory unit ( 31 1) for storing at least one delay value ( 309 ), wherein the at least one second receive data stream ( 201 ) according to the delay value ( 309 ) is delayed.
  5. Device according to claims 3 and 4, characterized in that a calibration switching unit ( 317 ) is provided with which of a normal mode in which the clock signal ( 302 ) from the first receive data stream ( 101 ) or the at least one second receive data stream ( 201 ) is returned to a calibration mode in which by means of the determination unit ( 310 ) a delay value ( 309 ) for the at least one second receive data stream ( 201 ), is switched.
  6. Device according to claim 1, characterized in that the delay unit ( 308 ) for providing a variable delay of the at least one second receive data stream ( 201 ) compared to the first receive data stream ( 101 ) is formed of series connected inverter units whose number is variable.
  7. Data processing system with at least two in series switched data processing devices according to claims 1 to 6th
  8. Method for data recovery with clock recovery in a data processing device ( 100 ), comprising the following steps: a) inputting a first receive data stream ( 101 ) into the data processing device ( 100 ) by means of a first reception data input unit ( 103 ); b) inputting at least one second received data stream ( 201 ) into the data processing device ( 100 ) by means of at least one second received data input unit ( 203 ); and c) recovering a clock signal ( 302 ) from the first receive data stream ( 101 ) and / or the at least one second receive data stream ( 201 ) by means of a clock recovery device ( 301 ); characterized in that the method further comprises the steps of d) controlling the clock recovery device ( 301 ) depending on either the first receive data stream ( 101 ) or one of the at least one second receive data streams ( 201 ) by means of a control device ( 316 ); and e) delaying the at least one second receive data stream ( 201 ) compared to the first receive data stream ( 101 ) by means of a delay unit ( 308 ) such that the first receive data stream ( 101 ) with the at least one second receive data stream ( 201 ) is synchronized.
  9. Method according to claim 8, characterized in that the phase of the recovered clock signal ( 302 ) by means of a in the clock recovery device ( 301 ) phase locked loop (PLL) is provided.
  10. A method according to claim 8, characterized in that a time shift between the first receive data stream ( 101 ) and the at least one second receive data stream ( 201 ) by means of a determination unit ( 310 ) is determined.
  11. Method according to claim 8, characterized in that at least one delay value ( 309 ) in a storage unit ( 311) is stored, wherein the at least one second receive data stream ( 201 ) according to the stored delay value ( 309 ) is delayed.
  12. Method according to claims 10 and 11, characterized in that by means of a calibration switching unit ( 317 ) between a normal mode in which the clock signal ( 302 ) from the first receive data stream ( 101 ) or the at least one second receive data stream ( 201 ) is returned to a calibration mode in which by means of the determination unit ( 310 ) a delay value ( 309 ) for the at least one second receive data stream ( 201 ), is switched.
  13. Method according to claim 8, characterized in that by means of the delay unit ( 308 ) a variable delay of the at least one second receive data stream ( 201 ) compared to the first receive data stream ( 101 ), wherein in series inverter units are provided, the number of which can be varied.
  14. Method according to Claim 8, characterized in that a generated clock signal ( 302 ) alternately with the first receive data stream ( 101 ) and the at least one second receive data stream ( 201 ) is synchronized.
  15. Method according to Claim 8, characterized in that a first transmission data stream ( 102 ) on a first transmission data output unit ( 104 ) of the data processing device ( 100 ) in response to the first receive data stream ( 101 ) provided.
  16. Method according to Claim 8, characterized in that a second transmission data stream ( 202 ) on a second transmission data output unit ( 204 ) of the data processing device ( 100 ) in response to the second receive data stream ( 201 ) provided.
  17. Method according to Claim 8, characterized in that the second received data stream ( 201 ) and the second transmission data stream ( 202 ) are provided multiple times.
  18. Method according to Claim 8, characterized in that the first receive data stream ( 101 ) as a reference data stream for the at least one second receive data stream ( 201 ) provided.
  19. Method according to claim 17, characterized in that in the calibration mode the received second received data stream ( 201 ) unchanged to the second transmission data output unit ( 204 ) of the data processing device ( 100 ) for output as a second transmit stream ( 202 ) is forwarded.
DE200410044815 2004-09-16 2004-09-16 Data processing device with clock recovery from different sources Withdrawn DE102004044815A1 (en)

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DE200410044815 DE102004044815A1 (en) 2004-09-16 2004-09-16 Data processing device with clock recovery from different sources
EP20050106580 EP1638243B1 (en) 2004-09-16 2005-07-18 Processing device with clock recovery from different sources
DE200550005595 DE502005005595D1 (en) 2004-09-16 2005-07-18 Data processing device with clock recovery from different sources
AT05106580T AT410852T (en) 2004-09-16 2005-07-18 Data processing device with take-back recovery from different sources
US11/229,102 US7567630B2 (en) 2004-09-16 2005-09-16 Data processing device including clock recovery from various sources

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EP1638243A2 (en) 2006-03-22
AT410852T (en) 2008-10-15
DE502005005595D1 (en) 2008-11-20
US20060067449A1 (en) 2006-03-30
EP1638243B1 (en) 2008-10-08
US7567630B2 (en) 2009-07-28
EP1638243A3 (en) 2006-07-19

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