DE102004037153B4 - Method for producing a power semiconductor device - Google Patents

Method for producing a power semiconductor device

Info

Publication number
DE102004037153B4
DE102004037153B4 DE200410037153 DE102004037153A DE102004037153B4 DE 102004037153 B4 DE102004037153 B4 DE 102004037153B4 DE 200410037153 DE200410037153 DE 200410037153 DE 102004037153 A DE102004037153 A DE 102004037153A DE 102004037153 B4 DE102004037153 B4 DE 102004037153B4
Authority
DE
Germany
Prior art keywords
region
semiconductor material
trench
material region
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE200410037153
Other languages
German (de)
Other versions
DE102004037153A1 (en
Inventor
Dr. Rüb Michael
Dr. Schmidt Gerhard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE200410037153 priority Critical patent/DE102004037153B4/en
Publication of DE102004037153A1 publication Critical patent/DE102004037153A1/en
Application granted granted Critical
Publication of DE102004037153B4 publication Critical patent/DE102004037153B4/en
Application status is Expired - Fee Related legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66136PN junction diodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout

Abstract

A method of manufacturing a power semiconductor device (1) with only a single photostructuring step, in which
a semiconductor material region (20) is formed with a central region (20Z), with an edge region (20R) and with a surface region (20a),
in the central region (20Z) of the semiconductor material region (20), a semiconductor circuit arrangement (10) on which the power semiconductor component (1) is based is formed,
an electrical edge termination region (30) provided for the semiconductor circuit arrangement (10) is formed with at least one trench (40) running in the edge region (20R) of the semiconductor material region (20), the at least one trench (40) extending from the surface region (20a) of the semiconductor material region (20) is formed extending vertically into the semiconductor material region (20),
the at least one trench (32) is lined by a passivation layer (80) produced in a conformable manner and filled by a dielectric (90),
outside of the at least one trench (32) the surface region (20a) of the semiconductor material region (20) exposed and self-aligned to the at least one trench a metallization (100) is formed, wherein the dielectric in a ...

Description

  • The present invention relates to a method of manufacturing a power semiconductor device.
  • In the fabrication of power semiconductor devices, it may be necessary to take certain measures to ensure proper electrical termination at the edges of the underlying semiconductor material region or chip with respect to the underlying semiconductor circuitry. In addition to so-called planar edge finishes, so-called vertical edge finishes using trench structures are also conceivable. Known methods for forming corresponding edge structures are characterized by a multiplicity of interlocking individual steps, wherein, in particular, the structuring measures in the edge region of the underlying chip are complex and, due to their complexity, also require a large amount of space.
  • US 2003/0047779 A1 relates to trench-gate semiconductor devices and their manufacturing methods. In an edge termination structure, a conductive layer consisting of, for example, a polysilicon gate material extends on an interlayer insulating layer over a higher doped termination region of a channel covering region. This insulating layer has a region of a trench etching mask, which preferably comprises silicon nitride, and has a greater thickness than the gate dielectric layer. A window extends through the trench etch mask at a location where a termination trench extends into the p + region. The final trench corresponds to an extension of the isolation gate trench into the p + region and accommodates an extension of the trench gate. The conductive layer is connected to the trench gate extension via the window. The lateral extent of the conductive layer terminates at an edge defined by the trench etch mask.
  • US 4,756,793 describes a method of fabricating a semiconductor device having at least a comparatively shallow and a comparatively deep trench in a semiconductor surface, while zones are implanted over the walls and / or the bottom of the trench over only a portion of the trench length. In this case, the implantation mask is formed on a filling material which fills the trench and is removed again after provision of the masking layer. The filling material is preferably made of a photoresist.
  • WO 2004/001854 A2 describes a semiconductor device with an edge structure. An edge termination region includes a plurality of trenches. Here, a conductive material as well as an insulating material fills the trenches and surface implantation areas are formed on both sides of the trenches. A conductive bridge connects the surface implantation areas to achieve balance in reverse operation.
  • The invention has for its object to provide a method for producing a power semiconductor device, in which a necessarily be provided edge termination structure can be produced in a particularly simple manner with a very small footprint.
  • The object is achieved in a method for producing a power semiconductor device according to the features of independent claim 1. Advantageous developments of the method according to the invention for producing a semiconductor device are the subject of the dependent subclaims.
  • Thus, a core idea of the present invention is to form the trench structure extending from the surface region of the semiconductor material region vertically into the semiconductor material region in the case of the embodiment of the power semiconductor component, this taking place overall as part of a single and single photostructuring step, and structuring and using a single mask.
  • The only mask can be a hard mask.
  • It is preferably provided that the semiconductor material region is formed with a first region (n + ) highly doped by a first conductivity type (n + ) and remote from the surface region of the semiconductor material region, this being provided in particular as a substrate. Furthermore, it is advantageous if the semiconductor material region is formed with a second region, which is less highly doped and of the first conductivity type (n) and faces in the surface region of the semiconductor material region, in particular as an epitaxial region.
  • In the method according to the invention is used as a semiconductor device z. B. a power diode is formed. Conceivable, however, are other components or their combination.
  • Alternatively or additionally, it is provided that the power semiconductor component and its underlying semiconductor circuit arrangement is formed completely or partially as an arrangement and parallel connection of identical semiconductor elements in a cell array.
  • It is of particular advantage if after step (b) of forming the Semiconductor circuit arrangement or a part thereof in the surface region of the semiconductor material region in one step or process (e) of a second conductivity type (p) highly doped (p + ) third region ( 20-3 ) is formed, in particular with p + doping and / or in particular by implantation of the side facing the surface region of the semiconductor material region, in particular in the epitaxial region inside.
  • Thereby, as a preparation for the step (e) of forming the third region doped with the second conductivity type (p) on the surface region of the semiconductor material region, a scattering layer and in particular a scattering oxide having a surface region can be formed.
  • In the latter variants, it is conceivable that a hard mask material is applied to the existing structure or in its edge region on the side facing the surface region of the semiconductor material region and in particular on the surface region of the scattering layer and in a single phototechnical structuring step to form a hard mask with recesses at least for is patterned trainee trench structure, which is exposed through the recesses, the underlying structure to the surface region of the semiconductor material region or to the surface region of the scattering layer.
  • In this case, provision may be made for a trench or a plurality of trenches for the trench structure to be formed over the recesses or over part of the recesses in the edge region of the semiconductor material region, in particular by an etching step.
  • The trench or the trenches can be formed running laterally in the edge region of the semiconductor material region and / or parallel to the edge of the edge region of the semiconductor material region.
  • It can be provided that the trench or the trenches in the edge region of the semiconductor material region are formed substantially vertically extending from the surface region of the semiconductor material region into the semiconductor material region.
  • Furthermore, it can be provided that the trench or the trenches are formed with an oxide layer, in particular by an oxidative conversion process in the respective wall / bottom area of the respective trenches.
  • Alternatively or additionally, it is provided that a lateral implantation in the wall region of the trench or trenches is carried out, in particular using boron and / or in particular with a subsequent activation of the implanted material.
  • As a further alternative or as a further addition, provision may be made for a passivation layer having a surface area to be produced on the structure obtained, in particular in a conformable manner, in particular the trench or trenches being lined.
  • In this case, it is conceivable that a dielectric having a surface area is formed on the resulting structure such that the trench or the trenches are filled thereby.
  • It is also conceivable for the resulting structure to be etched back in such a way that the passivation layer and the dielectric are removed down to the surface region of the semiconductor material region or down to the surface region of the hard mask, in particular outside the trench or trenches.
  • Then z. B. from the structure obtained, the hard mask and in particular the scattering layer optionally provided, so that in particular the surface region of the semiconductor material region and further in particular of the second conductivity type doped third region are exposed.
  • In this case, it is advantageous if a metallization is formed on the structure obtained and thus adjusted outside the trench or outside the trenches, in particular by a process of growth. These and other aspects of the present invention are further explained below:
    In particular, the invention relates to a method of manufacturing a high voltage or high voltage diode with a self-aligned single mask process.
  • To ensure a sufficiently high blocking capability in high-voltage semiconductor devices made of Si or SiC, it is necessary to take appropriate measures for the edge termination at the chip end. In modern circuit breakers such as IGBTs, SIPMOS power transistors, MOS-controlled compensation components (COOLMOS) and the associated high-voltage diodes, the electric field strength between the active area and the sawing edge must be completely reduced, without resulting in field elevation at the chip edge.
  • The higher the blocking capability of the device, the more complex in general the constructions for the edge termination and the higher the requirements for the passivation layers.
  • With the IGBT product series and the associated freewheeling diodes, reverse voltages of 600 V to 6.5 kV are required today. The edge termination is usually performed planar. The edge construction is intended to ensure that the equipotential lines are guided from the interior of the component to the surface such that their curvature and density does not lead to a premature onset of avalanche generation in the silicon or to a dielectric breakdown in the passivation layers and the blocking capability of the component is far drops below the value of volume breakdown voltage.
  • Other critical points are steps and edges in the topology of the boundary construction. At these points, peak field strengths of several MV / cm can be formed on the surface during dynamic operation, which place extremely high demands on the robustness of the protective layers for surface passivation. If these are insufficiently met, there is a risk that the component will fail after a certain number of switching cycles.
  • In order to ensure sufficient blocking capability, a number of edge finishing techniques are in use today, all with the aim of attenuating the surface electric field and increasing the tolerance to surface charges. As a result, the potential conditions on the semiconductor surface should be kept stable over time.
  • Conceptually, a distinction can be made between the so-called mesa and the planar edge termination. While in the first concept a contouring of the semiconductor edge in the form of oblique cuts or trenches is made by the blocking pn junctions, the degradation of the field strength in the outer space must be accomplished by suitable mask techniques in the planarity. For this purpose, either the lateral course of the doping is adjusted accordingly or so-called field plate constructions are used, via which the surface field strength is degraded in a suitable manner in the insulator layer located between them and the semiconductor surface.
  • However, optimizing a high blocking margin in terms of blocking capability and blocking stability requires a significant amount of chip area. Typically, the edge width should be set to two to three times the base thickness. The large footprint is due to the fact that the equipotential lines largely experience their curvature in the silicon in order to be led out of the component to the surface. A curvature of the equipotential lines in the silicon is associated with an increase in the electric field. If this exceeds the critical value, avalanche breakdown occurs. To keep the radius of curvature sufficiently low, for example, requires a field plate construction with pad oxide for a 600 V device edge width of about 200 .mu.m-250 .mu.m, with a blocking capacity of 6.5 kV, an edge width of more than 2000 microns already required.
  • A further disadvantage associated with the realization of a planar high-volume edge is the high optimization effort and the high process complexity. The latter is particularly noticeable in high-voltage diodes, since the basic structure in the active part of the component is relatively simple and would require only a few process steps. The realization of the described edge construction with successive oxide stages and polysilicon field plates requires, for example, a doubling of the number of photo planes and thus a corresponding increase in wafer costs, for example in the case of a 6.5 kV diode.
  • Compared to planar concepts, the concept of a mesa edge termination has the advantage that the degradation of the field strength is (at least partially) moved to the vertical depth of the component and the edge requirement correspondingly lower.
  • The modern trench cell concepts, for example in the new IGBT generations, meanwhile provide technologies that make the verticalization of the edge termination feasible.
  • In the present invention disclosure is now proposed to make a verticalization of the edge termination in high-voltage diodes using a self-aligning process sequence so that only a single photo level is required. As a result, the disadvantages of the high edge requirement and the high process complexity are reduced to a minimum.
  • The manufacturing principle will be described below with reference to an embodiment below.
  • An essential aspect of the invention is the provision of a production method for a high-voltage diode structure with trench edge by using only a single photo plane.
  • The manufacturing principle is described below with reference to 2A to 2H illustrated.
  • By way of example, a highly doped Si substrate with an epitaxial layer into which the active component is incorporated is carried out as the base material. When using a suitable Thin-wafer technology can also eliminate the stabilizing substrate material and introduce the backside n.sup. + Emitter at the beginning via ion implantation or from a dopant source via diffusion. For thinning the wafer, grinding methods, spin etching or polishing methods such as CMP are suitable.
  • After growth of a scattering oxide (optional), the p + emitter is implanted and driven. Subsequently, z. B. deposited in a CVD plasma deposition of TEOS (tetraethylene Oxisilan) about 2 microns thick, undoped silicon oxide and compressed in the oven at about 850 ° C. This hard mask is structured using photographic technology. Oxide-free areas are used to etch oxide windows either by a wet-chemical method or by a plasma process, and then the photoresist is removed. The structured hard mask etches the trenches either via an anisotropic wet-chemical etching (eg with KOH) or again by plasma etching. In the case of thin wafer processing, prior to the trench etch, bonding to a substrate that provides the required mechanical support to the entire system is indispensable.
  • The trench etching can optionally be supplemented by a subsequent oxidation step (sacrificial oxides), which possibly eliminates the damage on the crystal surface. (When using etching techniques that produce a very rough trench sidewall, such as the so-called Bosch process, it may be necessary to take other sidewall smoothing measures, such as sacrificial oxidation, or alternatively, or in combination with one isotropic overetching of the surface)
  • The sacrificial oxide layer can simultaneously serve as scattering oxide for (optional) boron sidewall implantation and is expediently subsequently removed again. An additional lateral Borimplantation is required in particular for Trenchtaperwinkel φ, which are significantly smaller than 90 °. This will be explained in more detail below. After boron activation, a passivation layer is deposited. This can for example consist of thermal oxide (which may be grown in combination with the furnace boron activation process) or of other dielectrics such as nitride or plasma oxide. Semi-insulating layers of amorphous or polycrystalline materials can also be used here. To avoid glow discharges in the ambient atmosphere in the sawn chip, the trench is then connected to a dielectric with high dielectric strength such. B. filled with polyimide. Alternatively, it may be advantageous to deposit a dielectric such as polyimide only on the trench sidewall in sufficient thickness. After a Recessätzung of polyimide and passivation layer in a corresponding plasma etching process, the TEOS hardmask is exposed again. This can simultaneously serve as protection against the etching of the anode and as etch stop during the Recessätzung. Thereafter, this is most conveniently removed by wet etching by an HF etch. At the now exposed anode, the front side metallization can be grown by electroplating without the aid of a further photo technique. Of course, another photo step is conceivable in the case of a full-surface coating by vapor deposition or sputtering. For adjustment here the trench edges or specially mitgeätzte auxiliary structures can be used. Finally, the back metallization can in any case be vapor-deposited or sputtered over the entire surface.
  • The heavy metal diffusion usually required for adjusting the dynamic properties can be expediently carried out after the boron drive or, alternatively, electron irradiation can be carried out. This measure for carrier life adjustment leads u. a. also to increase the reverse current in the diode. This is helpful in the case of galvanic deposition of the anode metallization, since the current thereby flows in the reverse direction over the pn junction. In addition, an increase in the temperature of the electroplating bath to, for example, 80 ° C.-90 ° C., helps to further increase the reverse current. If these values reach about 0.1 mA, about 75 minutes are required for the deposition of a 1 μm thick Cu metallization.
  • The mentioned sidewall implantation with acceptors is rather of minor importance for nearly vertical trenches. This shows the in 3 illustrated simulation for a high-voltage diode with vertical trench without lateral implantation.
  • Specifically, the simulation was based on the following structure: The vertical diffusion depth of the p + region (anode) is 6 μm and the edge concentration is 5 × 10 18 cm -3 . For the base material, silicon having a resistivity of 350 Ω · cm and a thickness of 375 μm was set. For the backside n + cathode region, a dose of 1 × 10 16 cm -2 and a junction depth of 12 μm were assumed. This corresponds, for example, to a structure that is dimensioned for use with a nominal voltage of 3.3 kV. Furthermore, the relative dielectric constant was set to ε = 4 in the outer space. The most common dielectrics such as SiO 2 and polyimide have values of this order of magnitude.
  • The simulation was performed with the program BREAKDOWN.
  • While with a planar edge termination the equipotential lines are always curved to the surface and therefore the volume blocking capability can never be realized to 100%, lateral removal of the equipotential lines without appreciable curvature makes it possible to achieve an optimum between blocking capability and space requirement. For receiving the electric field strength in the outer space, only the lateral connection of a sufficiently wide zone of dielectric material is required. In the case shown, the blocking voltage without additional implantation despite the extreme punch-through dimensioning is still 85 of the maximum blocking voltage of about 5100 V in volume and is therefore comparable to the situation as a planarity.
  • 4 indicates the situation at a taper angle of 54 ° and shows the blocking voltage normalized to the volume blocking capability as a function of the sidewall implantation dose for two different basic structures. Without additional implantation, this drops to 40% in the already described 3.3 kV diode under otherwise identical conditions.
  • A lateral acceptor implantation has the effect that the field strength peak occurring at the p + n junction is attenuated and that as a result the blocking voltage can increase in volume up to the maximum blocking capability. However, if the dose is too high, the forced curvature of the potential lines causes the nn + transition downwards, field division at this point and the blocking voltage decreases again. In addition to the grinding angle, it also depends on the basic dimensioning, how broad the plateau area fails with maximum blocking voltage as a function of the implantation dose. In the 3.3 kV structure, the application of a blocking voltage of about 2300 V in volume already leads to punch through of the electric field to the cathode, which simultaneously acts as a field stop, ie the further propagation of the space charge zone is stopped. The penetration happens here already at 45% of the maximum voltage.
  • On the other hand, if one considers a structure that is less strongly punched-through, the potential conditions at the semiconductor surface also defuse and the permissible p-dose range becomes wider. For this purpose, the following modifications were made in the simulation:
    The resistivity of the base material was set to 30 Ω · cm and the semiconductor thickness to 75 μm. This corresponds to a dimensioning for an 800 V component. The volume blocking voltage is about 990 V and the space charge zone reaches only when reaching a reverse voltage of 630 V to the cathode by. This corresponds to about 65% of the maximum voltage. In both cases, the field strength is about 110 kV / cm at the nn + transition on reaching the volume breakdown. Since the critical field strength for the avalanche insert at the p + n junction is (weak) doping-dependent, the value there drops from about 800 kV to 3.3 kV from about 220 kV / cm to about 180 kV / cm.
  • In this structure, the blocking voltage drops more slowly outside the plateau region and the dose range corresponding to the maximum blocking voltage becomes larger.
  • Conveniently, for Trenchtaper, which are well below 90 ° and in which case a sidewall implantation is attached, choose a dose value that lies in the middle region of the reverse voltage plateau. This provides appropriate protection against the effects of (both positive and negative) surface charges that may have originated in the process.
  • The manufacturing principle can be applied analogously to other semiconductor materials such as SiC. The invention will be explained in more detail on the basis of a schematic drawing with reference to preferred embodiments.
  • These and further aspects of the present invention are explained below with reference to the attached figures, which show by way of example embodiments of the invention:
  • 1A . 1B are a schematic plan view and a schematic and sectional side view of a power semiconductor structure produced by means of an embodiment of the manufacturing method according to the invention.
  • 2A -H show intermediate stages which are achieved in a preferred embodiment of the method according to the invention for producing a semiconductor component.
  • 3 shows in the form of a diagram the equipotential distribution of a high-voltage diode, which was generated according to a preferred embodiment of the method according to the invention for producing a power semiconductor device.
  • 4 is a graph showing the normalized reverse voltage as a function of the implantation dose in power semiconductor devices according to the invention.
  • Hereinafter, structurally and / or functionally similar or equivalent structures or method steps will be denoted by the same reference numerals designated. Not in every case of their occurrence, a detailed description of the structural elements or process steps is repeated.
  • The 1A and 1B show in the form of a schematic plan view and in the form of a schematic sectional side view of a power semiconductor device which has been produced according to an embodiment of the method according to the invention for producing a semiconductor device.
  • Each in the 1A and 1B shown power semiconductor device 1 lies a power semiconductor material area 20 underlying, also called a chip 20 can be designated. The chip 20 consists of a central area 20Z and from a border area 20R , In the area of the central area 20Z According to the invention, the semiconductor circuit arrangement on which the power semiconductor component is based 10 educated. At the edge 20R is for an electrical edge termination 30 taken care of, by which the potential and field profile for the power semiconductor device are brought to completion in the desired form. These are for the edge termination area 30 trenches 32 or trenches 32 provided in their entirety a corresponding trench structure 40 for the edge termination area 30 form. The trenches 32 run with respect to the surface area 20a of the chip 20 vertically into the material of the semiconductor material region 20 or chips 20 into it. Regarding the edge R of the chip 20 and the border area 20R the trenches run 32 essentially parallel.
  • The 2A to 2H show intermediate stages in the production of a power semiconductor device 1 in a manner according to the invention in accordance with a preferred embodiment of the production method according to the invention.
  • In the in 2A shown intermediate state is first a semiconductor material region 20 or chip 20 provided. This consists in the embodiment of the figure sequence 2A to 2H from a first area 20-1 , which is formed as an n + substrate. This is followed by a second area 20-2 ' as epitaxial layer or n-base. In the 2A is also the surface area 20A of the chip 20 to see on which additionally a litter layer 60 in the form of a litter oxide 60 is applied. These serve to homogenize a p-implantation in the form of implanted boron ions by scattering. This implantation of boron ions is performed areal and is in the 2A indicated by arrows, that is, the implantation takes place from the surface 20a of the chip 20 ago.
  • The implantation of the boron ions results in a surface-doped area or third area 20-3 of the chip 20 , which in the embodiment of the figure sequence 2A to 2H is an area with a p + doping. After removal of the litter layer 60 will then be on the surface area 20a and thus to the third area 20-3 a material 70 ' deposited for a trainee hardmask.
  • In the transition to the in 2C shown intermediate state, the hard mask is then structured by means of a photo-engineering process such that in the hard mask material 70 ' recesses 72 arise through which the surface area 20a of the chip 20 and so the third area 20-3 of the chip 20 be exposed. This is true at least in part of the border area 20R of the chip 20 or semiconductor material region 20 ,
  • In the transition to the in 2D intermediate state then finds a plasma etching with respect to in 2C shown structure, thereby characterized in the area below the recess 72 in the mask 70 a ditch 32 arises, which of the surface area 20a goes out and through the third area 20-3 with p + doping and by area 20-2 with n-type doping, except for a first portion of the n + substrate 20-1 , The trench thus obtained has a bottom area 32b in the region of the n + substrate 20-1 as well as wall areas 32w , In 2D is still a lateral Borimplantation indicated by arrows, through which the side walls 32w and the areas behind it are p-doped accordingly.
  • In the transition to the in 2E The intermediate state shown then conforms to a passivation layer 80 deposited, through which the surface area 70a the hard mask 70 outside the trenches 32 is covered. In addition, the interior of the trenches also conforms in a compliant manner 32 lined, that is the wall areas 32w and the floor areas 32b the trenches 32 are also using the passivation material 80 covered. Shown in the 2E also the p-doped side wall areas 32p , also called π zones 32p be designated. Their training is optional.
  • In the transition to the in 2F shown intermediate state then finds the formation of a dielectric 90 on the structure 2E instead, in such a way that both the surface 80a the passivation layer 80 covered, as well as the trenches 32 be completely filled, leaving a substantially planar surface 90a through the dielectric material 90 is taught.
  • In the transition to the in 2G shown intermediate state then takes place an etch-back process such that outside the trenches 32 the dielectric layer 90 and the passivation layer 80 from the preserved structure outside the trenches 32 be removed so that there is the surface 70a the hard mask 70 is exposed.
  • In the transition to the in 2H intermediate state shown is then still the hard mask 70 away. By a growing process then arises selectively on the surface 20a of the chip 20 and thus on the surface of the third and p + doped region 20-3 selectively a metallization through which the dielectric material 90 inside the trench 32 not covered.
  • The experimental results and simulation results for various embodiments are shown in the graphs of 3 and 4 and have already been discussed in detail above.
  • LIST OF REFERENCE NUMBERS
  • 1
    Power semiconductor device, power semiconductor module
    10
    Semiconductor circuitry,
    20
    Semiconductor material area, chip
    20a
    surface area
    20Z
    Central area
    20R
    border area
    20-1
    first material region, first section, substrate, n + substrate
    20-2
    second area, second section, epitaxy area, n-base area
    20-2 '
    second area, second section, epitaxy area, n-base area
    20-3
    third area, third section, surface doped area
    30
    Edge termination area
    32
    Ditch, trench
    32b
    floor area
    32p
    Side implantation region
    32w
    wall area
    40
    grave structure
    60
    Litter layer, litter oxide
    60a
    surface area
    70
    Mask, hard mask
    70 '
    Mask material, hard mask material
    72
    recess
    80
    passivation
    80a
    surface area
    90
    dielectric material
    90a
    surface area
    100
    metallization
    R
    edge

Claims (9)

  1. Method for producing a power semiconductor component ( 1 ) with only a single photostructuring step, in which a semiconductor material region ( 20 ) with a central area ( 20Z ), with a border area ( 20R ) and with a surface area ( 20a ), in the central area ( 20Z ) of the semiconductor material region ( 20 ) a power semiconductor device ( 1 ) underlying semiconductor circuit arrangement ( 10 ), one for the semiconductor circuit arrangement ( 10 ) provided electrical edge termination area ( 30 ) with at least one in the edge region ( 20R ) of the semiconductor material region ( 20 ) trench ( 40 ), wherein the at least one trench ( 40 ) from the surface area ( 20a ) of the semiconductor material region ( 20 ) vertically into the semiconductor material region ( 20 ) is formed extending into which at least one trench ( 32 ) by a passivation layer produced in a conformable manner ( 80 ) and through a dielectric ( 90 ) is filled outside the at least one trench ( 32 ) the surface area ( 20a ) of the semiconductor material region ( 20 ) and self-aligned to the at least one trench a metallization ( 100 ) is formed, wherein the dielectric in an interior of the at least one trench ( 30 ) through the metallization ( 100 ) is not covered.
  2. The method of claim 1, wherein the semiconductor material region ( 20 ) with a first of a first conductivity type (s) highly doped and of the surface area ( 20a ) of the semiconductor material region ( 20 ) remote area ( 20-1 ) is formed as a substrate.
  3. Method according to Claim 2, in which the semiconductor material region ( 20 ) with a second and of the first conductivity type (s) less highly doped and the surface area ( 20a ) of the semiconductor material region ( 20 ) facing area ( 20-2 . 20-2 ' ) is formed as Epitaxiebereich.
  4. The method of claim 3, wherein after the step of forming the semiconductor circuitry ( 10 ) or a part thereof in the surface area ( 20a ) of the semiconductor material region ( 20 ) a second region (p) highly doped third region ( 20-3 ) is formed by implantation.
  5. A method according to claim 4, wherein in preparation for the step of forming the third region doped with the second conductivity type (p) ( 20-3 ) on the surface area ( 20a ) of the semiconductor material region ( 20 ) a litter layer ( 60 ) with a surface area ( 60a ) is formed.
  6. Method according to one of the preceding claims, in which the at least one trench ( 32 ) parallel to the edge (R) of the edge region ( 20R ) of the semiconductor material region ( 20 ) is formed running.
  7. Method according to one of the preceding claims, in which a lateral implantation into a wall region ( 32w ) of the at least one trench ( 32 ) is performed with a subsequent activation of the implanted material.
  8. Method according to one of the preceding claims, in which a power diode is used as power semiconductor component ( 1 ) is formed.
  9. Method according to one of the preceding claims, in which the power semiconductor component ( 1 ) and its underlying semiconductor circuitry ( 10 ) is formed completely or partially as an arrangement and parallel connection of identical semiconductor elements in a cell array.
DE200410037153 2004-07-30 2004-07-30 Method for producing a power semiconductor device Expired - Fee Related DE102004037153B4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE200410037153 DE102004037153B4 (en) 2004-07-30 2004-07-30 Method for producing a power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE200410037153 DE102004037153B4 (en) 2004-07-30 2004-07-30 Method for producing a power semiconductor device

Publications (2)

Publication Number Publication Date
DE102004037153A1 DE102004037153A1 (en) 2006-03-23
DE102004037153B4 true DE102004037153B4 (en) 2011-09-15

Family

ID=36001460

Family Applications (1)

Application Number Title Priority Date Filing Date
DE200410037153 Expired - Fee Related DE102004037153B4 (en) 2004-07-30 2004-07-30 Method for producing a power semiconductor device

Country Status (1)

Country Link
DE (1) DE102004037153B4 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9070580B2 (en) 2013-05-01 2015-06-30 Infineon Technologies Austria Ag Semiconductor device with a super junction structure based on a compensation structure with compensation layers and having a compensation rate gradient
US9117694B2 (en) 2013-05-01 2015-08-25 Infineon Technologies Austria Ag Super junction structure semiconductor device based on a compensation structure including compensation layers and a fill structure
US9024383B2 (en) 2013-05-01 2015-05-05 Infineon Technologies Austria Ag Semiconductor device with a super junction structure with one, two or more pairs of compensation layers

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4756793A (en) * 1985-10-10 1988-07-12 U.S. Philips Corp. Method of manufacturing a semiconductor device
US5311052A (en) * 1981-10-16 1994-05-10 Siemens Aktiengesellschaft Planar semiconductor component with stepped channel stopper electrode
DE19531369A1 (en) * 1995-08-25 1997-02-27 Siemens Ag Semiconductor device based on silicon with hochsperrendem edge termination
US5963785A (en) * 1996-02-29 1999-10-05 Kabushiki Kaisha Toshiba Dielectrically-isolated integrated circuit
DE19954600C1 (en) * 1999-10-11 2000-11-16 Infineon Technologies Ag Integrated circuit contg. switching transistor and Zener diode chain has considerably increased breakdown voltage whilst maintaining size of edge termination
US20030047776A1 (en) * 2001-09-13 2003-03-13 Hueting Raymond J.E. Edge termination in MOS transistors
US20030047779A1 (en) * 2001-09-13 2003-03-13 Koninklijke Philips Electronics N.V. Trench-gate semiconductor devices and their manufacture
WO2004001854A2 (en) * 2002-06-25 2003-12-31 Koninklijke Philips Electronics N.V. Semiconductor device with edge structure
US20040048488A1 (en) * 2000-11-16 2004-03-11 Baliga Bantval Jayant Methods of forming vertical power devices having deep and shallow trenches therein

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311052A (en) * 1981-10-16 1994-05-10 Siemens Aktiengesellschaft Planar semiconductor component with stepped channel stopper electrode
US4756793A (en) * 1985-10-10 1988-07-12 U.S. Philips Corp. Method of manufacturing a semiconductor device
DE19531369A1 (en) * 1995-08-25 1997-02-27 Siemens Ag Semiconductor device based on silicon with hochsperrendem edge termination
US5963785A (en) * 1996-02-29 1999-10-05 Kabushiki Kaisha Toshiba Dielectrically-isolated integrated circuit
DE19954600C1 (en) * 1999-10-11 2000-11-16 Infineon Technologies Ag Integrated circuit contg. switching transistor and Zener diode chain has considerably increased breakdown voltage whilst maintaining size of edge termination
US20040048488A1 (en) * 2000-11-16 2004-03-11 Baliga Bantval Jayant Methods of forming vertical power devices having deep and shallow trenches therein
US20030047776A1 (en) * 2001-09-13 2003-03-13 Hueting Raymond J.E. Edge termination in MOS transistors
US20030047779A1 (en) * 2001-09-13 2003-03-13 Koninklijke Philips Electronics N.V. Trench-gate semiconductor devices and their manufacture
WO2004001854A2 (en) * 2002-06-25 2003-12-31 Koninklijke Philips Electronics N.V. Semiconductor device with edge structure

Also Published As

Publication number Publication date
DE102004037153A1 (en) 2006-03-23

Similar Documents

Publication Publication Date Title
TWI404220B (en) Power semiconductor devices and methods of manufacture
US6870201B1 (en) High voltage resistant edge structure for semiconductor components
US6399996B1 (en) Schottky diode having increased active surface area and method of fabrication
US6605858B2 (en) Semiconductor power device
JP3938964B2 (en) High voltage semiconductor device and manufacturing method thereof
JP5309058B2 (en) Trench metal oxide semiconductor device and method of manufacturing termination structure
US6498071B2 (en) Manufacture of trench-gate semiconductor devices
US8936985B2 (en) Methods related to power semiconductor devices with thick bottom oxide layers
US6534367B2 (en) Trench-gate semiconductor devices and their manufacture
US6919610B2 (en) Power semiconductor device having RESURF layer
US6426542B1 (en) Schottky diode with dielectric trench
EP0948818B1 (en) High density trench dmos transistor with trench bottom implant
US7166866B2 (en) Edge termination for silicon power devices
TWI270208B (en) High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon
US8994066B2 (en) Manufacturing method of semiconductor device
US8178920B2 (en) Semiconductor device and method of forming the same
US7795675B2 (en) Termination for trench MIS device
JP3850054B2 (en) Semiconductor device
DE10196527B3 (en) Method for producing a thick oxide layer on the bottom of a trench structure in silicon
JP5154347B2 (en) Superjunction semiconductor device and method of manufacturing superjunction semiconductor device
EP1842236B1 (en) Manufacturing process for high voltage semiconductor device
DE60118217T2 (en) Schottky rectifier with dig
US7339252B2 (en) Semiconductor having thick dielectric regions
US7052982B2 (en) Method for manufacturing a superjunction device with wide mesas
TWI254453B (en) Trench DMOS device with improved drain contact

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
R018 Grant decision by examination section/examining division
R082 Change of representative
R020 Patent grant now final

Effective date: 20111216

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee