DE102004019567B3 - Securing electronic components to substrate by subjecting the electronic component, supporting film and paste-like layer to pressure and connecting the substrate and the component by sintering - Google Patents

Securing electronic components to substrate by subjecting the electronic component, supporting film and paste-like layer to pressure and connecting the substrate and the component by sintering Download PDF

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DE102004019567B3
DE102004019567B3 DE102004019567A DE102004019567A DE102004019567B3 DE 102004019567 B3 DE102004019567 B3 DE 102004019567B3 DE 102004019567 A DE102004019567 A DE 102004019567A DE 102004019567 A DE102004019567 A DE 102004019567A DE 102004019567 B3 DE102004019567 B3 DE 102004019567B3
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layer
component
substrate
pressure
carrier film
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Gerhard Palm
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Semikron GmbH and Co KG
Semikron Elektronik GmbH and Co KG
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Semikron GmbH and Co KG
Semikron Elektronik GmbH and Co KG
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27003Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436Lamination of a preform, e.g. foil, sheet or layer
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor

Abstract

Electronic components are secured to a substrate by subjecting the electronic component, supporting film and paste-like layer to pressure so that adhesive force between the dried layer and the component becomes greater than the adhesive force between the dried layer and the supporting film; and subjecting the substrate and the component to pressure thus connecting the substrate and the component by sintering. Securing electronic components to a substrate by pressure sintering involves: (a) applying a paste-like layer (20) comprising a metal powder and a solvent to a supporting film (10); (b) drying the paste-like layer; applying electronic component(s) to the dried layer; (c) subjecting the electronic component, the supporting film and the dried layer to pressure so that the adhesive force between the dried layer and the component becomes greater than the adhesive force between the dried layer and the supporting film; (d) removing the component, with the layer adhering to the component, from the supporting film; (e) positioning the component on the substrate; and (f) subjecting the substrate and the component to pressure, thus connecting the substrate and the component by sintering.

Description

  • Die Erfindung beschreibt ein Verfahren zur Befestigung von elektronischen Bauelementen, insbesondere von Leistungshalbleiterbauelementen wie Dioden, Transistoren oder Thyristoren, auf einem Substrat. Bei dem Verfahren handelt es sich um ein Sinterverfahren, wie es grundsätzlich bereits seit langem bekannt ist.The Invention describes a method for mounting electronic Components, in particular of power semiconductor components such as diodes, Transistors or thyristors, on a substrate. In the process it is a sintering process, as it already is has long been known.
  • Den grundlegenden Stand der Technik hierzu bilden die DE 34 14 065 C2 sowie die EP 0 242 626 B1 . Die DE 34 14 065 C2 offenbart ein Verfahren, das durch folgende wesentliche Verarbeitungsschritte gekennzeichnet ist:
    • • Aufbringen einer aus einem Metallpulver und einem Lösungsmittel bestehenden pastösen Schicht auf die zu verbindende Kontaktfläche des Bauelements oder des Substrats;
    • • Aufbringen des Bauelements auf das Substrat, wobei die pastöse Schicht zwischen dem Bauelement und dem Substrat angeordnet wird;
    • • Austreiben des Lösungsmittels aus dem Verbund aus Bauelement, pastöser Schicht und Substrat;
    • • Erwärmung des Verbunds auf Sintertemperatur, vorzugsweise unter zusätzlicher Druckbeaufschlagung.
    The basic state of the art for this form the DE 34 14 065 C2 as well as the EP 0 242 626 B1 , The DE 34 14 065 C2 discloses a method characterized by the following essential processing steps:
    • Applying a paste-like layer consisting of a metal powder and a solvent to the contact surface of the component or the substrate to be connected;
    • Applying the component to the substrate, wherein the pasty layer is arranged between the component and the substrate;
    • • expelling the solvent from the composite of component, pasty layer and substrate;
    • • Heating of the composite to sintering temperature, preferably with additional pressurization.
  • Nachteilig am genannten Stand der Technik ist, dass der Trockenvorgang der pastösen Schicht nach dem Zusammenfügen des Bauelements und des Substrats durchgeführt wird. Da hier ein schnelles Ausgasen über eine große Oberfläche nicht möglich ist, ist dieses Verfahren durch erhebliche Prozesszeiten gekennzeichnet. Die EP 0 242 626 B1 offenbart demgegenüber ein Verfahren, das durch folgende wesentliche Verarbeitungsschritte gekennzeichnet ist:
    • • Aufbringen einer aus einem Metallpulver und einem Lösungsmittel bestehenden pastösen Schicht auf die zu verbindende Kontaktfläche des Bauelements oder des Substrats;
    • • Trocknen der pastösen Schicht;
    • • Aufbringen des Bauelements auf das Substrat, wobei die getrocknete pastöse Schicht zwischen dem Bauelement und dem Substrat angeordnet wird;
    • • Erwärmung des Verbunds auf Sintertemperatur unter zusätzlicher Druckbeaufschlagung.
    A disadvantage of the cited prior art is that the drying process of the pasty layer is carried out after the assembly of the component and the substrate. Since a rapid outgassing over a large surface is not possible here, this process is characterized by considerable process times. The EP 0 242 626 B1 In contrast, discloses a method which is characterized by the following essential processing steps:
    • Applying a paste-like layer consisting of a metal powder and a solvent to the contact surface of the component or the substrate to be connected;
    • • drying the pasty layer;
    • Applying the device to the substrate, wherein the dried pasty layer is disposed between the device and the substrate;
    • • Heating of the composite to sintering temperature with additional pressurization.
  • Dieses Verfahren vermeidet den Hauptnachteil des erstgenannten Stands der Technik. Allerdings weist dieses Verfahren, wie auch das erstgenannte den Nachteil auf, dass es sich um ein rein serielles Verfahren handelt, das einer modernen und rationellen Fertigung derartiger Verbindungen entgegen steht.This The method avoids the main disadvantage of the former state of the art Technology. However, this method, like the former, the Disadvantage that this is a purely serial process, that of a modern and rational production of such compounds opposes.
  • Ebenso nachteilig an den genannten Verfahren ist, dass ein strukturiertes Aufbringen der pastösen Schicht auf das Bauelement oder das Substrat nur unter erheblichem Aufwand möglich ist.As well A disadvantage of the said method is that a structured Apply the pasty Layer on the device or the substrate only under considerable Effort possible is.
  • Weiterhin sind aus der JP 03-46242 A, der DE 197 34 317 A1 und aus der EP 09 49 662 A2 Verfahren bekannt zum Bauteiletransfer von einem Zwischenträger auf einen finalen Bauteileträger. Hierbei wird auf vielfältige aus dem Stand der Technik bekannte Verfahren, wie Eutektikbonden, Lötbonden und Klebeverfahren abgestellt. Aus den Druckschriften JP 54-19363 A und JP 60-63939 A sind Verfahren bekannt zum Aufbringen von Pasten auf ein entsprechendes Trägermaterial bekannt. Die JP 54-19363 A offenbart hierbei ein Verfahren zur Übertragung einer Paste, die als Film auf eine Platte aufgebracht wurden, auf ein Halbleiterbauelement. Die JP 60-63939 A offenbart die Übertragung einer Paste von einem Transferträger in eine Kavität eines Substrats.Furthermore, from JP 03-46242 A, the DE 197 34 317 A1 and from the EP 09 49 662 A2 Method known for component transfer from an intermediate carrier to a final component carrier. This is based on various known from the prior art method, such as eutectic bonding, solder bonding and bonding process. From the documents JP 54-19363 A and JP 60-63939 A are known methods for applying pastes to a corresponding carrier material. JP 54-19363 A discloses a method for transferring a paste which has been applied as a film to a plate to a semiconductor device. JP 60-63939 A discloses the transfer of a paste from a transfer carrier into a cavity of a substrate.
  • Die vorliegende Erfindung hat die Aufgabe ein Verfahren zur Befestigung von elektronischen Bauelementen auf einem Substrat mittels Drucksintern vorzustellen, welches einer rationellen und zumindest teilweise parallelen Verarbeitung einer Mehrzahl von Bauelementen zugänglich ist sowie eine strukturierte Ausgestaltung der Sinterschicht erlaubt.The The present invention has the object of a method for fastening of electronic components on a substrate by means of pressure sintering to imagine which one rational and at least partially parallel processing of a plurality of components is accessible and a structured configuration of the sintered layer allowed.
  • Die Aufgabe wird gelöst durch ein Verfahren mit den Merkmalen des Anspruchs 1. Bevorzugte Weiterbildungen finden sich in den Unteransprüchen.The Task is solved by a method having the features of claim 1. Preferred developments can be found in the subclaims.
  • Das erfindungsgemäße Verfahren zur Befestigung von elektronischen Bauelementen, insbesondere von Leistungshalbleiterbauelementen wie Dioden, Transistoren oder Thyristoren, auf einem Substrat mittels Drucksintern ist gekennzeichnet durch folgende wesentliche Verfahrensschritten:
    • a) Aufbringen einer pastösen Schicht auf eine Trägerfolie. Hierbei besteht diese Schicht gemäß dem Stand der Technik aus einem Gemisch aus einem Metallpulver und einem Lösungsmittel.
    • b) Trocknen der pastösen Schicht.
    • c) Aufbringen von mindestens einem, vorteilhafterweise einer Mehrzahl von Bauelementen auf die getrocknete Schicht. Hierbei sind die Bauelemente vorzugsweise auf einer über einem Rahmen aufgespannten Trägerfolie angeordnet.
    • d) Druckbeaufschlagung des Verbunds aus dem mindestens einem Bauelement und der Trägerfolie mit der getrockneten Schicht. Hierdurch wird die Haftkraft zwischen der Schicht und dem Bauelement größer als die Haftkraft zwischen der Schicht und der Trägerfolie.
    • e) Abheben des mindestens einen Bauelements mit daran haftender Schicht von der Trägerfolie.
    • f) Positionierung des mindestens eine Bauelements mit der daran haftenden Schicht auf dem Substrat.
    • g) Druckbeaufschlagung der Anordnung des Substrats und des mindestens einen Bauelements, wodurch die Sinterverbindung entsteht.
    The method according to the invention for fastening electronic components, in particular power semiconductor components such as diodes, transistors or thyristors, to a substrate by means of pressure sintering is characterized by the following essential method steps:
    • a) applying a pasty layer to a carrier film. Here, this layer according to the prior art consists of a mixture of a metal powder and a solvent.
    • b) drying the pasty layer.
    • c) applying at least one, advantageously a plurality of components to the dried layer. In this case, the components are preferably arranged on a support film spanned over a frame.
    • d) pressurizing the composite of the at least one component and the carrier film with the dried layer. As a result, the adhesive force between the layer and the component is greater than the adhesive force between the layer and the carrier film.
    • e) lifting the at least one component with an adhering layer of the carrier film.
    • f) positioning of the at least one component with the layer adhering to it on the substrate.
    • g) pressurizing the arrangement of the substrate and the at least one component, whereby the sintered connection is formed.
  • Für einen nicht homogenen Auftrag der pastösen Schicht auf das Bauelement wird vor dem Prozessschritt (a) die Trägerfolie entsprechend strukturiert. Hierzu werden mit bekannten Techniken Ausnehmungen in die Folie eingebracht. Beim Aufbringen der Schicht wird diese somit ohne weiteren Aufwand direkt strukturiert. Diese Struktur wird anschließend im Prozessschritt (c) ebenso einfach auf die Bauelemente übertragen.For one not homogeneous order of pasty Layer on the component is before the process step (a) the carrier film structured accordingly. This is done with known techniques Recesses introduced into the film. When applying the layer This is thus directly structured without further effort. These Structure will follow in the process step (c) just as easily transferred to the components.
  • Nachfolgend wird der erfinderische Gedanke anhand der 1 bis 4 beispielhaft erläutert.Hereinafter, the inventive idea based on the 1 to 4 exemplified.
  • 1 zeigt den Verfahrensschritt (a) des erfindungsgemäßen Verfahrens. 1 shows the method step (a) of the method according to the invention.
  • 2 zeigt den Verfahrensschritt (d) des erfindungsgemäßen Verfahrens. 2 shows the method step (d) of the method according to the invention.
  • 3 zeigt die Verfahrensschritte (e, f) des erfindungsgemäßen Verfahrens. 3 shows the method steps (e, f) of the method according to the invention.
  • 4 zeigt den Verfahrensschritt (g) des erfindungsgemäßen Verfahrens. 4 shows the method step (g) of the method according to the invention.
  • 1 zeigt den Verfahrensschritt (a) des erfindungsgemäßen Verfahrens. Die Basis bildet eine Trägerfolie (10), vorzugsweise eine Polyesterfolie mit einer Dicke zwischen 100μm und 200μmm. Hierauf wird mittels eines Sprühverfahrens (22) eine pastöse Schicht (20) aufgebracht. Ebenso anwendbar sind andere nach dem Stand der Technik bekannte Verfahren, wie beispielsweise ein Siebdruckverfahren. Die pastöse Schicht besteht (20) aus einer Mischung eines Metallpulvers, vorzugsweise aus Silber oder einer Silberlegierung, mit Cyclohexanol im Verhältnis von 1:2 bis 1:4. Die Schichtdicke dieser Schicht beträgt zwischen 10μm und 50μm. 1 shows the method step (a) of the method according to the invention. The base forms a carrier foil ( 10 ), preferably a polyester film having a thickness between 100μm and 200μmm. This is followed by means of a spray process ( 22 ) a pasty layer ( 20 ) applied. Also applicable are other methods known in the art, such as a screen printing process. The pasty layer consists ( 20 ) from a mixture of a metal powder, preferably of silver or a silver alloy, with cyclohexanol in the ratio of 1: 2 to 1: 4. The layer thickness of this layer is between 10 .mu.m and 50 .mu.m.
  • Um Bauelemente nicht flächig, sondern strukuriert zu beschichten, wie es beispielhaft für Steueranschlüsse notwendig sein kann, wird die Trägerfolie (10) vor der Beschichtung in sich strukturiert.In order to coat components not flat, but structured, as may be necessary for example for control connections, the carrier film ( 10 ) before the coating in itself.
  • In einem weiteren Verfahrensschritt (b) wird die aufgebrachte pastöse Schicht (20) bei einer Temperatur zwischen 100°C und 200°C getrocknet.In a further process step (b), the applied pasty layer ( 20 ) dried at a temperature between 100 ° C and 200 ° C.
  • Anschließend werden die Bauelemente (40) im Verfahrensschritt (c) auf die nun getrocknete Schicht (20') aufgebracht. Hierbei sind die Bauelemente (40) nach dem Stand der Technik auf einer in einen Rahmen (32) gespannten Folie (34) angeordnet. Diese Anordnung der Bauelemente (40) erfordert keinen zusätzlicher Arbeitsschritt, da der letzte Fertigungsschritt der Herstellung von Halbleiterbauelementen das Sägen der im Waferverbund vorhandenen Bauelemente ist und hierzu die Bauelemente (40) auf derartige Trägervorrichtungen (30) aufgebracht werden. Somit werden die Bauelemente (40) auf dieser Vorrichtung (30) belassen, wie es auch für andere nach dem Stand der Technik bekannte Verarbeitungsschritte von ungehausten Bauelementen üblich ist.Subsequently, the components ( 40 ) in process step (c) on the now dried layer ( 20 ' ) applied. Here are the components ( 40 ) according to the state of the art on a frame ( 32 ) stretched film ( 34 ) arranged. This arrangement of the components ( 40 ) requires no additional work step, since the last manufacturing step of the production of semiconductor devices is the sawing of the components present in the wafer assembly and, for this purpose, the components ( 40 ) to such carrier devices ( 30 ) are applied. Thus, the components ( 40 ) on this device ( 30 ), as is conventional with other prior art processing steps of unhoused devices.
  • 2 zeigt den Verfahrensschritt (d) des erfindungsgemäßen Verfahrens. Hierbei wird der Verbund aus Trägerfolie (10), getrockneter Schicht (20') und Bauelementen (40) mit Druck beaufschlagt. Als vorteilhaft hat sich hierbei ein Druck (70) zwischen 20 MPa und 80 MPa und eine Temperatur zwischen 40°C und 100°C erwiesen. Der hierbei eingeleitete Druck ist ausreichend um eine Verbindung zwischen dem Bauelement (40) und der getrockneten Schicht (20') herzustellen, die eine höhere Haftkraft aufweist als die Verbindung zwischen der Trägerfolie (10) und dem Bauelement (40). 2 shows the method step (d) of the method according to the invention. Here, the composite of carrier film ( 10 ), dried layer ( 20 ' ) and components ( 40 ) is pressurized. An advantage here is a pressure ( 70 ) between 20 MPa and 80 MPa and a temperature between 40 ° C and 100 ° C proved. The pressure introduced in this case is sufficient for a connection between the component ( 40 ) and the dried layer ( 20 ' ), which has a higher adhesive force than the connection between the carrier film ( 10 ) and the component ( 40 ).
  • In einem weiteren Verfahrensschritt (e) werden die beschichteten Bauelemente (40, 20'') aus dem Verbund gelöst und an denjenigen Stellen eine Substrats (50) angeordnet, an denen die Verbindung zwischen den Bauelementen (40) und dem Substrat (50) hergestellt werden soll. Hierbei können Abnahmevorrichtungen (60), wie sie aus so genannten „Pickand- Place- Automaten" der Halbleiterbauelementverarbeitung bekannt sind, verwendet werden. 3 zeigt für den Verfahrensschritt (f) eine derartige Vorrichtung (60). Hierbei drückt ein Stempel (60), der mit einem Nadelsystem ausgestattet ist, von der dem Bauelement (40) abgewandten Seite auf die Trägerfolie (34) der Vorrichtung (30). Hiermit wird das Bauelement (40) zumindest von der Trägerfolie (34) abgehoben. Vollständig getrennt wird das Bauelement (40) durch das Nadelsystem, das die Folie (32) durchsticht. Somit können mit bekannten Techniken einzelne Bauelement (40) beliebig auf einer Leiterbahn (52) des Substrats (50) positioniert werden.In a further process step (e), the coated components ( 40 . 20 '' ) are released from the composite and at those locations a substrate ( 50 ), at which the connection between the components ( 40 ) and the substrate ( 50 ) is to be produced. In this case, take-off devices ( 60 ), as known from so-called "pick and place automata" of semiconductor device processing. 3 shows for the method step (f) such a device ( 60 ). Here a stamp ( 60 ) equipped with a needle system from which the component ( 40 ) facing away from the carrier film ( 34 ) of the device ( 30 ). This is the component ( 40 ) at least from the carrier film ( 34 ) lifted. The component is completely separated ( 40 ) by the needle system that the film ( 32 ) pierces. Thus, with known techniques, individual components ( 40 ) arbitrarily on a conductor track ( 52 ) of the substrate ( 50 ).
  • In einem abschließenden Verfahrenschritt (g) wird die Anordnung aus Bauelement (40) mit abgeschiedener Schicht (20'') und Substrat (50) mit Druck von mehr als 30 MPa beaufschlagt. Bei gleichzeitiger Erwärmung (ϑ) auf Werte von mehr als 220°C wird die Sinterverbindung hergestellt.In a final process step (g), the device ( 40 ) with deposited layer ( 20 '' ) and substrate ( 50 ) is pressurized to more than 30 MPa. With simultaneous heating (θ) to values of more than 220 ° C, the sintered compound is produced.

Claims (8)

  1. Verfahren zur Befestigung von elektronischen Bauelementen (40), insbesondere von Leistungshalbleiterbauelementen wie Dioden, Transistoren oder Thyristoren, auf einem Substrat (50) mittels Drucksintern mit den Verfahrensschritten: a) Aufbringen einer aus einem Metallpulver und einem Lösungsmittel bestehenden pastösen Schicht (20) auf eine Trägerfolie (10); b) Trocknen der pastösen Schicht (20); c) Aufbringen von mindestens einem Bauelement (40) auf die getrocknete Schicht (20'); d) Druckbeaufschlagung (70) des Verbunds aus dem mindestens einen Bauelement (40) und der Trägerfolie (10) mit der getrockneten Schicht (20'), wodurch die Haftkraft zwischen der Schicht (20') und dem Bauelement (40) größer wird als zwischen der Schicht (20') und der Trägerfolie (10); e) Abheben des mindestens einen Bauelements (40) mit daran haftender Schicht (20'') von der Trägerfolie (10); f) Positionierung des Bauelements (40) mit der daran haftenden Schicht (20'') auf dem Substrat (50); g) Druckbeaufschlagung (80) der Anordnung des Substrats (50) und des Bauelements (40) zu deren Sinterverbindung.Method for fixing electronic components ( 40 ), in particular of power semiconductor components such as diodes, transistors or thyristors, on a substrate ( 50 ) by means of Pressure sintering with the method steps: a) applying a pasty layer consisting of a metal powder and a solvent ( 20 ) on a carrier foil ( 10 ); b) drying the pasty layer ( 20 ); c) applying at least one component ( 40 ) on the dried layer ( 20 ' ); d) pressurization ( 70 ) of the composite of the at least one component ( 40 ) and the carrier film ( 10 ) with the dried layer ( 20 ' ), whereby the adhesive force between the layer ( 20 ' ) and the component ( 40 ) becomes larger than between the layer ( 20 ' ) and the carrier film ( 10 ); e) lifting the at least one component ( 40 ) with adherent layer ( 20 '' ) of the carrier film ( 10 ); f) Positioning of the device ( 40 ) with the layer adhering thereto ( 20 '' ) on the substrate ( 50 ); g) pressurization ( 80 ) of the arrangement of the substrate ( 50 ) and the component ( 40 ) to the sintered connection.
  2. Verfahren nach Anspruch 1, wobei das Metallpulver aus Silber oder einer Silberlegierung besteht.The method of claim 1, wherein the metal powder made of silver or a silver alloy.
  3. Verfahren nach Anspruch 1, wobei die Trägerfolie (10) aus einen Polyesterfolie mit einer Dicke zwischen 100μmm und 200μmm besteht.Method according to claim 1, wherein the carrier film ( 10 ) consists of a polyester film with a thickness between 100μmm and 200μmm.
  4. Verfahren nach Anspruch 1, wobei die Trägerfolie (10) in sich strukturiert ist um das Bauelement (40) strukturiert zu beschichten.Method according to claim 1, wherein the carrier film ( 10 ) is structured around the device ( 40 ) to coat structured.
  5. Verfahren nach Anspruch 1, wobei die pastöse Schicht (20) aus einer Mischung aus Silberpulver mit Cyclohexanol im Verhältnis von 1:2 bis 1:4 besteht und eine Schichtdicke zwischen 10μm und 50μm aufweist.Process according to claim 1, wherein the pasty layer ( 20 ) consists of a mixture of silver powder with cyclohexanol in the ratio of 1: 2 to 1: 4 and has a layer thickness between 10 .mu.m and 50 .mu.m.
  6. Verfahren nach Anspruch 1, wobei die pastöse Schicht (20) bei einer Temperatur zwischen 100°C und 200°C getrocknet wird.Process according to claim 1, wherein the pasty layer ( 20 ) is dried at a temperature between 100 ° C and 200 ° C.
  7. Verfahren nach Anspruch 1, wobei der Verbund aus Bauelement (40) und Trägerfolie (10) mit pastöser Schicht (20') für 5 bis 20 Sekunden mit einem Druck zwischen 20 MPa und 80 MPa und einer Temperatur zwischen 40°C und 100°C beaufschlagt wird.Method according to claim 1, wherein the composite of component ( 40 ) and carrier film ( 10 ) with pasty layer ( 20 ' ) is pressurized for 5 to 20 seconds to a pressure between 20 MPa and 80 MPa and a temperature between 40 ° C and 100 ° C.
  8. Verfahren nach Anspruch 1, wobei eine Mehrzahl von Bauelementen (40) mittels einer auf der der Schicht (20) abgewandten Seite mittels eines Trägers (30) bestehend aus einem Rahmen (32) und einer Haftfolie (34) zueinander angeordnet sind.Method according to claim 1, wherein a plurality of components ( 40 ) by means of a layer on the 20 ) facing away by means of a carrier ( 30 ) consisting of a frame ( 32 ) and an adhesive film ( 34 ) are arranged to each other.
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DE102004056702A DE102004056702B3 (en) 2004-04-22 2004-11-24 Method for mounting electronic components on a substrate
EP05004621A EP1599078A3 (en) 2004-04-22 2005-03-03 Method of mounting an electronic component on a substrate
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005047567B3 (en) * 2005-10-05 2007-03-29 Semikron Elektronik Gmbh & Co. Kg Power semiconductor module comprises a housing, connecting elements and an electrically insulated substrate arranged within the housing and semiconductor components with a connecting element and an insulating molded body
EP1796137A2 (en) 2005-12-09 2007-06-13 Semikron Elektronik GmbH & Co. KG Patentabteilung Apparatus and clocked method for pressure sintering
WO2008003308A1 (en) 2006-07-07 2008-01-10 Technische Universität Carolo-Wilhelmina Method for attaching electronic components to a support by means of pressure sintering and circuit arrangement
EP1956647A1 (en) 2007-02-10 2008-08-13 SEMIKRON Elektronik GmbH & Co. KG Switch device with connecting device and corresponding production method
EP2061071A2 (en) 2007-11-16 2009-05-20 SEMIKRON Elektronik GmbH & Co. KG Method for producing a semiconductor component
DE102008009510B3 (en) * 2008-02-15 2009-07-16 Danfoss Silicon Power Gmbh Method for low-temperature pressure sintering
EP1993133A3 (en) * 2007-05-12 2010-09-08 SEMIKRON Elektronik GmbH & Co. KG Sintered high performance semiconductor substrate and corresponding production method
EP1993132A3 (en) * 2007-05-12 2010-09-08 SEMIKRON Elektronik GmbH & Co. KG High performance semiconductor substrate with metal contact layer and corresponding production method
DE102009018541A1 (en) * 2009-04-24 2010-10-28 W.C. Heraeus Gmbh Contacting unit for electronic component, is porous metallic layered structure, and contact surface of electronic component and layered structure geometrically fit to each other, where thickness of layer is ten micrometers
US7851334B2 (en) 2007-07-20 2010-12-14 Infineon Technologies Ag Apparatus and method for producing semiconductor modules
DE102005047566C5 (en) * 2005-10-05 2011-06-09 Semikron Elektronik Gmbh & Co. Kg Arrangement with a power semiconductor component and with a housing and manufacturing method thereof
EP2367202A2 (en) 2010-03-17 2011-09-21 SEMIKRON Elektronik GmbH & Co. KG Method for producing an electrically conductive connection between a contact and a counter contact
US8110925B2 (en) 2007-07-26 2012-02-07 Semikron Elektronik Gmbh & Co., Kg Power semiconductor component with metal contact layer and production method therefor
DE102010044329A1 (en) 2010-09-03 2012-03-08 Heraeus Materials Technology Gmbh & Co. Kg Contacting agent and method for contacting electrical components
EP2498283A2 (en) 2011-03-10 2012-09-12 SEMIKRON Elektronik GmbH & Co. KG Method for manufacturing a power-semiconductor substrate
DE102012204159A1 (en) * 2012-03-16 2013-03-14 Continental Automotive Gmbh Power semiconductor module for controlling electric machine in e.g. motor mode, has punching lattice provided with metal strips, where covers of lattice comprise connection between surfaces of electrode with terminal surfaces
DE102011083926A1 (en) * 2011-09-30 2013-04-04 Robert Bosch Gmbh Layer composite of a carrier film and a layer arrangement comprising a sinterable layer of at least one metal powder and a solder layer
DE102011083911A1 (en) * 2011-09-30 2013-04-04 Robert Bosch Gmbh Electronic assembly with high-temperature-stable substrate base material
US8662377B2 (en) 2004-04-22 2014-03-04 Semikron Elektronik Gmbh & Co., Kg Method for securing electronic components to a substrate
WO2014086519A1 (en) 2012-12-06 2014-06-12 Robert Bosch Gmbh Method for connecting at least two components using a sintering process
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US8835299B2 (en) 2012-08-29 2014-09-16 Infineon Technologies Ag Pre-sintered semiconductor die structure
DE102013104572A1 (en) * 2013-05-03 2014-11-06 Osram Opto Semiconductors Gmbh Method for forming an optoelectronic assembly and optoelectronic assembly
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DE102019134410A1 (en) * 2019-12-13 2021-06-17 Pink Gmbh Thermosysteme System and method for connecting electronic assemblies and related film transfer unit

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5419363A (en) * 1977-07-13 1979-02-14 Sharp Corp Die bonding method of semiconductor devices
DE3414065C2 (en) * 1984-04-13 1989-07-27 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De
JPH0346242A (en) * 1989-07-13 1991-02-27 Fujitsu Ltd Manufacture of semiconductor device
EP0242626B1 (en) * 1986-04-22 1991-06-12 Siemens Aktiengesellschaft Method for mounting electronic components on a substrate
JPH0663939A (en) * 1991-10-11 1994-03-08 Denki Kagaku Kogyo Kk Tablet of epoxy resin composition
DE19734317A1 (en) * 1997-07-29 1999-02-18 Aumer Horst Dipl Ing Fh Die bonder for semiconductor manufacturing
EP0949662A2 (en) * 1998-03-27 1999-10-13 Supersensor (Proprietary) Limited Die transfer method and system
JP5419363B2 (en) 2008-02-27 2014-02-19 株式会社ユニバーサルエンターテインメント Game machine

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5419363A (en) * 1977-07-13 1979-02-14 Sharp Corp Die bonding method of semiconductor devices
DE3414065C2 (en) * 1984-04-13 1989-07-27 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De
EP0242626B1 (en) * 1986-04-22 1991-06-12 Siemens Aktiengesellschaft Method for mounting electronic components on a substrate
JPH0346242A (en) * 1989-07-13 1991-02-27 Fujitsu Ltd Manufacture of semiconductor device
JPH0663939A (en) * 1991-10-11 1994-03-08 Denki Kagaku Kogyo Kk Tablet of epoxy resin composition
DE19734317A1 (en) * 1997-07-29 1999-02-18 Aumer Horst Dipl Ing Fh Die bonder for semiconductor manufacturing
EP0949662A2 (en) * 1998-03-27 1999-10-13 Supersensor (Proprietary) Limited Die transfer method and system
JP5419363B2 (en) 2008-02-27 2014-02-19 株式会社ユニバーサルエンターテインメント Game machine

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8662377B2 (en) 2004-04-22 2014-03-04 Semikron Elektronik Gmbh & Co., Kg Method for securing electronic components to a substrate
DE102005047566C5 (en) * 2005-10-05 2011-06-09 Semikron Elektronik Gmbh & Co. Kg Arrangement with a power semiconductor component and with a housing and manufacturing method thereof
DE102005047567B3 (en) * 2005-10-05 2007-03-29 Semikron Elektronik Gmbh & Co. Kg Power semiconductor module comprises a housing, connecting elements and an electrically insulated substrate arranged within the housing and semiconductor components with a connecting element and an insulating molded body
DE102005058794A1 (en) * 2005-12-09 2007-06-14 Semikron Elektronik Gmbh & Co. Kg Device and clocked process for pressure sintering
EP1796137A2 (en) 2005-12-09 2007-06-13 Semikron Elektronik GmbH & Co. KG Patentabteilung Apparatus and clocked method for pressure sintering
WO2008003308A1 (en) 2006-07-07 2008-01-10 Technische Universität Carolo-Wilhelmina Method for attaching electronic components to a support by means of pressure sintering and circuit arrangement
DE102006031844A1 (en) * 2006-07-07 2008-01-10 Technische Universität Braunschweig Carolo-Wilhelmina Method for fastening electrical components to a carrier by pressure sintering and circuit arrangement
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EP1956647A1 (en) 2007-02-10 2008-08-13 SEMIKRON Elektronik GmbH & Co. KG Switch device with connecting device and corresponding production method
DE102007006706B4 (en) * 2007-02-10 2011-05-26 Semikron Elektronik Gmbh & Co. Kg Circuit arrangement with connecting device and manufacturing method thereof
EP1993133A3 (en) * 2007-05-12 2010-09-08 SEMIKRON Elektronik GmbH & Co. KG Sintered high performance semiconductor substrate and corresponding production method
EP1993132A3 (en) * 2007-05-12 2010-09-08 SEMIKRON Elektronik GmbH & Co. KG High performance semiconductor substrate with metal contact layer and corresponding production method
US9768036B2 (en) 2007-05-12 2017-09-19 Semikron Elektronik Gmbh & Co., Kg Power semiconductor substrates with metal contact layer and method of manufacture thereof
US7851334B2 (en) 2007-07-20 2010-12-14 Infineon Technologies Ag Apparatus and method for producing semiconductor modules
US8110925B2 (en) 2007-07-26 2012-02-07 Semikron Elektronik Gmbh & Co., Kg Power semiconductor component with metal contact layer and production method therefor
DE102007022338B4 (en) * 2007-07-26 2013-12-05 Semikron Elektronik Gmbh & Co. Kg Manufacturing method for a power semiconductor device with metal contact layer
DE102007054710B3 (en) * 2007-11-16 2009-07-09 Semikron Elektronik Gmbh & Co. Kg Method for producing a semiconductor module
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DE102008009510B3 (en) * 2008-02-15 2009-07-16 Danfoss Silicon Power Gmbh Method for low-temperature pressure sintering
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DE102010011719A1 (en) 2010-03-17 2011-09-22 Semikron Elektronik Gmbh & Co. Kg Method for producing an electrically conductive connection of a contact with a mating contact
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