DE102004017787A1 - Method and test device for testing integrated circuits - Google Patents

Method and test device for testing integrated circuits

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Publication number
DE102004017787A1
DE102004017787A1 DE200410017787 DE102004017787A DE102004017787A1 DE 102004017787 A1 DE102004017787 A1 DE 102004017787A1 DE 200410017787 DE200410017787 DE 200410017787 DE 102004017787 A DE102004017787 A DE 102004017787A DE 102004017787 A1 DE102004017787 A1 DE 102004017787A1
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Germany
Prior art keywords
output signal
test
change
predetermined condition
predetermined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE200410017787
Other languages
German (de)
Inventor
Reiner Diewald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Automotive GmbH
Original Assignee
Atmel Germany GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Germany GmbH filed Critical Atmel Germany GmbH
Priority to DE200410017787 priority Critical patent/DE102004017787A1/en
Publication of DE102004017787A1 publication Critical patent/DE102004017787A1/en
Withdrawn legal-status Critical Current

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2894Aspects of quality control [QC]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2882Testing timing characteristics
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2893Handling, conveying or loading, e.g. belts, boats, vacuum fingers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31718Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis

Abstract

A method of testing integrated circuits (12) providing an analog output signal (AS; 44,46,48; 58,60,62) is provided comprising the steps of: generating a change in an input signal (40) of the integrated circuit (12); 12), detecting a change in the output signal (AS; 44, 46, 48, 58, 60, 62) of the integrated circuit (12) triggered by the change of the input signal (40) when a predetermined condition (VB) is satisfied and comparing the detected output signal (M; AS; 44,46,48; 58,60,62) with at least one predetermined comparison criterion. The method is characterized in that the predetermined condition (VB) is derived individually for each integrated circuit (12) from a time behavior (ZV) of the output signal (AS; 44, 46, 48; 58, 60, 62).

Description

  • The The invention relates to a method for testing integrated circuits, which is an analog output signal supplied, with the steps: generating a change of an input signal an integrated circuit, detecting a change of an output signal the integrated circuit caused by the change of the input signal triggered was, if a predetermined condition is met, and comparing the detected output signal with at least one predetermined comparison criterion.
  • Furthermore The invention relates to an integrated circuit test device with Handling means for contacting integrated circuits, an input signal generator and an output signal acquisition and evaluation unit, wherein the test device a change an input signal of an integrated circuit and generates a change an output signal of the integrated circuit detected by the change of Input signal triggered was when a predetermined condition is met, and the detected output signal compared with at least one predetermined comparison criterion.
  • One such method and such a test device are known per se. Integrated circuits are produced in millions. For some Applications, such as integrated circuits for safety-related Functions such as the control of an airbag triggering, becomes a zero error rate required. Therefore, every single integrated circuit needs to be one Application is provided after manufacture to its proper function checked become. Even in less safety-critical applications, the Production are at least randomly tested, which in the above numbers still very high numbers of integrated circuits to be tested results.
  • at The above-mentioned known method is used as a predetermined condition the requirement used that after a change of the input signal a fixed waiting time must elapse before a measured value of an output signal response is detected. This wait is wearing a series-specific delay bill, with the integrated circuits respond to a stimulating input signal change. The real ones delays which can occur in individual circuits, may be due to variations the component parameter at different representatives of a series of have integrated circuits of the same series, so some integrated circuits integrated earlier and others Circuits later to an input signal change react.
  • Around a sure distinction between good and bad ones to enable integrated circuits the fixed waiting time must be so predetermined that even in the frame the allowed variations slower, but still sufficient fast-response integrated circuits still recognized as good become. It follows that measured values for within the allowed variations quickly reacting components are taken up unnecessarily late what, though for the quality of Measurement is uncritical, but that for a test of a large number Measurement time required by similar integrated circuits extended. This extension the test time reduces the throughput of a single test device, so for a predetermined rate at which to test integrated circuits more test devices must be provided. The extended measuring time must be through higher Investment for more testing devices, related Handling systems, installation space, Power supply, etc. are collected.
  • In front In this background, the object of the invention in the specification a method and a test device with which the above-mentioned disadvantages at least be reduced.
  • These Task is characterized by a method of the type mentioned by solved, that the predetermined condition individually for each integrated circuit is derived from a time behavior of the output signal.
  • Further This object is achieved in a test device of the aforementioned Kind solved by that the test device individually determines the predetermined condition for each integrated one Derives circuit from a timing of the output signal.
  • By these features, the object of the invention is completely solved. By deriving IC individual predetermined conditions from the individual timing of the integrated circuit output, faster responding integrated circuits may be tested earlier in a test than in the prior art method. As a result, averaging over many test cycles results in an overall shorter test time, so that the amount of tested integrated circuits handled by a test device increases. As a result, with a given amount of integrated circuits to be tested, the number of test devices, including the associated handling means, can be reduced, reducing the footprint of the entire test equipment and the average cost of testing each integrated circuit lowers.
  • With Looking at embodiments of the method is preferred that the Output signal after a change of the input signal continuously monitored and that the predetermined condition is then satisfied, when the output signal runs in a predetermined range of values.
  • These Design is for integrated circuits suitable in which a comparatively strong Reaction of the output signal occurs. The running in of the output signal in a predetermined range of values assumes that the output signal first outside of the range of values. Running in therefore indicates that there is one at all Reaction occurs, which may already indicate a functioning IC can be evaluated.
  • alternative or in addition But from this point on there is also a certain waiting time to calm down to wait for the output signal. The individual test time is then the sum of the waiting time and the previous, individual circuit Time span between stimulating the integrated circuit and the running of the output signal in the predetermined value range together.
  • at In a preferred embodiment, the predetermined condition applies therefore as fulfilled, if after running the output signal in a predetermined Range of values a predetermined minimum waiting time has expired.
  • Further it is preferred that the predetermined condition is then satisfied, if after entering the output signal in the predetermined Range of values a slope of a curve of the output signal over the Time falls below a predetermined threshold.
  • These Design has the additional Advantage that both time periods, ie the time span between a Stimulate the circuit and run into the value range as well as the time between running in and recording the actual measured value, ie the value of the output signal the time when the predetermined condition is met, are individual to the circuit. This results in a further shortening of the Test time and thus a further increase in the rate at which a single test device tests integrated circuits.
  • Prefers is also that the predetermined condition is then satisfied, if after entering the output signal in the predetermined Range of values a percentage change of the output signal exceeds a predetermined threshold.
  • Also in this embodiment, both of the time periods mentioned above individual circuit, so that here comparable advantages result. The difference between the two designs exists in that the slope of the difference of two output signal values depends while the percentage change as a function of the quotient of both output signal values.
  • A Another preferred embodiment is characterized in that the predetermined condition is then satisfied if one by a change triggered by the input signal percentage change of the output signal exceeds a predetermined threshold.
  • These similar at first glance Embodiment differs from those listed above Embodiments in that it does not require that the output signal at the beginning outside of the predetermined value range lies. In circuits where the output signal is in the predetermined value range from the beginning, can be determined, if at all a sufficient change in response to stimulation. This embodiment is thus particularly suitable for integrated circuits with small output signal amplitudes.
  • With Looking at embodiments of the test device is preferred that the test device the output signal after a change of the input signal continuously monitored and evaluates the predetermined condition as satisfied when the output signal enters a predetermined range of values.
  • Prefers is also that the test device the output signal after a change of the input signal continuously monitored and then evaluates the predetermined condition as fulfilled, if any a change triggered by the input signal percentage change of the output signal exceeds a predetermined threshold.
  • Further it is preferred that the test device be at least one of the above mentioned embodiments of the method performs.
  • These Embodiments of the test device have the advantages of the corresponding Method and the associated Configurations. Further advantages emerge from the description and the attached Characters.
  • It is understood that the abovementioned and those still to be explained below Characteristics can be used not only in the specified combination, but also in other combinations or in isolation, without departing from the scope of the present invention.
  • drawings
  • embodiments The invention are illustrated in the drawings and in the following description explained. In each case, in schematic form:
  • 1 a test device for testing integrated circuits;
  • 2 Waveforms that outputs and / or detects such a test device in the context of first embodiments over time;
  • 3 Waveforms that outputs and / or detects such a test device in the context of second embodiments over time;
  • 4 a flowchart as an embodiment of a method according to the invention in general form; and
  • 5 a further flowchart with embodiments of the method according to the 4 ,
  • 1 shows a test device 10 for testing integrated circuits 12 with a gripping device 14 , Feed conveyors 16 a discharge transport means 18 for integrated circuits that meet given requirements, an evacuation transport means 20 for integrated circuits that do not meet given requirements, a carrier device 22 , an input signal generator 32 an output signal acquisition and evaluation unit 34 , a control device 36 and a control connection 38 , Tested integrated circuits 12 are from the feed conveyor 16 , For example, a conveyor belt, and supplied by the movable in the X and Y direction gripping device 14 captured and to the carrier plate 22 transported. The carrier plate 22 has input signal contacts 24 . 26 and output signal contacts 28 . 30 on. The input signal contacts 24 . 26 are with the input signal generator 32 connected and the output signal contacts 28 . 30 are with the output signal acquisition and evaluation unit 34 connected.
  • The input signal generator 32 stimulates those on the contacts 24 . 26 . 28 . 30 remote integrated circuit 12 which responds by changing its output signal. The output signal change is made by the output signal acquisition and evaluation unit 34 recorded and evaluated. Depending on whether the tested integrated circuit 12 meets predetermined requirements or not met, it is from the gripping device 14 to the discharge transport means 18 or the removal transport 20 transported. The gripping device 14 , the feed transport 16 and the discharge transport means 18 and 20 be from a controller 36 controlled by a control connection 38 , for example a bus system, with the input signal generator 32 and / or the output signal acquisition and evaluation unit 34 communicated. The test device 10 to 1 is characterized by having the predetermined condition, upon entry of which a measured value of the output signal of the integrated circuit for evaluating the function of the integrated circuit 12 is derived from a timing of the output signal derived. Embodiments of corresponding procedures will be described below with reference to the 2 to 5 explained.
  • This shows the 2 in its part a) the time course of a stimulating input signal, in its part b) individually different reactions of different integrated circuits 12 a series over time t and in its part c) individual test times for integrated circuits 12 , the output signals after 2 B) deliver. The test begins with a change in the input signal generator 32 supplied input signal 40 at time t_0. After the expiry of a minimum waiting time, the active test, ie a continuous monitoring of the output signal of the integrated circuit to be tested, becomes active at the instant t_1 12 and thus the timing of the output signal started. The continuous monitoring can be realized by periodic sampling or a continuous evaluation. The time t_1 is in the 2 by the falling level of the signal 42 in the 2c) which marks the beginning of the active test time.
  • 2 B) shows output signal curves 44 . 46 and 48 of three different integrated circuits 12 , which differ in their reaction rate. Of the three considered output waveforms 44 . 46 . 48 the course reacts 48 fastest on an input signal change at time t 0 and runs at time t_1_48 in a predetermined range of values I_1 into it. In one embodiment of the invention, this running into the value range I_1 can already be assessed as fulfilling the predetermined condition. Within the scope of this embodiment, the test for this particular IC can be terminated at this time.
  • In the context of a further embodiment, however, a certain amount of time is still waited until the time t_2_48, and then the present value of the output signal 48 as a measured value for an assessment of the integrated circuit 12 used. In the context of this embodiment, the predetermined applies Condition is then fulfilled when the time t_2_48 = t_1_48 + Δ_t is reached. In this case, the test measurement is ended, which is in the
  • 2c) through the rising flank 50 is represented. Alternatively, the time t_2_48 may also be evaluated by evaluating the slope of the signal 48 be determined. The initially large slope after the time t_1_48 decreases with increasing approach to the time t_2_48, so that falling below a corresponding threshold value can define the time t_2_48.
  • Quite analogous to these considerations for the output signal 48 can also output signal waveforms 46 and 44 to be evaluated when taking measurements on other integrated circuits 12 to be obtained. That by the course 46 represented output signal 46 runs at the time t_1_46 in the value range I_1 and is, for example, at time t_2_46 to assess the functionality of the integrated circuit 12 detected. Accordingly, the test measurement for this integrated circuit 12 at the time t_2_46 be canceled, which is in the 2c) through the rising flank 52 is represented.
  • Accordingly, from the times t_1_44, to which the output signal 44 into the value range I_1, and the associated time t_2_44, at which a measured value is recorded, a test end, which is triggered by the rising edge 54 in 2c) is represented.
  • The rising flank 56 in the 2 represents an inevitable termination of the test at a time t_max. When the predetermined condition for detecting an output signal 44 . 46 . 48 a special integrated circuit 12 At this time t_max is not fulfilled, for example, then the current value of the output signal 44 . 46 48 be used as a measured value for an assessment of the functionality and be compared with predetermined limits. The provision of the maximum test time t_max prevents a possibly non-functional IC from passing the test device 10 blocked for an unacceptably long time.
  • At the same time, the time t_max defines an example of the point in time at which the measured values for each individual IC 12 were recorded in the known method mentioned at the outset. The entire measuring time of a variety of integrated circuits 12 is therefore limited by the known method by a corresponding multiple of the time period between the times t_1 and t_max down. In contrast, a comparable (theoretical) lower limit for a test method according to the invention results as the sum of the distances from each of the flanks 50 . 52 and 54 at time t_1, which can be seen to a smaller sum and thus to an overall shortening of the test time for a variety of integrated circuits 12 leads.
  • As an alternative to the embodiments already described, the assessment of an integrated circuit 12 also be done by after the running in of the output signal 44 . 46 . 48 in the predetermined value range I_1 a percentage change of the output signal 44 . 46 . 48 determined and compared with a predetermined threshold. The percentage change can be, for example, to the value of the output signal 44 . 46 . 48 be normalized at the time of entering into the predetermined value range I_1.
  • 3 shows waveforms 58 . 60 . 62 individual integrated circuits 12 which lie in the allowed, predetermined value range I_1 right at the beginning of the test. In this case, a reliable judgment can be achieved by the output waveforms 58 . 60 . 62 after time t_1 and monitored for the occurrence of a percentage change exceeding a predetermined threshold. The percentage change is advantageously at the initial level of the output waveforms 58 . 60 . 62 based. Once the change of the output signal 58 . 60 . 62 exceeds a percentage threshold, which is in the 3 at the times t_1_58, t_1_60, t_1_62 is the case, the circuit in question 12 be considered functional.
  • Alternatively, at these times, the value of the output signal 58 . 60 . 62 the relevant circuit 12 are detected and compared with predetermined limits, which may be identical or deviate from the limits of the predetermined range of values I_1, are compared.
  • In the context of a further embodiment, the following with reference to the output signal 58 is explained, there is still a wait until the time t_2_58. The then present value of the output signal 58 is used as a measured value for an evaluation of the integrated circuit 12 used. In the context of this embodiment, the condition is then considered fulfilled when the time t_2_58 = t_1_58 + Δ_t is reached. In this case, the test measurement is ended, which is in the 3c) through the rising flank 64 is represented. Alternatively, the time t_2_58 can also be evaluated by evaluating the slope of the signal 58 be determined. The large slope after the time t_1_58 decreases with increasing approach to the time t_2_58, so that falling below a corresponding threshold defines the time t_2_58 can. Analogous to these considerations to the output signal curve 58 can also the output curves 60 and 62 be evaluated.
  • Accordingly, the test of an integrated circuit ends 12 in the method according to 3 each with rising edges 64 . 66 and 68 , all in time before the rising edge 56 lie, which represents an inevitable termination of the test at time t_max.
  • 4 shows an embodiment of a method according to the invention in a general form, with which the waveforms in the 2 and 3 are displayed, achieved and evaluated. The procedure is in the test device 10 to 1 through the composite of the controller 36 with the input signal generator 32 and the output signal detection and evaluation unit 34 carried out. This is done in one step 70 Initially a test is started when the gripping device 14 an IC 12 on the carrier plate 22 has dropped off. After discontinuing an IC 12 on the contacts 24 . 26 . 28 . 30 an input signal change is triggered and in step 72 the time behavior ZV of the resulting output signal AS; 44 . 46 . 48 ; 58 . 60 . 62 evaluated. Subsequently, in step 74 set a predetermined condition VB as a function of the timing ZV.
  • With continuous further detection of the output signal AS; 44 . 46 . 48 ; 58 . 60 . 62 is in the step 76 checks if the predetermined condition is satisfied. As long as this is not the case, a branching into the step takes place 78 in which it is checked whether the maximum test time t_max has been exceeded. If this query is denied in the step 78 gets the loop out of the steps 76 and 78 go through until either the predetermined condition in step 76 is met or the maximum test time in the step 78 is exceeded. In both cases, branching to step closes 80 in which a measured value M of the output signal AS; 44 . 46 . 48 ; 58 . 60 . 62 the integrated circuit 12 is recorded.
  • The recorded measured value M is in step 82 then checks whether it is an element of an allowed value range I_2. It is understood that I_2 with the in connection with the 2 and 3 explained range of values I_1 may be identical or may differ from it. If the measured value M is in the interval I_2, the tested IC 12 is considered functional and it becomes the step 84 Branched, the removal of the sufficiently functional integrated circuit 12 via the discharge transport means 18 triggers. Otherwise, that is, if the measured value M is not within the interval I_2, the step goes to 86 branches, in which, for example, a removal of the tested IC 12 via the discharge transport means 20 he follows.
  • After this presentation of a very general method will be described below with reference to the 5 a more detailed embodiment of a method described by which the waveforms after the 2 as well as the waveforms after the 3 achieve and evaluate. After starting the program in step 70 First, a count variable n is set to the value 1. This is followed by the step 72 the evaluation of the time behavior ZV of the output signal AS; 44 . 46 . 48 ; 58 . 60 . 62 an integrated circuit 12 at. The evaluation of the time behavior ZV is in the 5 shown in more detail and begins with a sub-step 90 of the step 72 , which checks whether the related to the 2 and 3 explained minimum waiting time until time t_1 has elapsed. Only when this is the case is a branching to the sub-step 92 in which an output signal AS; 44 . 46 . 48 ; 58 . 60 . 62 the integrated circuit 12 is recorded. This is followed by a partial step 94 in which the output signal AS; 44 . 46 . 48 ; 58 . 60 . 62 is checked to see if it is in the predetermined value range I_1. If this is not the case, what in the 2 corresponds to the output signal behavior described, a step closes 96 in which one of the in connection with the 2 explained predetermined conditions VB is set. In addition, in step 96 the value of the count variable n increases by 1.
  • Then in step 98 checks if the maximum test time t_max has expired. As long as this is not the case, becomes the sub-step 92 branched back, in which a new output signal AS; 44 . 46 . 48 is recorded. This is followed by the step again 94 ie, a determination as to whether the value AS lies in the interval I_1. As long as this is not the case and the maximum test time t_max is not exceeded, the loop becomes out of the steps 92 . 94 . 96 . 98 run through, wherein the value of the count variable n increases in each case and thus always deviates from n = 1. Only when in step 94 it is determined that the output signal AS; 44 . 46 . 48 into the allowed value range I_1, the loop is exited and, since the count variable n is greater than 1 in this case, by negation of the corresponding query in the step 102 the step 104 achieved in which it is checked whether the predetermined condition VB is satisfied.
  • As long as this is not the case, a branching out of the step takes place 104 in the step 106 in which it is checked whether the maximum test time t_max has been reached. Only when the predetermined condition in step 104 is detected as fulfilled or if the predetermined maximum test time t_max in step 106 is detected as exceeded, a branch takes place in the step 80 already related to the 4 has been explained and the the reading recording and branching in the steps 82 . 84 . 86 of the 4 concerns. The step 80 is also achieved when the loop out of the steps 92 . 94 . 96 and 98 by exceeding the maximum test time t_max from the step 98 is left out.
  • If the output signal at the time t_1 in the allowed range I_1, as the ratios of 3 corresponds, results in a slightly different sequence of the procedure. In this case, the query is in the sub-step 94 of the step 72 the first time you walk through it and the step 102 in which it is checked whether the count variable n has the value 1. As this is only a single pass through the previous step 94 the case is, the query becomes 102 in this case, affirmative and it closes the step 108 in which one of the in connection with the 3 explained predetermined conditions VB is set. Subsequently, in step 110 an output signal AS; 58 . 60 . 62 taken and in step 112 then evaluated whether the set predetermined condition VB is satisfied. As soon as the predetermined condition VB is fulfilled, branching into the step also ensues in this embodiment of the method 80 for receiving a measured value for the output signal AS; 58 . 60 . 62 as a basis for an assessment of the functionality of the integrated circuit 12 at.
  • As long as the predetermined condition is not met and in the step 114 checked maximum time t_max has not yet been reached, the sequence of steps 110 . 112 and 114 go through repeatedly. Similar to the previously described embodiment, this loop is either left by the fact that the predetermined condition in step 112 is detected as being met or by the fact that the maximum test time t_max in step 114 is detected as exceeded.

Claims (10)

  1. Method for testing integrated circuits ( 12 ) having an analog output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ), comprising the steps of: generating a change of an input signal ( 40 ) of the integrated circuit ( 12 ), Detecting a change in the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) of the integrated circuit ( 12 ) caused by the change of the input signal ( 40 ) has been triggered when a predetermined condition (VB) is satisfied and comparing the detected output signal (M; AS; 44 . 46 . 48 ; 58 . 60 . 62 ) with at least one predetermined comparison criterion, characterized in that the predetermined condition (VB) is determined individually for each integrated circuit ( 12 ) from a time behavior (ZV) of the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) is derived.
  2. Method according to Claim 1, characterized in that the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) after a change of the input signal ( 40 ) is continuously monitored and that the predetermined condition (VB) is considered satisfied when the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) runs into a predetermined value range (I_1).
  3. Method according to Claim 2, characterized in that the predetermined condition (VB) is deemed to be satisfied if, after running in the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) in the predetermined value range (I_1) a predetermined minimum waiting time has expired.
  4. Method according to Claim 2, characterized in that the predetermined condition (VB) is deemed to be satisfied if, after running in the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) in the predetermined value range (I_1) a slope of a curve of the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) over the time (t) falls below a predetermined threshold.
  5. Method according to Claim 2, characterized in that the predetermined condition (VB) is deemed to be satisfied if, after running in the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) in the predetermined value range (I_1) a percentage change of the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) exceeds a predetermined threshold.
  6. Method according to Claim 1, characterized in that the predetermined condition (VB) is deemed to be fulfilled if a change is caused by a change in the input signal (VB). 40 ) triggered percentage change of the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) exceeds a predetermined threshold.
  7. Test device ( 10 ) for integrated circuits ( 12 ) with handling means ( 14 . 16 . 18 . 20 . 22 ) for contacting integrated circuits ( 12 ), an input signal generator ( 32 ) and an output signal acquisition and evaluation unit ( 34 ), wherein the test device ( 10 ) a change of an input signal ( 40 ) an integrated circuit ( 12 ), and a change of an output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) of the integrated circuit ( 12 ) detected by the change of the input signal ( 40 ) was triggered when a predetermined condition (VB) is satisfied and the detected output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) is compared with at least one predetermined comparison criterion, characterized in that the test device ( 10 ) the predetermined condition individually for each integrated circuit ( 12 ) from a time behavior (ZV) of the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ).
  8. Test device ( 10 ) according to claim 7, characterized in that the test device ( 10 ) the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) after a change of the input signal ( 40 ) continuously monitors and evaluates the predetermined condition (VB) as fulfilled when the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) runs in a predetermined value range (I_1).
  9. Test device ( 10 ) according to claim 7, characterized in that the test device ( 10 ) the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) after a change of the input signal ( 40 ) continuously monitors and then evaluates the predetermined condition (VB) as fulfilled by a change of the input signal (VB). 40 ) triggered percentage change of the output signal (AS; 44 . 46 . 48 ; 58 . 60 . 62 ) exceeds a predetermined threshold.
  10. Test device ( 10 ) according to at least one of claims 8 or 9, characterized in that the test device ( 10 ) at least one of the methods according to claims 3 to 5 executes.
DE200410017787 2004-04-02 2004-04-02 Method and test device for testing integrated circuits Withdrawn DE102004017787A1 (en)

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DE200410017787 DE102004017787A1 (en) 2004-04-02 2004-04-02 Method and test device for testing integrated circuits
EP05006862A EP1584933A1 (en) 2004-04-02 2005-03-30 Method and device for testing of integrated circuits
US11/095,488 US7199601B2 (en) 2004-04-02 2005-04-01 Method and testing apparatus for testing integrated circuits
US11/710,466 US7408375B2 (en) 2004-04-02 2007-02-26 Method and testing apparatus for testing integrated circuits

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JP6536111B2 (en) * 2015-03-23 2019-07-03 セイコーエプソン株式会社 Electronic component conveying apparatus and electronic component inspection apparatus

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US7199601B2 (en) 2007-04-03
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US7408375B2 (en) 2008-08-05

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