DE102004007196A1 - Edge closure for a semiconductor element, comprises at least one semiconductor member with two electrodes, and a polarised edge material - Google Patents

Abstract

An edge closure for a semiconductor element comprises at least one semiconductor member (1) with two electrodes (3,4). A voltage is applied between the electrodes so a charged zone is formed. At least one edge region has a material (9) which is polarised and has a compensating charge for the charged zone. The material has a high dielectric constant and consists of e.g. hafnium oxide, zirconium oxide, titanium oxide or lanthanum oxide. The material is applied onto an insulating layer (12). The edge region has at least one field plate (7).

Description

The The present invention relates to an edge termination for a semiconductor device with a semiconductor body, on which at least two electrodes are provided, between which a voltage can be applied, so that in the semiconductor body, a space charge zone arises.

Semiconductor devices and have groupings of similar semiconductor devices necessarily due to their finite extent a border area, in which, as further below explained will be increased electric field strengths occur. Therefore, in semiconductor devices to which higher voltages be created and thus by a high dielectric strength should designate the edge area in a suitable manner so structured that will be there for those too reaches the semiconductor device provided breakdown voltage becomes.

A Another task of peripheral areas of semiconductor devices is to be seen in that they provide electrical isolation between adjacent semiconductor devices or in the case of edge-layer semiconductor components an electrical insulation to a saw edge guarantee.

The Achievement of the intended breakdown voltage in the edge region of a Semiconductor device is problematic because its blocking pn junction there inevitably a curvature which leads to an increase the electric field strength leads, which in turn results in a lowering of the breakdown voltage.

The Structuring the edge region of a semiconductor device for the achievement a high breakdown voltage is thus of great importance. Of course, should solutions This problem also ensure good long-term stability and, for example insensitive to inevitably occurring Be interfacial charges.

• (a) Bevorzugt werden floatende Feldringe eingesetzt (vgl. hierzu B. J. Baliga: Modern Power Devices (John Wiley & Sons, 1987)). Solche floatende Feldringe sehen, wie in 4 gezeigt ist, in welcher eine Diode mit einem n^–-leitenden Halbleiterkörper 1, einer p-leitenden Anodenzone 2, einer Kathode (K) 3 und einer Anode (A) 4 dargestellt ist, ringförmige, voneinander getrennte Dotierungsgebiete 5 um einen sperrenden pn-Übergang 6 zwischen der Anodenzone 2 und dem n^–-leitenden Halbleiterkörper 1 vor. Diese Dotierungsgebiete sind bei einer p-leitenden Anodenzone 2 p-leitend und in ihrem Potenzial nicht festgelegt. Das Potenzial der Dotierungsgebiete 5 stellt sich zwischen den Werten des Potenzials an den beiden Elektroden 3, 4 ein, an welchen die Sperrspannung für den pn-Übergang 6 anliegt. Die die Feldringe bildenden Dotierungsgebiete 5 werden im Sperrfall nicht ausgeräumt und führen zu einer lateralen Aufweitung der sich im Halbleiterkörper 1 ausbreitenden Raumladungszone und damit zu einer Verringerung der dort auftretenden elektrischen Feldstärke. Die Aufteilung des Potenzials zwischen den die Feldringe bildenden Dotierungsgebieten 5 und damit die Sperrfähigkeit der Diode hängen allerdings deutlich von Oberflächenladungen auf dem Halbleiterkörper 1 oder von in einer dort vorgesehenen Isolierschicht enthaltenen so genannten Oxidladungen ab, was die Langzeitstabilität eines derartigen Randabschlusses beeinträchtigt (vgl. hierzu auch H. Yilmaz: Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions, IEEE Trans. on Electron Devices, Vol. ED-38, Nr. 7 (1991), S. 1666–1675).
• (b) Ein anderer Randabschluss für hochsperrende Halbleiterbauelemente verwendet Feldplatten (vgl. Baliga, S. 116 ff.). Bei diesen Feldplatten handelt es sich um Schichten mit hoher Leitfähigkeit aus beispielsweise Metall oder polykristallinem Silizium. Diese Feldplatten sind mit einer der Elektroden verbunden und befinden sich in bzw. auf einer auf der Oberfläche des Halbleiterkörpers vorgesehenen Isolierschicht aus vorzugsweise Siliziumdioxid. Eine derartige Feldplatte 7 ist in 5 für das Beispiel einer Diode gezeigt. Die Feldplatten, wie beispielsweise die Feldplatte 7 in 5, führen das Potenzial der Elektrode, also im vorliegenden Beispiel das Potenzial der Anode 4, lateral über den pn-Übergang 6 hinaus, wobei der Abstand der Feldplatte zum Halbleiter mit zunehmender Distanz zur Anode 4 zunimmt. Dadurch wird – ähnlich wie bei floatenden Feldringen – eine seitliche Aufweitung der Raumladungszone erreicht. Feldplatten werden auch bei Driftstrecken von lateralen Transistoren eingesetzt. Es sei darauf hingewiesen, dass bei Feldplatten die Abhängigkeit von Oberflächenladungen geringer als bei Feldringen ist. Jedoch werden für hochsperrende Halbleiterbauelemente mit Feldplatten im Randbereich für höhere Spannungen relativ dicke Isolierschichten unter den Feldplatten benötigt, was einen erheblichen Fertigungsaufwand bedeutet. So werden für Spannungen von etwa 1200 V maximale Schichtdicken der Isolierschicht unterhalb der Feldplatte von etwa 8 μm als notwendig erachtet.
• (c) Eine weitere Möglichkeit zur Erhöhung der Durchbruchspannung im Randbereich von hochsperrenden Halbleiterbauelementen besteht in der Verwendung einer so genannten "Junction Termination Extension" (JTE), bei der es sich um eine niedrig dotierte laterale Fortsetzung des hochdotierten Teiles eines pn-Überganges handelt (vgl. hierzu Baliga, Seiten 113 ff., und Yilmaz). Eine solche JTE ("Übergangsabschlusserweiterung") 8 ist in Strichlinien schematisch in 5 angedeutet, wobei die Feldplatte 7 in diesem Fall fehlen kann. Die JTE wird im Sperrfall zu einem wesentlichen Teil oder ganz an Ladungsträgern ausgeräumt und enthält somit als Dotierung etwa die Durchbruchsladung. Die Dotierung kann lateral auch variieren (vgl. US 4 672 738 ) und wird dann als "VLD-Struktur" (VLD = Variation der lateralen Dotierung) bezeichnet. Bei lateralen Transistoren ist für die JTE auch die Bezeichnung "Drain Extension" (Drainerweiterung) üblich. Zu Strukturen wie JTE und VLD ist auch noch RESURF (Reduced Surface Field; reduziertes Oberflächenfeld) zu zählen (vgl. hierzu auch P. Walker et al.: A numerical analysis of the resurf structure, IEEE Proc. Vol. 132, Pt. I, Nr. 6 (1985), S. 285–290). Alle hier abgehandelten Strukturen, also die JTE-Struktur, die VLD-Struktur und die Resurf-Struktur sind gegenüber Grenzflächenladungen sehr empfindlich, was ihre Einsatzmöglichkeiten begrenzt.
• (d) Schließlich dienen auch noch semiisolierende Schichten zur Erhöhung der Randfestigkeit von hochsperrenden Halbleiterbauelementen (vgl. Baliga, Seite 126 ff. und C. Mingues und G. Charitat, IEEE International Symposium on Power Semiconductor Devices and ICs Weimar, S. 137–140 (1997)). Mit solchen semiisolierenden Schichten, wie beispielsweise SIPOS-Schichten (SIPOS = Semiinsulating Polycrystalline Silicon), deren Widerstandswert viel höher ist als derjenige von beispielsweise dotiertem polykristallinem Silizium, jedoch wesentlich kleiner ist als derjenige von Siliziumdioxid, können resistiven Feldplatten realisiert werden. Diese liegen wie die Feldplatten 7 von 5 auf einer Isolierschicht über dem Randbereich des Halbleiterkörpers. Sie sind aber vorzugsweise mit beiden Elektroden, also bei einer Diode mit der Anode und mit der Kathode, verbunden und führen entsprechend der anliegenden Sperrspannung und ihrem elektrischen Widerstand einen relativ großen Leckstrom. Innerhalb einer solchen resistiven Feldplatte aus einer semiisolierenden Schicht ergibt sich ein durch die geometrische Form und gegebenenfalls eine inhomogene Verteilung des Schichtwiderstandes (vgl. hierzu EP 0 615 291 A1 ) bestimmter Potenzialverlauf, der wiederum die laterale Ausdehnung der Raumladungszone steuert. Randabschlüsse mit semiisolierenden Schichten sind wegen des vorgegebenen Potenzialverlaufs unempfindlich gegen Oberflächenladungen. Ein Nachteil von Randabschlüssen mit semiisolierenden Schichten ist aber darin zu sehen, dass der elektrische Widerstand der semiisolierenden Schichten mit der darunter liegenden Isolierschicht- und Raumladungskapazität im Halbleiterkörper ein RC-Glied bildet, dessen Zeitkonstante bei einem für einen kleinen Leckstrom notwendigen großen Wert des Widerstandes relativ groß wird. Beispielsweise ergibt sich mit einer Kapazität C = 10 pF, einem Leckstrom von 60 μA bei 600 V und einem Widerstand R = 10 MΩ eine Zeitkonstante τ = RC = 100 μs.

In particular, there have long been various approaches for structuring the edge region of a semiconductor component in order to overcome the above-indicated problem:

• (a) Floating field rings are preferably used (compare BJ Baliga: Modern Power Devices (John Wiley & Sons, 1987)). See such floating field rings as in 4 is shown, in which a diode with an n ^- -type semiconductor body 1 , a p-type anode region 2 , a cathode (K) 3 and an anode (A) 4 is shown, annular, separate doping regions 5 around a blocking pn junction 6 between the anode zone 2 and the n ^- -type semiconductor body 1 in front. These doping regions are at a p-type anode region 2 p-conductive and not defined in their potential. The potential of the doping regions 5 is between the values of the potential at the two electrodes 3 . 4 to which the blocking voltage for the pn junction 6 is applied. The doping regions forming the field rings 5 are not cleared in the blocking case and lead to a lateral expansion in the semiconductor body 1 propagating space charge zone and thus to a reduction in the electric field strength occurring there. The partitioning of the potential between the doping regions forming the field rings 5 and thus the blocking capability of the diode, however, depend significantly on surface charges on the semiconductor body 1 or from so-called oxide charges contained in an insulating layer provided there, which impairs the long-term stability of such edge termination (see also H. Yilmaz: Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions, IEEE Trans-on Electron Devices , Vol. ED-38, No. 7 (1991), pp. 1666-1675).
• (b) Another edge termination for high-barrier semiconductor devices uses field plates (see Baliga, pp. 116 et seq.). These field plates are layers of high conductivity of, for example, metal or polycrystalline silicon. These field plates are connected to one of the electrodes and are located in or on an insulating layer, preferably of silicon dioxide, provided on the surface of the semiconductor body. Such a field plate 7 is in 5 for the example of a diode shown. The field plates, such as the field plate 7 in 5 , lead the potential of the electrode, so in the present example, the potential of the anode 4 , laterally across the pn junction 6 addition, wherein the distance of the field plate to the semiconductor with increasing distance to the anode 4 increases. As a result - similar to floating field rings - a lateral expansion of the space charge zone is achieved. Field plates are also used in drift paths of lateral transistors. It should be noted that in field plates, the dependence on surface charges is less than field rings. However, for high-blocking semiconductor devices with field plates in the edge region for higher voltages relatively thick insulating layers are required under the field plates, which means a considerable manufacturing cost. Thus, for voltages of about 1200 V maximum layer thicknesses of the insulating layer below the field plate of about 8 microns than deemed necessary.
• (c) A further possibility for increasing the breakdown voltage in the edge region of high-blocking semiconductor components is the use of a so-called "junction termination extension" (JTE), which is a low-doped lateral continuation of the highly doped part of a pn junction ( see Baliga, pages 113 ff., and Yilmaz). Such a JTE ("transition completion extension") 8th is schematic in dashed lines 5 indicated, with the field plate 7 can be missing in this case. The JTE is eliminated in the blocking case to a substantial part or completely on charge carriers and thus contains as doping about the breakdown charge. The doping may also vary laterally (cf. U.S. 4,672,738 ) and is then referred to as "VLD structure" (VLD = lateral doping variation). For lateral transistors, the term "drain extension" is also common for the JTE. Structures such as JTE and VLD also include RESURF (Reduced Surface Field) (see also P. Walker et al .: A numerical analysis of the resurfure structure, IEEE Proc. Vol 132, Pt , No. 6 (1985), pp. 285-290). All of the structures discussed here, ie the JTE structure, the VLD structure and the resurf structure, are very sensitive to interfacial charges, which limits their possible uses.
• (d) Finally, semi-insulating layers also serve to increase the edge strength of high-barrier semiconductor devices (see Baliga, page 126 ff., and C. Mingues and G. Charitat, IEEE International Symposium on Power Semiconductor Devices and ICs Weimar, pp. 137-140 (1997)). With such semi-insulating layers, such as SIPOS layers (SIPOS = Semiinsulating Polycrystalline Silicon), whose resistance value is much higher than that of, for example, doped polycrystalline silicon, but substantially smaller than that of silicon dioxide, resistive field plates can be realized. These are like the field plates 7 from 5 on an insulating layer over the edge region of the semiconductor body. However, they are preferably connected to both electrodes, that is to say in the case of a diode with the anode and with the cathode, and lead according to the applied blocking voltage and its electrical resistance a relatively large leakage current. Within such a resistive field plate made of a semi-insulating layer results from the geometric shape and optionally an inhomogeneous distribution of the sheet resistance (see EP 0 615 291 A1 ) specific potential course, which in turn controls the lateral extent of the space charge zone. Edge seals with semi-insulating layers are insensitive to surface charges due to the given potential curve. However, a disadvantage of edge terminations with semi-insulating layers is the fact that the electrical resistance of the semi-insulating layers with the underlying Isolierschicht- and space charge capacity in the semiconductor body forms an RC element whose time constant at a necessary for a small leakage current large value of the resistance relative gets big. For example, with a capacitance C = 10 pF, a leakage current of 60 μA at 600 V and a resistance R = 10 MΩ, a time constant τ = RC = 100 μs results.

The above-described four fundamentally different measures (a) to (d) for designing a high-voltage-resistant edge termination can be combined in various ways. For example, it is possible to combine floating field rings according to (a) with field plates (b) or field rings (a) with a SIPOS layer (d), wherein the field rings are set to a defined potential by the SIPOS layer (cf. EP 0 615 291 A1 ). It is likewise possible to combine semi-insulating layers (d) with field plates (b), floating field rings (a) or a JTE (c) (cf. EP 0 615 291 A1 ).

The above explanations prove that so far a wealth Efforts have been made to close the margins of a Semiconductor device to make high voltage resistant. Nevertheless, show All possibilities developed so far certain disadvantages. Common to these possibilities is also the disadvantage a relatively high space requirement.

It is therefore an object of the present invention, an edge termination for a Specify semiconductor device, especially by a small Requires space, easy to manufacture and insensitive against surface charges is and can be used easily.

These Task is at a border closure according to the preamble of the claim 1 according to the invention thereby solved, in that at least one edge region of the semiconductor body is provided with a material is that by its polarization compensation charges for in the space charge zone-available charges available. As a material, the compensation charges due to its polarization provides, is preferably a material with a high dielectric constant or number, namely a so-called high-k material used.

at the edge termination according to the invention So it is on the edge region of a semiconductor device, for example a layer of a material with a high dielectric constant ε, ie a high-k material, applied. This material represents by polarization Compensation charges for the charges of the space charge zone available. Also needed one such layer significantly less space than, for example, a field ring structure.

There the polarization in the high-k material locally through that in the space charge zone influential with time variably available charges results so an optimal field distribution with small margins and Insensitivity to Interface charges, which varies in charge and quantity during the life of a Change semiconductor device can. This means, the edge termination according to the invention is not only characterized by a relatively small footprint, but also by a negligible Sensitivity to interfacial charges out.

As a high-k material, a material having a dielectric constant of, for example, 20, preferably 200 or even more preferably 1000 is used. Such materials are for example hafnium oxide (HfO ₂ ), zirconium oxide (Zo ₂ ), titanium dioxide (TiO ₂ ), lanthanum oxide (La ₂ O ₃ ) or a compound from the group of titanates, in particular barium titanate, strontium titanate or barium strontium titanate or from the groups of zirconates, niobates or tantalates.

It is easily possible the edge termination according to the invention or by one of the options given above under (a) to (d) to complete. For example, the edge termination according to the invention can still be used with floating Field rings and / or field plates and / or JTE (or VLD or resurf) and / or semi-insulating layers. Such Procedure is particularly advantageous if only materials with a moderate to the Semiconductor material of the semiconductor body used increased dielectric constant So, if so the dielectric constant of the high-k material only slightly opposite the permittivity of the semiconductor material of the semiconductor body is raised.

in the Compared to semi-insulating layers, the edge seal according to the invention is characterized a high-k material characterized in that in the case of blocking no additional Leakage current flows and the charging time constants are still low.

Essential at the edge termination according to the invention It is quite common that the compensation charges for the charges the space charge zone not by moving charge carriers in conductors or semi-insulating layers or introduced into the semiconductor body Doping regions, but by polarization of a dielectric layer to disposal be put.

Preferably is the high-k material of the edge trim according to the invention on the edge region of the semiconductor body applied and at its ends, for example, with two electrodes, in Case of a diode so with the anode and the cathode, contacted, so that these ends are at the anode potential or cathode potential are located. This prevents insulating layers or dielectrics between the respective electrode and the high-k material one be exposed to high electric field.

Preferably is the high-k material on a thin insulating layer, such as a silicon dioxide layer or a silicon nitride layer, applied, which acts as a diffusion barrier. But it is also possible that high-k material directly on the semiconductor body applied.

It is possible, the high-k material on a main surface of the semiconductor body in its edge region or on its side wall directly or via a thin insulating layer apply.

The semiconductor device according to the invention may be a pn diode, a Schottky diode, a MOS transistor, a DMOS transistor, a bipolar transistor, an IGBT, a thyristor or the like. For example, silicon, silicon carbide (SiC) or another suitable semiconductor material, eg A _III B _V , etc., can be used as the semiconductor material for the semiconductor body. The line types can also be reversed in each case.

following The invention will be explained in more detail with reference to the drawings. Show it:

1 a sectional view of a diode with a high-k field plate according to a first embodiment of the invention,

2 a sectional view of a diode with a high-k field plate according to a second embodiment of the invention,

3 a sectional view of a diode with a high-k field plate according to a third embodiment of the invention,

4 a sectional view of a diode with a conventional field ring edge and

5 a sectional view of a diode with a conventional field plate edge.

The 4 and 5 have already been explained at the beginning. In the figures, the same reference numerals are used for corresponding components.

1 shows a pn diode, where a high-k material 9 in the form of a field plate on a surface of the semiconductor body 1 located in the edge region of the diode. This high-k material 9 For example, hafnium oxide or any of the materials listed above is at one end with the anode 4 contacts and at its other end adjoins one on a heavily doped n ⁺ -type terminal area 11 arranged electrode 10 which is at cathode potential.

Optionally, in this embodiment, in addition to the field plate of the high-k material 9 in the surface region of the semiconductor body 1 one or more floating p-type field rings 5 to be available.

2 illustrates an embodiment in which the high-k material 9 through a thin insulating layer 12 of silicon dioxide or silicon nitride or other suitable insulating material from the surface of the semiconductor body 1 is disconnected.

In this exemplary embodiment, one or more floating field rings may possibly additionally be provided 5 and / or a JTE structure 8th , as indicated in dashed lines, be present.

In 3 Finally, an embodiment of a pn diode is shown with an edge termination, which is a high-k material 9 in the form of a field plate as a vertical boundary in the edge region of the semiconductor device provides. The side wall below an insulating layer 12 ' Of silicon dioxide can be easily p-doped here. In the embodiment of 3 is the high-k material 9 between the anode 4 and the cathode 3 , In this embodiment, other than vertical side walls can be used, so for example in one direction or the other obliquely inclined side walls.

Will be between the anode 4 and the cathode 3 In the above embodiments, a reverse voltage applied, so it forms in the semiconductor body 1 a space charge zone. Polarization then results in the high-k material 9 Compensating charges for the charges of the space charge zone, so that narrow curvatures of the potential lines in the region of the blocking pn junction 6 can be avoided.

1

Semiconductor body

2

anode zone

3

cathode

4

anode

5

floating field ring

6

pn junction

7

field plate

8th

JTE structure

9

high-k material

10

electrode

11

terminal region

12 12 '

insulating

13

VLD structure

A

anode electrode

K

cathode electrode

Claims (14)

Edge termination for a semiconductor component with a semiconductor body ( 1 ), on which at least two electrodes ( 3 . 4 ) are provided between which a voltage can be applied, so that in the semiconductor body, a space charge zone is formed, characterized in that at least one edge region of the semiconductor body ( 1 ) with a material ( 9 ) which, by its polarization, provides compensation charges for the charges present in the space charge zone. Edge seal according to claim 1, characterized in that that the material is a material with a high dielectric constant, a so-called high-k material. Edge seal according to claim 2, characterized that the high-k material hafnium oxide, zirconium oxide, titanium dioxide or lanthanum oxide or a compound from the group of titanates, in particular barium titanate, strontium titanate or barium strontium titanate or from the groups of zirconates, niobates or tantalates. Edge seal according to one of claims 1 to 3, characterized in that the material ( 9 ) is applied as a layer on at least one edge region. Edge seal according to one of claims 1 to 4, characterized in that the material ( 9 ) over an insulator layer ( 12 ) on the semiconductor body ( 1 ) is applied. Edge seal according to one of claims 1 to 4, characterized in that the material ( 9 ) between the potential of the at least two electrodes ( 3 . 4 ) lies. Edge seal according to one of claims 1 to 6, characterized in that in the semiconductor body ( 1 ) additionally at least one floating field ring ( 5 ) is provided. Edge seal according to one of claims 1 to 7, characterized in that in the edge region additionally at least one field plate ( 7 ) is provided. Edge termination according to one of claims 1 to 8, characterized in that in the edge region additionally a JTE structure ( 8th ) is provided. Edge termination according to one of claims 1 to 9, characterized in that in the edge region additionally a VLD structure ( 13 ) is provided. Edge seal according to one of claims 1 to 10, characterized in that the semiconductor device is a pn diode, a Schottky diode, a MOS transistor, a DMOS transistor Bipolar transistor, an IGBT or a thyristor is. Edge seal according to one of claims 1 to 11, characterized in that the semiconductor body ( 1 ) consists of silicon, silicon carbide or an A _III B _V semiconductor material. Edge seal according to one of claims 1 to 12, characterized in that the material ( 9 ) on a main surface of the semiconductor body ( 1 ) is provided. Edge seal according to one of claims 1 to 12, characterized in that the material ( 9 ) on a side surface of the semiconductor body ( 1 ) is provided.