DE102004004307A1 - Circuit arrangement for control of command sequences to a circuit unit, e.g. a memory circuit, has additional access control arrangement for checking command authorization and temporal command allocation - Google Patents

Circuit arrangement for control of command sequences to a circuit unit, e.g. a memory circuit, has additional access control arrangement for checking command authorization and temporal command allocation

Info

Publication number
DE102004004307A1
DE102004004307A1 DE200410004307 DE102004004307A DE102004004307A1 DE 102004004307 A1 DE102004004307 A1 DE 102004004307A1 DE 200410004307 DE200410004307 DE 200410004307 DE 102004004307 A DE102004004307 A DE 102004004307A DE 102004004307 A1 DE102004004307 A1 DE 102004004307A1
Authority
DE
Germany
Prior art keywords
command
unit
circuit
signal
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE200410004307
Other languages
German (de)
Inventor
Sven Boldt
Erwin Thalmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE200410004307 priority Critical patent/DE102004004307A1/en
Publication of DE102004004307A1 publication Critical patent/DE102004004307A1/en
Application status is Withdrawn legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55Detecting local intrusion or implementing counter-measures
    • G06F21/554Detecting local intrusion or implementing counter-measures involving event detection and direct action
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0754Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

The invention provides a circuit arrangement comprising a circuit unit (202) and a command bus connection unit (204) for connecting a command bus (201) to the circuit unit (202), wherein a state control device between the command bus connection unit (204) and the circuit unit (202) (100) is connected, which verifies a check of an admissibility of a via the command bus (201) in the circuit unit (202) command to be input by means of a command assignment unit (101) and a temporal assignment of the command bus (201) in the circuit unit (202) command to be entered by means of a timing allocation unit (103).

Description

  • The The present invention relates generally to a circuit arrangement, in the case of a circuit unit command sequences via a Command bus for execution be supplied by circuit functions in the circuit unit, and more particularly relates to a circuit arrangement with a state control device.
  • Specific The present invention relates to a circuit arrangement with a circuit unit and a command bus connection unit for Connecting a command bus to the circuit unit, wherein circuit functions the circuit unit via Command sequences, by means of the command bus connection unit in the circuit unit be entered, controlled or activated.
  • electronic Circuit units such as memory modules communicate with other circuit units (external circuit units) via address buses, Data buses and control buses, e.g. via command busses. The circuit units are for example designed as memory units (DRAM), wherein a selection of the memory cells provided in the circuit units via the Address bus occurs while a data exchange over the data bus is provided with commands via a control bus be dropped off; be discontinued; be deducted; be dismissed.
  • The Driving the circuit unit by settling different Commands defines the operating state of the circuit unit. Usually be transitions between different operating conditions the circuit unit defined by a state diagram. At the Issuing a corresponding command becomes circuit functions the circuit unit of a current operating state in one transferred further permitted operating state.
  • One Disadvantage of conventional The procedure for a change of an operating state is that if, in a current operating state, an unauthorized Command is issued, then such a command either not accomplished can be, because no command transition is allowed in the existing state diagram, or because one is allowed Command executed but not at the correct time, i. the command is e.g. too early discontinued. Disadvantageously, this is a termination of a Command sequence (system crash) brought about.
  • 3 shows a circuit arrangement in which a circuit unit, which is designed as a dynamic read-write memory DRAM (DRAM: dynamic random access memory) is set by means of a command sequence B in a predetermined state. For this purpose, an external command bus B e is connected to an internal command bus B i of the circuit unit DRAM by means of a connection line V. Disadvantageously, all commands present on the command bus B e are transferred to the internal command bus B i of the circuit unit DRAM via the connection line V. This means that unauthorized commands can also be issued from the command bus B e to the circuit unit and thereby cause a system error.
  • It is therefore an object of the present invention, in a transmission of instruction sequences from a command bus to a circuit unit to ensure safe operation of the circuit unit.
  • These The object is achieved by a Circuit arrangement solved with the features of claim 1.
  • Further the object is achieved by a method specified in claim 11 solved.
  • Further Embodiments of the invention will become apparent from the dependent claims.
  • One The essential idea of the invention is that between one Command bus and a command sequences to be activated or activated Circuit unit to arrange a state control device, which provides an upstream command control. The core of The invention is to provide a device between a Command bus and the circuit unit such that only then command sequences can be issued from the command bus to the circuit unit when a correspondingly exactly defined state of the circuit unit, which allows for the issuing of a specific command.
  • The the state of the circuit unit upstream state control device reflects a current operating state of the circuit unit again and has at least one command allocation unit and at least a timing allocation unit on, the content and timing of a specific command to change specify the operating state of the circuit unit.
  • Advantageously, such state control means provides complete command control prior to inputting the command sequence into the circuit unit. In purpose a check is made for a permissibility of a command sequence of the command sequence to be entered via the command bus by means of the command allocation unit, while a check of a temporal assignment of a command sequence to be entered via the command bus into the circuit unit is provided by the timing allocation unit.
  • Of the substantial advantage of a between the command bus and the to be controlled Circuit unit switched state control device consists in an elevated System security over one System crash.
  • Farther It is advantageous that a functional safety against impermissible commands elevated which is in the original one Circuit design of the circuit unit were not considered. Thus, the circuit arrangement according to the invention advantageously a possibility ready, only allowed Commands, and not all possible ones Commands as in the prior art to apply to the circuit unit.
  • The circuit arrangement according to the invention essentially comprises:
    • a) a circuit unit; and
    • b) a command bus connection unit for connecting a command bus to the circuit unit, wherein
    • c) switching functions of the circuit unit via command sequences, which are input by means of the command bus connection unit in the circuit unit, are controllable, wherein
    • d) between the command bus connection unit and the circuit unit, a state control device is connected, which a check of an admissibility of a command on the command bus in the circuit unit command of the command sequence by means of a command assignment unit and a check of a temporal assignment of the command bus to be entered into the circuit unit command the Command sequence by means of a timing allocation unit provides.
  • Furthermore, the method according to the invention for checking a command sequence to be supplied to a circuit unit essentially has the following steps:
    • a) connecting the circuit unit to a command bus by means of a command bus connection unit; and
    • b) controlling circuit functions of the circuit unit via command sequences supplied by means of the command bus, wherein
    • c) between the command bus connection unit and the circuit unit, a state control device is switched, wherein a permissibility of an over the command bus in the circuit unit command of the command sequence is checked by means provided in the state control device command assignment unit and a temporal assignment of the over the command bus in the circuit unit to be entered Command of the command sequence is checked by means provided in the state control device timing allocation unit.
  • In the dependent claims find advantageous developments and improvements of respective subject of the invention.
  • According to one preferred embodiment of the present invention is over the Command bus in the circuit unit to be entered command of the command sequence only then passed through the state control device and as passing an output command signal to the circuit unit, if both the admissibility the command as well as the time assignment of the command verified is.
  • According to one Another preferred embodiment of the present invention stored in the instruction allocation unit, a command table, the a sequence of commands corresponding to a state diagram for Operation of the circuit unit contains. Preferably, in addition the timing allocation unit, a timing allocation table stored, which has a predefinable assignment of commands according to a state diagram for operation of the circuit unit contains.
  • According to one more Another preferred embodiment of the present invention in the state control device, a linking unit for linking a command assignment signal output from the instruction allocation unit with a timing signal output from the timing allocation unit and for outputting a determination signal.
  • According to one more further preferred embodiment of the present invention has the state controller means a system time storage unit on, which is a system time depending on stores the determination signal.
  • According to one more further preferred embodiment of the present invention has the condition control means a level setting unit for adaptation a signal level of the command sequence signal to a predetermined Signal level for an input command signal.
  • According to yet another preferred embodiment of the present invention, the Condition control means a gate unit, through which the input command signal is passed only and output as the Aungabebefehlssignal when the determination signal indicates both the admissibility of a command and a correct assignment of the command.
  • According to one more further preferred embodiment of the present invention has the state control device is a command storage unit for Caching a current input command signal.
  • According to one more further preferred embodiment of the present invention provides the condition control means a bidirectional check of enter in the circuit unit and output from this Command sequences ready. Preferably, by means of the state control device a bidirectional check of command sequences performed in such a way that is an admissibility one over to enter the command bus in the circuit unit or from this command of the command sequence to be issued by means of the in the state control device provided command allocation unit is checked while a time allocation of the over enter the command bus in the circuit unit or output from this Command of the command sequence using the in the state control device provided timing allocation unit is checked.
  • embodiments The invention is illustrated in the drawings and in the following Description closer explained.
  • In show the drawings:
  • 1 a schematic block diagram of a connection of a command bus with a circuit unit via an intermediate state control device, according to a preferred embodiment of the present invention;
  • 2 in the 1 shown state control device in greater detail; and
  • 3 a conventional circuit arrangement for connecting a command bus with a circuit unit.
  • In the same reference numerals designate the same or functionally identical Components or steps.
  • 1 shows a command bus 201 via which a circuit unit 202 Commands can be supplied to operate the circuit unit. The circuit unit 202 This communicates in general via address, data and tax busses. In this case, a selection of, for example, memory cells takes place in the circuit unit 202 via the address bus, a data exchange takes place via the data bus and commands are issued via a command or control bus. To simplify an explanation of the circuit arrangement according to the invention, only the command bus is used here 201 for supplying commands and in the circuit unit 202 provided, internal command bus 205 considered.
  • The command bus 201 has at least one command bus connection unit 204 for connecting at least one circuit unit 202 on. According to the invention, the circuit unit 202 not directly to the command bus 201 connected to a command sequence 203 to the circuit unit 202 but rather it gets between the command bus 201 and the circuit unit 202 a condition control device 100 provided below with reference to 2 is explained in more detail. The state machine provides an upstream command check such that the output command signal only contains commands corresponding to a given state diagram of the circuit unit 202 which are entered in a correct chronological order and a correct time assignment to a system time.
  • 2 shows the state control device according to the invention 100 , in the 1 is shown schematically, in greater detail. From the command bus 201 is via the command bus connection unit 204 a command sequence 203 first to a Pegeleinstelleinheit 115 entered. The level adjustment unit 115 the condition control device 100 represents an adjustment of a signal level of the command sequence signal 203 to a predetermined, required for further processing signal level of an input command signal 112 ready.
  • The from the Pegeleinstelleinheit 115 output input command signal 112 , which contains at least one command to be checked or at least one command sequence to be checked, becomes a command allocation unit 101 , a timing allocation unit 103 , a command storage unit 109 and a gate unit 114 fed. The gate unit 114 serves as a gating element for the input command signal to an output terminal 118 the condition control unit 100 an output command signal 113 provide. Passing the input command signal to the output port 118 occurs as a function of one of the gate unit 114 supplied determination signal 106 , The generation of the destination signal 106 will be described in detail below.
  • The first of the instruction allocation unit 101 supplied input command signal 112 is checked for the principle permissibility of a current command. In the command mapping unit 101 there is a check of a permissibility of the over the command bus 201 in the circuit unit 202 command of the command sequence to be input 203 , wherein in the instruction allocation unit 101 Preferably, a command table is stored which contains a sequence of commands corresponding to a state diagram for operation of the circuit unit 202 stored in advance. That from the Command Mapper 101 output command assignment signal 102 has a logic "1" level (high level, H) when an allowance of a current command of the input command signal 112 is verified. Similarly, a verification of the input command signal 112 in terms of a temporal assignment to, for example, a system time corresponding to a state diagram of the circuit unit 202 carried out. For this purpose, the input command signal 112 a timing allocation unit 103 in which a correct timing of a command sequence or a correct temporal assignment of a command of the input command signal 112 is verified. A time allocation signal output from the timing allocation unit 104 then, and only then, has a logic "1" level, if a correct time assignment of the in the input command signal 112 contained, current command is present. The command assignment signal 102 and the time assignment signal 104 become a linking unit 105 fed, which may be formed for example as an AND gate.
  • The output signal of the AND gate 105 is called a destination signal 106 the gate unit 114 , a system time storage unit 107 and the command storage unit 109 fed. If both the command assignment signal 102 as well as the time assignment signal 104 is at logic "1", the destination signal goes 106 also to a logical "1" level, such that the gate unit 114 is turned on to the input command signal 112 as an output command signal 113 to the output terminal 118 the condition control device 100 by pass. The output terminal 118 the condition control device 100 becomes as above with reference to 1 finally illustrates with the circuit unit 202 or the internal command bus 205 the circuit unit 202 connected, such that the circuit unit 202 now with a verified output command signal 113 can be controlled. This output command signal 113 contains only permitted commands or authorized command sequences. In this way, the advantage is achieved that any by the output command signal 113 the circuit unit 202 supplied command in the circuit unit 202 can be executed because in the circuit unit 202 a current command transition according to state diagram is present. Furthermore, the temporal assignment of the over the output command signal 113 supplied command correctly, such that the circuitry 202 gets into a well-defined state, avoiding system crashes. On via the command bus connection unit 204 supplied input command signal 112 does not become the output terminal 118 the condition control device 100 passed, if either the admissibility of the command in the command allocation unit 101 is not verified, or a temporal assignment of the command in the timing allocation unit is not verified, or if both of the above-mentioned cases occur. In this way, only commands to the circuit unit 202 deposed, if preceded by a well-defined state.
  • In the command storage unit 109 If a last command issued, ie a current command is stored. In this way, an up-to-date information is provided, at which point a command processing in a state diagram of the circuit unit 202 located. From the command storage unit 109 off, on the one hand, becomes an instruction mapping match 110 for the command mapping unit 101 and on the other hand a time allocation match 111 for the timing allocation unit 103 carried out.
  • With a knowledge of the position of the command processing in the state diagram is then known which command must be performed next. If a new command is issued, then it is with the help of the command allocation unit 101 stored command table possible to check whether the new command is allowed or not. If the new instruction is allowed, it will be considered the instruction assignment signal 102 issued a logical "1".
  • In addition to the above check, the condition control device provides 100 also a check of the time at which the new command is to be issued. The timing allocation unit 103 checks whether the time is reached at which the new command may be issued, that is, a command may be permissible, but it may happen that the time is not correct (command comes too early, for example). In the timing allocation unit 103 is checked by means of a time table, if the time assignment of the entered command is correct. If the time allocation is correct, it will act as a time allocation signal 104 a logical "1" from the timing allocation unit 103 output.
  • If the new command is now allowed, ie the command assignment signal 102 has a logical "1", and the instruction has a correct time assignment, ie the time allocation signal 104 has a logic "1", then this command can be passed through the gate unit as described above 114 and the output terminal 118 to the circuit unit 202 ( 1 ). If a new command is issued or to the circuit unit 202 passed, then a current system time in the system time storage unit 107 saved. Using the in the system time storage unit 107 stored system time can be determined on the one hand an elapsed time of a current command, while on the other hand, a system time update signal 108 the timing allocation unit 103 can be fed.
  • Advantageously, this provides as a circuit extension for circuit units 202 provided state control device 100 between the command bus 201 and the circuit unit 202 ensures that unauthorized commands, be it from the command sequence or from the time sequence, are blocked and not forwarded. Thus, a safe functional operation of the circuit unit 202 , For example, which is designed as a dynamic random access memory (DRAM), can be ensured, with a system reliability is significantly increased.
  • Furthermore, it is possible via a command input unit 116 a specific command table representing a state diagram of the circuit unit 202 corresponds to, in the Command Mapper 101 save. Further, via a timing input unit 117 the system time storage unit 107 be updated by an externally determined timing.
  • It should be noted that the in 2 shown bidirectional, that is, by means of the state control device, a bidirectional verification of command sequences is performed such that a permissibility of an over the command bus in the circuit unit to be entered or issued from this command of the command sequence 203 by means of the in the state control device 100 provided command mapping unit 101 is checked while a temporal assignment of the over the command bus 201 in the circuit unit 202 command of the command sequence to be inputted or outputted therefrom 203 by means of the timing allocation unit provided in the condition control means 103 is checked.
  • By the the circuit unit 202 upstream state control device 100 Provides comprehensive command control that increases system security and avoids system crashes. Subcomponents such as a processor unit, a controller unit and storage units can thus be manufactured by different manufacturers who do not necessarily have to use a uniform protocol. If impermissible command sequences are canceled, this occurs due to the upstream state control device 100 nevertheless not to a failure of the entire system.
  • Regarding the in 3 illustrated, conventional circuit arrangement is made to the introduction to the description.
  • Even though the present invention above based on preferred embodiments It is not limited to this, but in many ways modifiable.
  • Also the invention is not limited to the aforementioned applications limited.
  • In the same reference numerals designate the same or functionally identical Components or steps.
  • 100
    State control device
    101
    Command allocation unit
    102
    Command assignment signal
    103
    Timing allocation unit
    104
    Time allocation signal
    105
    linking unit
    106
    determination signal
    107
    System time storage unit
    108
    System time update signal
    109
    Instruction memory unit
    110
    Command Allocation Balance
    111
    Time Allocation Balance
    112
    Input command signal
    113
    Output command signal
    114
    gate unit
    115
    level adjusting
    116
    Command input unit
    117
    Timing input unit
    118
    output port
    201
    instruction
    202
    circuit unit
    203
    command sequence
    204
    Command bus connection unit
    205
    internal instruction

Claims (18)

  1. Circuit arrangement comprising: a) a circuit unit ( 202 ); and b) a command bus connection unit ( 204 ) for connecting a command bus ( 201 ) to the scarf processing unit ( 202 ), where c) circuit functions of the circuit unit ( 202 ) via command sequences ( 203 ), which by means of the command bus connection unit ( 204 ) in the circuit unit ( 202 ) are controllable, characterized in that d) between the command bus connection unit ( 204 ) and the circuit unit ( 202 ) a state control device ( 100 ), which d1) a check of a permissibility of a via the command bus ( 201 ) in the circuit unit ( 202 ) instruction to be entered command sequence ( 203 ) by means of a command assignment unit ( 101 ); and d2) checking a temporal assignment of the data via the command bus ( 201 ) in the circuit unit ( 202 ) instruction to be entered command sequence ( 203 ) by means of a timing allocation unit ( 103 ).
  2. Circuit arrangement according to claim 1, characterized in that via the command bus ( 201 ) in the circuit unit ( 202 ) command sequence to be entered ( 203 ) only by the state control device ( 100 ) and as an output command signal ( 113 ) is passed to the circuit unit when both the admissibility of the command and the time assignment of the command is verified.
  3. Circuit arrangement according to Claim 1, characterized in that in the command allocation unit ( 101 ) a command table is stored which contains a sequence of commands corresponding to a state diagram for operation of the circuit unit ( 202 ) contains.
  4. Circuit arrangement according to claim 1, characterized in that in the timing allocation unit ( 101 a timing allocation table is stored, which has a predefinable assignment of commands in accordance with a state diagram for the operation of the circuit unit ( 202 ) contains.
  5. Circuit arrangement according to Claim 1, characterized in that in the condition control device ( 100 ) a linking unit ( 105 ) for linking one of the instruction allocation unit ( 101 ) issued instruction allocation signal ( 102 ) with one of the timing allocation unit ( 103 ) output time signal ( 104 ) and for outputting a determination signal ( 106 ).
  6. Circuit arrangement according to Claim 5, characterized in that the condition control device ( 100 ) a system time storage unit ( 107 ) having a system time in dependence on the determination signal ( 106 ) stores.
  7. Circuit arrangement according to Claim 1, characterized in that the condition control device ( 100 ) a level setting unit ( 115 ) for adjusting a signal level of the command sequence signal ( 203 ) to a predetermined signal level of an input command signal ( 112 ) having.
  8. Circuit arrangement according to Claims 2 and 7, characterized in that the condition control device ( 100 ) a gate unit ( 114 ), by which the input command signal ( 112 ) and only as the output command signal ( 113 ) is output when the determination signal ( 106 ) indicates both the admissibility of the command and a correct time assignment of the command.
  9. Circuit arrangement according to Claim 1, characterized in that the condition control device ( 100 ) a command storage unit ( 109 ) for temporarily storing a current input command signal ( 112 ) having.
  10. Circuit arrangement according to Claim 1, characterized in that the condition control device ( 100 ) a bidirectional check in the circuit unit ( 202 ) and to be issued from this command sequences. 11. Method for checking a circuit unit ( 202 ) command sequence ( 203 ), comprising the following steps: a) connecting the circuit unit ( 202 ) to a command bus ( 201 ) by means of a command bus connection unit ( 204 ); and b) controlling circuit functions of the circuit unit ( 202 ) via command sequences ( 203 ), which by means of the command bus ( 201 ), characterized in that c) between the command bus connection unit ( 204 ) and the circuit unit ( 202 ) a state control device ( 100 ), wherein c1) a permissibility of a via the command bus ( 201 ) in the circuit unit ( 202 ) instruction to be entered command sequence ( 203 ) by means of a in the state control device ( 100 ) provided instruction allocation unit ( 101 ) is checked; and c2) a time assignment of the via the command bus ( 201 ) in the circuit unit ( 202 ) instruction to be entered command sequence ( 203 ) by means of a in the state control device ( 100 ) provided timing allocation unit ( 103 ) is checked.
  11. A method according to claim 11, characterized in that via the command bus ( 201 ) in the circuit unit ( 202 ) command sequence to be entered ( 203 ) only by the state control device ( 100 ) and as an output command signal ( 113 ) to the circuit unit ( 202 ) if both the admissibility of the command as well as the time assignment of the command has been verified.
  12. A method according to claim 11, characterized in that a predeterminable temporal assignment of commands in accordance with a state diagram for the operation of the circuit unit ( 202 ) in a timing allocation table of the timing allocation unit ( 101 ) is stored.
  13. Method according to claim 11, characterized in that one of the command assignment unit ( 101 ) issued command assignment signal ( 102 ) with one of the timing allocation unit ( 103 ) output time signal ( 104 ) by means of a in the state control device ( 100 ) provided linking unit ( 105 ) and as a destination signal ( 106 ) is output.
  14. A method according to claim 14, characterized in that in one in the state control device ( 100 ) provided system time storage unit ( 107 ) a system time in dependence on the determination signal ( 106 ) is stored.
  15. Method according to claim 11, characterized in that in a state control device ( 100 ) level adjusting unit ( 115 ) an adjustment of a signal level of the command sequence signal ( 203 ) to a predetermined signal level of an input command signal ( 112 ) is carried out.
  16. A method according to claim 12 and 16, characterized in that by means of a in the state control device ( 100 ) provided gate unit ( 114 ) the input command signal ( 112 ) only by the state control device ( 100 ) and as the output command signal ( 113 ) is output, if by the determination signal ( 106 ) both the admissibility of the command and the temporal assignment of the command is displayed.
  17. Method according to claim 11, characterized in that a current input command signal ( 112 ) in a state control device ( 100 ) provided command memory unit ( 109 ) is cached.
  18. Method according to claim 11, characterized in that by means of the condition control device ( 100 ) a bidirectional check of command sequences ( 203 ) is carried out such that a permissibility of a via the command bus ( 201 ) in the circuit unit ( 202 ) command to be entered or issued from the command sequence ( 203 ) by means of the in the state control device ( 100 ) provided instruction allocation unit ( 101 ) and a temporal assignment of the via the command bus ( 201 ) in the circuit unit ( 202 ) command to be entered or issued from the command sequence ( 203 ) by means of the in the state control device ( 100 ) provided timing allocation unit ( 103 ) is checked.
DE200410004307 2004-01-28 2004-01-28 Circuit arrangement for control of command sequences to a circuit unit, e.g. a memory circuit, has additional access control arrangement for checking command authorization and temporal command allocation Withdrawn DE102004004307A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE200410004307 DE102004004307A1 (en) 2004-01-28 2004-01-28 Circuit arrangement for control of command sequences to a circuit unit, e.g. a memory circuit, has additional access control arrangement for checking command authorization and temporal command allocation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE200410004307 DE102004004307A1 (en) 2004-01-28 2004-01-28 Circuit arrangement for control of command sequences to a circuit unit, e.g. a memory circuit, has additional access control arrangement for checking command authorization and temporal command allocation

Publications (1)

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DE102004004307A1 true DE102004004307A1 (en) 2005-09-01

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DE200410004307 Withdrawn DE102004004307A1 (en) 2004-01-28 2004-01-28 Circuit arrangement for control of command sequences to a circuit unit, e.g. a memory circuit, has additional access control arrangement for checking command authorization and temporal command allocation

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69017178T2 (en) * 1989-12-20 1995-08-10 Ibm A data processing system with apparatus for marking command.
DE10223178A1 (en) * 2002-05-24 2003-12-11 Infineon Technologies Ag Circuit arrangement with a sequence control, integrated memory and test arrangement with such a circuit arrangement

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69017178T2 (en) * 1989-12-20 1995-08-10 Ibm A data processing system with apparatus for marking command.
DE10223178A1 (en) * 2002-05-24 2003-12-11 Infineon Technologies Ag Circuit arrangement with a sequence control, integrated memory and test arrangement with such a circuit arrangement

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