DE10110615A1 - Process for generating drive pulses for power semiconductors - Google Patents

Abstract

The invention relates to a method for generating offset control pulses for half bridges (1), which are recorded in multiphase converters (12, 13, 14) or DC voltage converters (18), with the following method steps: DOLLAR A The shifting of the reference voltage u¶Ref¶ (31 ) by a delay or dead time T¶0¶ (33) or shifting the control voltage u¶St¶ (30) by the delay or dead time T¶0¶ (33), each divided by the number n of displacements.

Description

Technical field

The transformation of electrical energy, e.g. B. in a vehicle electrical system übli usually by static converters. There, equals in alternating sizes become one certain frequency or alternating quantities converted into equal quantities. Exchange or Equal quantities are e.g. B. voltages or currents. There is also the possibility of equal sizes in equal sizes z. B. a DC voltage into a DC voltage with another transform their voltage level.

State of the art

DE 199 47 476.1 describes a converter for converting electrical energy known. This converter is used in a vehicle electrical system and includes at least one half bridge. The half bridge in turn comprises at least one high side and a low-side switch, the switches on the half-bridge in any type number can be specified. The high-side switches are connected to a positive pole, while the low-side switches can either be connected to ground or the negative pole, which with a component generating the electrical energy, for. B. a three-phase current nerator communicates. An intermediate circuit capacitor is on parallel to the half bridge ordered, the capacity of which should be as small as possible. To achieve this, the An Control of the switches offset from each other, so that the intermediate circuit capacitor current to be supplied remains as low as possible.

With currently used direct current / direct current converters (DC / DC converters) at single-phase wiring only generates a PWM signal. The usual control procedure ren lies in the generation of a reference signal in the form of a trapezoid. On this one control procedures are the reset times each half a period T / 2 to each other  added. Unfavorable with trapezoidal reference signals are their ver poorer properties with regard to EMC. Furthermore, in this control ver the disadvantage of the fact that the reset times go to half the period T / 2 are defined and are therefore used with offset-clocked multi-phase half bridges can only be carried out with increased effort.

Presentation of the invention

The method proposed according to the invention can be used for multipha with offset clocking sen half-bridges can be controlled reliably, the displacement of the control im pulse can be done in two different ways.

On the one hand, the reference voltage can be shifted by a time period T ₀ . This is accomplished by means of a signal generator or by using an analog delay element, on which the dead times can be preset in a wide range. Depending on the number of half bridges used, in order to bring about sufficient control pauses, control times that are evenly spaced apart can be set. At these times, the corresponding half-bridge is activated by means of ten-aligned PWM control commands (center-aligned PWM), which is preferable to edge-aligned PWM (edge-aligned PWM) to avoid signal blurring and signal overlap.

On the other hand, the offset of the control pulses of offset-clocked multiphase half bridges can also be followed by a displacement of the PWM pulses by a dead time T ₀ . A T-link is used for this, e.g. B. an analog working dead time element or a shift register. As part of the generation of control signals on a digital path, counters can be used which are reset on the positive / negative edge of the PWM signal being used. The counter readings of the digital counters are evaluated; If certain criteria are met, output gates can be set or reset depending on the signal.

When the control signals are shifted twice (n = 2), using the method proposed according to the invention opens up the possibilities of either mirroring the reference voltage U _Ref or the control voltage U _St and in this way modulating a PWM signal, ie within the time To postpone period.

The method proposed according to the invention for generating offset to Control pulses for multi-phase half bridges can optionally be used as a software algorithm  run in a microcontroller or as programmable logic; it can be of course also as a hardware structure.

drawing

The invention is explained in more detail below with the aid of the drawing.

It shows:

Fig. 1 shows a module of a half-bridge for offset drive,

Fig. 2 shows a complete three-phase inverter composed of three identical half bridges for offset drive,

Fig. 2.1 a DC voltage converter (DC / DC converter) with different voltage levels,

Fig. 3 is a shift of the reference voltage U _{Ref 1} by T _0,

Fig. 4 is a shift of the PWM signals by a delay time T / n = T _{0 period,}

Figure 5 deceleration membered. The generation of PWM signals in 2-fold staggered switching with Ver.

Fig. 6 shows the implementation of the delay means of reflection of the reference clamping voltage 50% at u =

Fig. 7, the generation of offset PWM signals at 2 times offset clocks and

Fig. 8 shows the digital implementation of the time delay with counters for positive / negative edge of the PWM signal.

variants

Fig. 1 is a module of a half bridge for offset control can be removed.

Fig. 1 shows a module of a half-bridge 1 tion for a converter with offset control. As an example, four switches 4 , 5 , 6 and 7 and 8 , 9 , 10 and 11 connected in parallel are shown here. However, any other number of parallel valves or a different number of parallel sub-branches is also conceivable. Reference number 2 denotes an intermediate circuit capacitance, while reference numbers 3.1 , 3.2 , 3.3 and 3.4 identify decoupling indications that are necessary for the functionality of the converter.

The illustration according to FIG. 2 shows a complete three-phase converter, constructed from three identical half bridges for offset control.

Each of the half bridges 12 , 13 and 14 are assigned decoupling inductors 3.1 , 3.2 , 3.3 and 3.4 . Control of the switches or valves can be ensured, for example, by arranging a control and regulating device.

With the reference numerals 15 , 16 and 17 , the phase windings of a three-phase generator are exemplified in schematic form, which is operated via the multi-phase converter, which contains individual half bridges 12 , 13 and 14 .

The representation according to Fig. 2.1 is shown in a DC-DC converter (DC / DC converter) with different voltage levels.

The DC-DC converter 18 as shown in FIG. 2.1 comprises a half bridge analogous to that shown in FIG. 1. On the high side of the half bridge 1 as shown in FIG. 2.1, the high-side switches 4 , 5 , 6 and 7 , while the low-side switches 8 , 9 , 10 and 11 are located on the low-side of the half-bridge as shown in FIG. 2.1. The individual parallel branches of the half-bridge of the DC converter 18 according to FIG. 2.1 are each provided with decoupling inductors 3.1 , 3.2 , 3.3 and 3.4 . In a modification of the half-bridge 1 as shown in FIG. 1, a further capacitance in the form of a capacitor 21 is arranged on the half-bridge serving as a DC / DC converter 18 as shown in FIG. 2.1. The first voltage level 19 is given by a DC voltage of 14 V, with which part of a vehicle electrical system can be supplied, while the second voltage level 20 of the DC voltage converter 18 is, for example, at a level of approximately 42 V as shown in FIG. 2.1 . with which further consumers of a supply system of a motor vehicle can be supplied.

In the illustration according to FIG. 3, the displacement of a reference voltage U _ref by a delay time T is shown _0th

The illustration in Fig. 3 shows the profile of the control voltage 30, u _St, which over time does not change. The triangular curve 31 of the reference _voltage u _Ref1 is superimposed on the control voltage 30 . The PWM signal 32 (PWM1) is reproduced as a rectangular waveform. If the reference voltage shifted by the delay time T tarry ₀ 33 31, there is set a by the delay time T _0, 33, corresponding shifted reference voltage 35th The delay time T ₀ becomes according to the relationship

T ₀ = T _period / n

determined, where n is the number of transfers, d. H. the timing means.

The same effect occurs when the PWM signal 32 is shifted by the delay time T ₀ (reference numeral 33 ) when the control voltage u _Sd , 30 and reference voltage u _Ref , 31 remain unchanged, the reference voltage still being one essentially has a triangular shape, which is enormously advantageous for the use of a center-aligned PWM signal 32 , in particular with regard to an improvement in the EMC.

The resulting shifted PWM signal is identified according to FIG. 3 by reference numeral 36 and is also shifted by T ₀ , like the reference voltage curve 31 according to the diagram on the left in FIG. 3.

Fig. 4 shows the generation of offset PWM signals by mirroring the control voltage u _St and mirroring the reference voltage u _Ref with double offset clocking (n = 2).

In the left part of the diagram according to FIG. 4 is the reflection of the voltage curve of the reference voltage U _R, 31, shown at u = 50%. From the reflection of the reference voltage 31 u _Ref on the mirror axis 38, which is arbitrarily selected in this example by u = 50%, the reference voltage 31 u _{R is flipped} . The PWM signals 32 and 36 which arise therefore obey the following equations:

PWM1 = SIGN (u _Ref1 - u _St )

PWM2 = SIGN (u _Ref2 - u _St ).

A comparison of the courses of PWM signal 1, reference numeral 32 with the course of the PWM signal 2, reference number 36 , shows that the manipulation of the reference voltage 31 shows a shift of the second PWM signal 36 by the delay or dead time T. ₀ 33 takes place.

In the right part of the illustration according to FIG. 4, another manipulation possibility for generating a delay of a PWM signal 31 is shown . This representation also relates to the special case n = 2, and consequently to a 2-fold offset clocking of the PWM signal. According to this variant of the method proposed according to the invention, the reference signal, ie the reference voltage U _R , 31 , is maintained and is continuously triangular, while the control voltage 30 , u _St , is mirrored at the mirror axis 38 at u = 50%. The PWM signals 32 and 36 are formed in accordance with this embodiment variant in accordance with the relationships shown below:

PWM1 = SIGN (u _Ref - u _St1 )

PWM2 = SIGN (U _St2 - u _Ref ).

Even with the mirroring of the control voltage 30 , u _St , a delay of the two th PWM signal 36 can be achieved by the delay or dead time T ₀ , 33 .

The illustration of FIG. 5 is seen from the construction of an array of generating PWM signals at 2-fold staggered switching.

The output PWM signal is tapped at a tap point and a delay element 40 is applied . If the delay element 40 is an analog delay element, the delay time T ₀ , reference numeral 33 , can be set on this in order to obtain a time-shifted PWM signal 36 . If the implementation is carried out digitally, a shift register can be inserted on delay element 40 .

Fig. 6 illustrates the implementation of the time delay by mirroring the reference voltage u _R , reference numeral 31 .

FIG. 6 corresponds to a conversion of the left part of the diagram according to FIG. 4. The control voltage u _St , 30 is applied to both inputs of the input side 44 of operational amplifiers 41 , 42 which are assigned positive signs. At the output 45 of the operational amplifiers 41 and 42 , their output signals are connected to an inverted input of K elements 46 and 47 , at the output of which the PWM signals 32 and 36 , which are shifted with respect to one another, are present and can be tapped.

The reference voltage 31 , u _Ref , is connected directly to the input of the K1 element 46 , while an inverting stage 43 is connected upstream of the K2 element 47 . The mirror axis 38 is implemented on this at u = 50%; according to the relationship y = x - 1, the reference voltage u _Ref , reference numeral 31 , is mirrored and can be adjusted in accordance with the curve shown in FIG. 4, ie in particular shifted in time.

FIG. 7 shows the generation of offset PWM signals in the case of double-offset switching with reflection of the control voltage u _St at u = 50% and subsequent formation of the inverted PWM signal. According to the mirroring of the control voltage 30 , u _{St shown} in the right part of FIG. 4, the leveling 43 in the circuit arrangement according to FIG. 7 is connected upstream of the operational amplifier 42 for the control voltage 30 . In this variant for the special case n = 2, the reference voltage 31 u _{Ref is} given directly to a K1 element or a K2 element 46 or 47 .

On the output side, there are PWM signals 32 and 36 on the K1 element 46 and on the K2 element 47 , which are shifted from one another in time by T ₀ , ie corresponding to the set delay or dead time.

The representation in FIG. 8 shows a digital implementation of the time delay of PWM signals with digital counters for positive / negative signal edge of the PWM signal.

In this digital embodiment, the clock generator 50 (CLK) is connected to the clock input 52 of each flip-flop 51 or 53 via connecting lines, the flip-flops 51 or 53 connected in series with a mastering master PWM signal are applied. The positive output of the first flip-flop 51 is present at the input of an "AND-NOT" combination 55 and an "OR" combination 54 . The negative output of the second flip-flop 53 is also present at both links 54 and 55, respectively.

The start signal from the clock 50 is present at the two clock signals 52 of the two enumerated flip-flops 51 and 53 at the clock input 60 of a digital counter 56 and 57, respectively. The digital counter 56 counts the positive edge passes 58 , the digital counter 56 counts the passes of the respective negative edges 59 . The respective positive / negative flanks of the master PWM signal are reset on the digital counters 56 , 57 . The digital counters 56 , 57 can e.g. B. be designed as a 12-bit counter, the positive edge 58 by the dead time T ₀ , 33 , offset or, in the alternative, the negative edge 59 of the master PWM signal by the dead time T ₀ , 33 , offset ,

Numerical values are given below, which are only intended as an example.

LIST OF REFERENCE NUMBERS

1

half bridge

2

DC link capacity

3.1

Decoupling

3.2

Decoupling

3.3

Decoupling

3.4

Decoupling

4

High-side switch

5

High-side switch

6

High-side switch

7

High-side switch

8th

Low-side switch

9

Low-side switch

10

Low-side switch

11

Low-side switch

12

First half bridge

13

Second half bridge

14

Third half bridge

15

phase winding

16

phase winding

17

phase winding

18

Gleichspannungsumrichter

19

First voltage level

20

Second level of tension

21

capacitor

30

Voltage u _St

31

Reference voltage u _R

32

First PWM signal

33

Delay, dead time

34

Dislocation by T ₀

35

Shifted reference voltage

36

Shifted PWM signal

37

Mirrored reference voltage

38

Mirror axis u = 50%

39

Inverted PWM signal

40

Analog delay element

41

operational amplifiers

42

Another operational amplifier

43

inverting stage

44

input side

45

output side

46

K1 element

47

K2 element

50

clock

51

Flip-flop block

52

Clock input

53

Another flip-flop device

54

Or link

55

AND NOT operation

56

Digital counter positive edge

57

Digital counter negative edge

58

Positive edge signal

59

Negative edge signal

60

Clock input

Claims (11)

1. Method for generating offset control pulses for half bridges ( 1 ), which are recorded on multi-phase converters ( 12 , 13 , 14 ) or DC voltage converters ( 18 ), with the following method steps:

• - The shifting of the reference voltage U _R ( 31 ) by a delay time which corresponds to the dislocations or
• - The shifting of a PWM signal ( 32 ) by a delay time T ₀ ( 33 ), which corresponds to the period T divided by the number n of displacements.

2. The method according to claim 1, characterized in that the shifting of the reference voltage u _R ( 31 ) is carried out by triggering a signal generator. 3. The method according to claim 1, characterized in that the displacement of the reference voltage u _Ref ( 31 ) by means of a delay element arranged in the signal run takes place ( 40 ), at which the delay or dead time T ₀ ( 33 ) can be given before. 4. The method according to claim 1, characterized in that the displacement of the PWM signal ( 32 ) by means of a digital delay element ( 40 ). 5. The method according to claim 1, characterized in that the displacement of the PWM signal ( 32 ) is carried out in digital implementation by means of a shift register. 6. The method according to claim 1, characterized in that the output pulse of the PWM signal ( 32 ) is that of a center-aligned PWM signal. 7. The method according to claim 1, characterized in that with digital implementation of the offset control of half bridges ( 12 , 13 , 14 ) the delay of the PWM signal ( 32 ) by means of digital counters ( 56 , 57 ). 8. The method according to claim 7, characterized in that in each case one of the digital counter ( 56 , 57 ) of the positive edge ( 58 ) and one of the digital counter ( 56 , 57 ) of the negative edge ( 59 ) of the PWM signal ( 32 ) assigned. 9. The method according to claim 1, characterized in that at 2 times offset clocks (n = 2) for mirroring the reference voltage u _Ref ( 31 ) this passes through an inverting stage ( 43 ). 10. The method according to claim 1, characterized in that at 2 times offset clocks (n = 2) for mirroring the control voltage u _St ( 30 ) this is an inversion stage ( 43 ) is applied. 11. The method according to claim 1, characterized in that the implementation of the offset control optionally as a software algorithm in a microcon troller or implemented as programmable logic.