DE10021735B4 - Method for producing a semiconductor component with a metallic conductor track - Google Patents
Method for producing a semiconductor component with a metallic conductor track Download PDFInfo
- Publication number
- DE10021735B4 DE10021735B4 DE2000121735 DE10021735A DE10021735B4 DE 10021735 B4 DE10021735 B4 DE 10021735B4 DE 2000121735 DE2000121735 DE 2000121735 DE 10021735 A DE10021735 A DE 10021735A DE 10021735 B4 DE10021735 B4 DE 10021735B4
- Authority
- DE
- Germany
- Prior art keywords
- metal
- conductor track
- deposited
- recess
- dopant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Verfahren
zur Herstellung eines Halbleiterbauelementes mit einer metallischen
Leiterbahn, bei dem
– in
einem ersten Schritt an einer Oberseite des Halbleiterbauelementes
eine Aussparung (5) im Bereich einer herzustellenden Leiterbahn
hergestellt wird,
– in
einem zweiten Schritt ein für
die Leiterbahn vorgesehenes Metall (8) in diese Aussparung (5) abgeschieden
und von der Oberseite des Halbleiterbauelementes entfernt wird,
so daß das
Metall (8) nur noch in der Aussparung (5) vorhanden ist,
– in einem
dritten Schritt auf das Metall (8) ein Dotierstoff (9) abgeschieden
wird,
– in
einem vierten Schritt der Dotierstoff (9) in das Metall (8) eingetrieben
wird und
– in
einem fünften
Schritt überschüssige Anteile
des Dotierstoffes entfernt werden.Method for producing a semiconductor component with a metallic conductor track, in which
A recess (5) is produced in the region of a conductor track to be produced in a first step on an upper side of the semiconductor component,
In a second step, a metal (8) provided for the conductor track is deposited in this recess (5) and removed from the upper side of the semiconductor component so that the metal (8) is present only in the recess (5),
In a third step, a dopant (9) is deposited on the metal (8),
- In a fourth step, the dopant (9) is driven into the metal (8) and
- In a fifth step, excess portions of the dopant are removed.
Description
Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauelementes mit metallischen Leiterbahnen, mit denen die elektrische Verdrahtung bewirkt ist.The The present invention relates to a process for producing a Semiconductor component with metallic conductor tracks, with which the electrical wiring is effected.
Die bei Halbleiterbauelementen ausgebildeten elektrischen Leiterbahnen, die üblicherweise aus Kupfer oder Aluminium hergestellt sind, werden durch den hindurchfließenden Strom erwärmt, was insbesondere bei einer Verwendung in Speicher- oder Logikbausteinen zu Problemen führt. Die Erwärmung der Leiterbahnen regt einen Materialtransport in dem Metall der Leiterbahnen an, der als Elektromigration bekannt ist. In der Veröffentlichung von F.M.D. Heule und A. Gangulee in Thin Solid Films 25, 531–544 (1975) ist beschrieben, dass die Resistenz eines Materiales gegen Elektromigration verbessert werden kann, indem dem Material Dotierstoffatome zugesetzt werden.The formed in semiconductor devices electrical conductor tracks, the usual Made of copper or aluminum, are made by the current flowing through heated especially when used in memory or logic devices leads to problems. The warming the conductor tracks stimulates a material transport in the metal of the Tracks, known as electromigration. In the publication from F.M.D. Heule and A. Gangulee in Thin Solid Films 25, 531-544 (1975) is described as the resistance of a material to electromigration can be improved by adding dopant atoms to the material become.
Weiterhin
offenbart die Druckschrift
Aufgabe der vorliegenden Erfindung ist es, ein Herstellungsverfahren für ein Halbleiterbauelement anzugeben, dessen metallische Leiterbahnen einer verminderten Degradation unterliegen.task The present invention is a method of manufacturing a semiconductor device indicate whose metallic interconnects of a reduced degradation subject.
Diese Aufgabe wird mit dem Verfahren mit den Merkmalen des Anspruches 1 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.These Task is with the method with the features of the claim 1 solved. Embodiments emerge from the dependent claims.
Bei dem erfindungsgemäßen Verfahren sind metallische Leiterbahnen vorhanden, die zumindest bereichsweise derart mit Dotierstoff versehen sind, dass eine mögliche Elektromigration im Betrieb des Bauelementes gegenüber herkömmlichen Leiterbahnen deutlich vermindert ist. Die Leiterbahnen sind vorzugsweise Kupfer, das z. B. mit Zinn oder Magnesium dotiert ist. Zur Herstellung wird auf eine Leiterbahn (insbesondere aus Kupfer), die zunächst ganzflächig aufgebracht sein kann, eine Schicht aus dem Dotierstoff abgeschieden. Anschließend wird der Dotierstoff unter Wärmezufuhr in das Metall der Leiterbahn eingetrieben (thermal anneal). Überschüssiges Metall und überschüssiger Dotierstoff werden von der Oberseite des Bauelementes entfernt, so dass nur die strukturierten dotierten Leiterbahnen mit ausreichender Resistenz gegen Elektromigration übrig bleiben.at the method according to the invention metallic interconnects are present, at least in some areas are provided with dopant such that a possible electromigration during operation of the device over conventional interconnects clearly is reduced. The interconnects are preferably copper, the z. B. doped with tin or magnesium. For the production is on a conductor track (in particular of copper), which initially applied over the entire surface may be a layer of the dopant deposited. Subsequently, will the dopant under heat driven into the metal of the track (thermal anneal). Excess metal and excess dopant are removed from the top of the device so that only the structured doped tracks with sufficient resistance left over against electromigration stay.
Es folgt eine genauere Beschreibung des erfindungsgemäßen Herstellungsverfahrens anhand zweier typischer Ausführungsbeispiele des Herstellungsverfahrens.It follows a more detailed description of the production process according to the invention with reference to two typical embodiments of the manufacturing process.
Die
Bei dem erfindungsgemäßen Verfahren werden Aussparungen in der Oberseite des Bauelementes hergestellt, die jeweils die Bereiche der herzustellenden Leiterbahnen definieren. So ist es möglich, die Leiterbahn in einfacher Weise wie vorgesehen zu strukturieren und den Verfahrensschritt, in dem der Dotierstoff in das Metall der Leiterbahn eingebracht wird, an einer planaren Oberseite des Bauelementes auszuführen.at the method according to the invention recesses are made in the top of the component, each defining the areas of the printed conductors to be produced. So it is possible the To structure a track in a simple way as intended and the process step in which the dopant in the metal of Conductor is introduced to perform on a planar top of the device.
In
der
In
Auf
die soweit hergestellte Struktur wird ein für die Leiterbahn vorgesehenes
Metall
Das
aufgebrachte Metall wird dann von der Oberseite z.B. mittels CMP
(Chemical Mechanical Polishing) soweit entfernt, dass entsprechend
dem Querschnitt von
Nachdem
der restliche Dotierstoff
In
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2000121735 DE10021735B4 (en) | 2000-05-04 | 2000-05-04 | Method for producing a semiconductor component with a metallic conductor track |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2000121735 DE10021735B4 (en) | 2000-05-04 | 2000-05-04 | Method for producing a semiconductor component with a metallic conductor track |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10021735A1 DE10021735A1 (en) | 2001-11-15 |
DE10021735B4 true DE10021735B4 (en) | 2006-01-12 |
Family
ID=7640771
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2000121735 Expired - Fee Related DE10021735B4 (en) | 2000-05-04 | 2000-05-04 | Method for producing a semiconductor component with a metallic conductor track |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE10021735B4 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6022808A (en) * | 1998-03-16 | 2000-02-08 | Advanced Micro Devices, Inc. | Copper interconnect methodology for enhanced electromigration resistance |
US6023100A (en) * | 1997-07-23 | 2000-02-08 | Advanced Micro Devices, Inc. | Metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects |
-
2000
- 2000-05-04 DE DE2000121735 patent/DE10021735B4/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6023100A (en) * | 1997-07-23 | 2000-02-08 | Advanced Micro Devices, Inc. | Metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects |
US6022808A (en) * | 1998-03-16 | 2000-02-08 | Advanced Micro Devices, Inc. | Copper interconnect methodology for enhanced electromigration resistance |
Non-Patent Citations (2)
Title |
---|
F.M.D. Heule und A. Gangulee, In: Thin Solid Films 25, 531-544 (1975) |
F.M.D. Heule und A. Gangulee, In: Thin Solid Films25, 531-544 (1975) * |
Also Published As
Publication number | Publication date |
---|---|
DE10021735A1 (en) | 2001-11-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8125 | Change of the main classification |
Ipc: H01L 21/768 |
|
8364 | No opposition during term of opposition | ||
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |