DD289357A5 - ERROR TREATMENT AND MODIFICATION ARRANGEMENT FOR DATA PROCESSING PLANTS - Google Patents

Abstract

The invention relates to a Fehlerbehandlungs- and Modifizierungsanordnung for data processing systems. Error handling and modification arrangement for data processing systems for the efficient search and treatment of hardware and software errors and the modification of data processing programs by using a programmable, consisting of non-volatile memory control circuit with the flexibly programmable, consisting of volatile memories comparison circuit, memory circuit and program module and evaluation logic and decoupling circuit , The comparison circuit containing the error effect in the automatic function is interconnected with the system bus and the evaluation logic, the latter being further connected to the switching device and this to the decoupling circuit and the program module. This circuit chain ensures the separation of the main memory from the system bus and the activation of the program module containing the error handling and modifying programs which is coupled to the memory circuit containing a set of data values. The system bus is interconnected with the decoupling circuit, control circuit, compare circuit, memory circuit, and program module {error handling arrangement; Modification arrangement; Data processing system; non-volatile memory; volatile memory; system bus; Random access memory}

Description

Field of application of the invention

The error handling and modifying arrangement is used to monitor the workflow of data processing equipment and allows detection and correction of errors as well as; Testing and modification of new data processing programs.

Characteristic of the known state of the art

Increasing complexity and complexity of data processing systems and the programs running on them require the demand for efficient arrangements for troubleshooting and treatment of the data processing systems and programs as well as the modification of the programs.

The known arrangements are based on the condition that in the error state of the data processing systems at least the Adrisse of the defect causing the defect is known. The circuit arrangements are connected to the system breaker data processing system and monitor its data streams.

In the arrangement known from SU 987624, the scheduling of a program is controlled by changing. J whose Abarbeit the address values of the command counter compared with predetermined address values and a match

Transition to a likewise specified subroutine address takes place.

Since it is not possible to readily locate all the errors that have occurred, with the arrangement according to DE 2737350 in addition to that described in SU 987624 by a circuit arrangement for the sequential retracing of the program flow path, it is possible to precisely fix the cause of the error.

According to the circuit arrangement described in DE 2725077, the possibility of superimposing certain commands with new command content is furthermore provided. The signal output upon detection of the predetermined address value can also be used to start alarm signal devices.

The monitoring device DE 3036926 switches on reaching a predetermined error state of the data processing system, the clock generator to a normal process interrupting, separate test cycle. Depending on the cause of the error, the test cycle decides on the measures to be initiated subsequently. The check for the presence of an interrupt request takes place in a clock window of the power stroke.

The known arrangements rely on their reference to the current instruction count of the data processing system that the eventual error is already located. This is given as a precondition for static errors of the system and for logical program errors. For the search of dynamic errors die.se arrangements are only partially usable. Another disadvantage is their low flexibility during the execution of programs, since all values and J error programs must be written in beforehand. Erroneous, significant data sequences of the system bus can not be detected because the monitoring devices are purely combinatorial in nature and can not fulfill a vending machine function. '

Object of the invention

The aim of the invention is to provide a flexible arrangement for troubleshooting and treatment in data processing systems and for modifying the programs running on them.

Explanation of the essence of the invention

The object is to provide a Fehlerbehandlungs- and Modifizierungsanordnung for data processing systems, which is universally applicable and freely programmable.

According to the invention this is achieved by an arrangement for connection to the system bus of the data processing system whose programmable, consisting of non-volatile memory control circuit with the evaluation logic, the switching device and the freely programmable, volatile memory-containing comparison circuit, memory circuit and program module is connected.

Furthermore, there is a concatenation between the comparator circuit containing the error features in the form of automatic functions, the comparator circuit analyzing its state, the adjoining switchover device and the decoupling circuit separating the mainframe of the data processing system when the error is detected. By a further interconnection of program module and this activating switching device to be performed in error detection interruption of the normal processing of the data processing program and the start of programs contained in the program module for troubleshooting and modification and modification. The memory circuit also connected to the program module and containing a set of the last data words of the system bus contributes to the efficiency increase of the debugging.

The coupling of the system bus to the control circuit, decoupling circuit, comparison circuit, memory circuit and program module is for complex connection with the data processing system and provides input values for the error handling and modification system.

embodiment The figure shows the error handling and modification arrangement for data processing systems. On an exemplary embodiment, this solution is explained in more detail. The error handling and modification arrangement provides

a complex circuit module, which is connected via connectors directly to the system bus. The

Main memory 5 of the data processing system is coupled via an adapter to the system bus 1 that this connection

can be influenced by the decoupling circuit 2. In the circuit system, the comparison circuit 3,

Memory circuit 4, control circuit 6 and program module 7 connected directly to the system bus 1. The control circuit 6 as a central element for setting the operating modes active, passive and initialization is via control and Data lines internally with the comparison circuit 3, memory circuit 4, program module 7, evaluation logic 8 and Switching device 9 connected To initialize the arrangement, the following are set in the nonvolatile memories of the control circuit 6 Actions performed. On the one hand is about the connection Control circuit 6-switching device 9-decoupling circuit 2, the connection of the working memory 5 with the System bus 1 interrupted, the decoupling according to the existing hardware conditions z. B. by

appropriate assignment of the bus terminals of the working memory 5 can be realized. On the other hand, at the same time, the control circuit 6 connects the program module 7 to the system bus 1, thereby providing the conditions for the same

Programming. The programming of the likewise volatile memory containing comparison circuit 3 and Memory circuit 4 is created by transferring the previously created and stored on external storage devices programs

or performed from the keyboard.

After initialization, the arrangement can be used in the operating mode active or passive, in the latter case the Control circuit 6 via the connection to the decoupling circuit 2 selbige blocked. When in Umschaitmoment in the Operating mode active, the working memory 5 is separated from the system bus 1 by the decoupling circuit 2, a deletion takes place

the stored data sequence of the memory circuit 4. But the main memory 5 is connected to the system bus, d. H.

possibly run data processing programs, then this deletion is performed only after appropriate Diaiogabfraged, since these stored data sequences for reasons mentioned above may be relevant.

The interruption of the current data processing programs to be performed after error detection is performed via the Coupling of system bus 1, comparison circuit 3, evaluation logic 8, switching device 9 and decoupling circuit 2

realized as follows.

The jacks of the system bus 1 are input values for the machine function, which in the volatile memory of the Comparative circuit 3 is implemented and in the occurrence of the errors described by means of these functions in one

pass over certain state. The evaluation logic 8 connected to the comparison circuit 3 recognizes these states and reformulates the signal to the switching device 9 which, with the aid of the internal circuit functions, controls the organizational and temporal sequence of the separation of the main memory 5 from the system bus 1, d. H. Interruption of the

Datanverarbeitungsprogrammes, the activation of the program module 7 by circuit validation of the data

the system bus 1 for the memory 5 of the data processing system corresponding memory structure and the

Starting a routine for redirecting the control flow contained in the non-volatile memory part of the control circuit β Data processing system on the entry point of the stored in the program module 7 Fehlerbehandlungs- and Modification programs. About the connection with the memory circuit 4 is for the program module 7, the possibility

in order to increase the efficiency of debugging the data words of the system bus 1 preceding the interruption and stored in the volatile memories of the memory circuit 4 organized as shift registers or queues.

The return to the interrupted after execution of the error handling and modification programs Data processing program is programmatically by reversing the process of switching. The field of application of this order is not limited to error detection and correction, but rather

allows a modification during the test runs of data processing programs, the monitoring of the operation of the system itself, if errors affect the date or sequence of data on the system bus 1, the analysis of

Data processing programs during their processing, the search for semantic errors of programs that z. B. too System crashes, infinite loops, stop states, false references, etc. lead, i.a.m. In addition, the arrangement is freely programmable and thus also modifiable and expandable during use. It

Dynamic errors can also be detected.

Claims (1)

Error handling and modification arrangement for data processing installations, characterized in that a programmable control circuit (6) consisting of non-volatile memories and provided with active passive initialization mode is provided with a volatile memory comparison circuit (3), memory circuit (4) and program module (7) and on the other hand with an evaluation logic (8) and a switching device (9) is connected, that the switching means (9) a decoupling circuit (2), which is arranged between the system bus (1) of the data processing system and the memory (5), controls that the memory circuit (4) and the program module (7) are coupled and the system bus (1) of the data processing system with the comparison circuit (3), the memory circuit (4), the program module (7) and the control circuit (6) is interconnected. For this 1 page drawing