DD272177A1 - MEMORY-PROGRAMMABLE CASCADABLE MICRO-CONTROLLER - Google Patents

Abstract

The invention relates to a memory programmable cascadable microcontroller (SKM), which can be integrated and implemented in conjunction with an external program memory (ROM), a microcontroller for binary sequence controls. By means of the inventive circuitry arrangement of logical means of digital technology, such a control can be realized both with an SKM and with a non-limited number of further SKMs of the same type as a control system (MK) in conjunction with a ROM, with one SKM as the master in the MK operate as a slave and both the working mode of each SKM as well as the assignment of the control inputs of the other SKM as a sensor input or as Aktuatorausgaenge, by external wiring of the SKM is programmable. Fig. 1

Description

T itle of the invention:

Memory programmable cascadable microcontroller

Field of application of the invention:

The invention relates to a programmable cascadable microcontroller SKM, which programmatically undertakes the setting of actuators and displays for controlling a wide variety of types of machines and processes, taking into account preselected setting variables and the process progress and result. Such a microcontroller, together with an associated program memory, in which the control algorithms required for the particular application in question are stored as programs, forms a programmable logic controller.

Characteristic of the known state of the art:

It is known to realize controller circuits for machines and processes by microprocessor systems using I / O ports to connect the sensor and actuator lines. The number of connectable sensor and actuator lines is determined by the number of connected ports. The disadvantage of such control systems consists in the large number of required components (CPU, PIO, SIO, CTC) and the resulting material costs, the associated assembly costs,

the required PCB area and the energy requirement. The programming of such microprocessor systems is tailored to the included calculator; the processing of a sensor state into a switching command of an actuator line requires a plurality of program commands.

It is also known for controllers of special applications controller, which are also known as microcontroller in integrated technology to use, which can work depending on the application in conjunction with or independently without microprocessor systems (Electronics 34 (1985) 25, pp 75-77 and Electronics 35 (1986) 6, pp. 134-138).

In the DD-WP, the disadvantage inherent in these microcontrollers is that the number and variability of the sensor and actuator connections, as well as the amount of internal logic, in particular the number of memories and registers, must be adapted to the discrete application 228996 proposed a modular stringable, d. H. cascadable, to apply integrated IPLS programmable logic controller circuitry in a bit processing unit with associated RAM in the form of bit-variable logic links. However, this proposed solution for the cascading of circuits IPLS has several disadvantages for a universal use in control devices, whereby their scope is appreciably restricted. A major drawback is that the IPLS requires an integrated circuit containing fixed-program-link address to achieve unrestricted cascadability. This means that different IPLS in different configurations require different types of circuits, which are differentiated by this connection representing the fixed address. Another significant disadvantage is the cost of the fixed address processing address comparison unit, for the required thereby component address counter, by the in this context

necessary special Initialisierungsvcr ^ ang at the beginning of the work of a system of IPLS, which is feasible only under control of a higher-level control system, the required two pins for Initiglisierungsein- and output and the associated further hierarchy formation with the associated programming effort. Another disadvantage of the IPLS is the need for a RAM for storing the bit variables corresponding to the sensors of the SIiM, thus the too low flexibility when using an input / output unit for bit variables and addressing of the program memory

 Another disadvantage is that in a system of IPLS only a specific IPLS for addressing the program memory is prioritized, while the dedicated logic overhead in the other IPLS remains unused. The same applies to the m each IPLS contained bit processing unit, the result of which only in one circuit 'directly processed wire, while it is used in the other only error messages that can only be processed by a higher-level processor system'. Thus, the existing logical processing capacity, based on the subject invention appears insufficiently usable.

Object of the invention:

It is the object of the invention to provide a technical solution for a programmable microcontroller which can be integrated, by its application in control systems requiring no further or higher-level control devices, control problems with very different numbers of both sensor and actuator lines Sum can also exceed the number of terminals of a single microcontroller, and with different levels of programmable programs to be stored are solvable, the nature and extent of required assemblies that should not exceed that of conventional microcontrollers, and without more ice a circuit type is required.

Explanation of the essence of the invention:

The invention has for its object to make the logical structure of a programmable microcontroller so that it can be produced in integrated technology and that it by cascading several completely identical such microcontroller SKM in a controller system in conjunction with a program memory without further control or Prozessoralemente allows to solve control tasks with a wide variation in the number of both the sensor and the actuator lines and the number of commands to be addressed, so that technological limitations of the pin number and the register scope in individual SKM cause no functional restriction d9s application, where position and Function of each SKM in the controller system are to be determined by turning on little external control potentials, all the SKMs used in the system offer the user the full amount of logical processing capacity and that in the controller system implemented control sequence as strictly synchronous, interference-free and well-defined runs as in berei 'known systems. According to the invention, the object of creating a memory programmable cascadable microcontroller SKM, as shown in the characterizing part of the claims, solved.

The advantages of the proposed solution are that only one type of SKM can be used, either individually or cascaded in a controller system, in conjunction with a program memory, but without any further need for controlling elements to perform initializer control operations, so that controllers with a total number of sensor and actuator lines that may be less than, equal to, or any larger than the terminal number of a single SKM, with the logical processing capability of the SKM fully available for user-specific applications. In this case, the addressable memory space can also advantageously be extended with each further controller circuit.

Another advantage lies in the fact that with each cascaded circuit it is possible to use pins available for control only as inputs or only as outputs, thereby considerably expanding the number of applications. In summary, the advantage of the proposed solution is to allow a variety of applications with only one type of circuit.

Exemplary embodiment;

The invention will be explained below using an exemplary embodiment. In the accompanying drawing shows:

Fig. Ij the block diagram of a programmable logic

control

 Fig. 2: the block diagram of the programmable memory cascadable microcontroller for integrated manufacturing including the invention

characteristics

 3 shows an example of the possible command structure of a

cascadable controller circuit. Fig. 4: a controller system using 4 SKM

Figure 1 shows the known block diagram of a programmable logic controller, with the help of the terms used to be clarified. The functional algorithm to be implemented in the control is stored in the form of a tailored program in a memory which is embodied here as read-only memory ROM. This ROM is addressed by a microcontroller MK, which according to the invention consists of one or more cascaded SKMs, via address lines ADR and supplies the corresponding commands or data to the microcontroller via its data lines DAT. The synchronous microcontroller requires a clock line T and a reset line RES. From the machine to be controlled or the process to be controlled, the microcontroller receives process information via sensor lines SENS. Actuator lines AKT are used to send control signals to the controlling machine

27 2 t 7 7 ^s

or processes issued.

The SKM block diagram Fig. 2 is for the production as integrated circuit, z. As in gate array technique, suitable and can individually or cascaded run as a controller system, the function of the microcontroller shown in Fig. 1. It is assumed by way of example that the ROM used has a data width of 8 bits = 1 byte, that an instruction of the SKM or the controller system consists of 4 bytes each of the ROM which have been read successively and that the instruction is that shown in FIG Structure has. However, the realization of the solution according to the invention is not necessarily bound to these assumptions. It is envisaged to use the SKM according to the invention in 3 possible status settings. The first possible status is called Master. It must be set in the individual operation of the SKM and in system operation at an SKM. For example, the master supplies 8 instruction addresses ADRO... 7 to the ROM. The second possible status is called Slave I. The slave 1 can provide, for example, 4 further ROM addresses with the address lines ADRO ... 3 for command addressing in the ROM. It is essential that the addresses supplied by the slave I as well as those automatically updated by the master in each jump command. In the exemplary command structure illustrated in FIG. 3, only 1 SKM may be configured as slave I in each controller system. The third possible status is called slave χ (χ 2. 2). By way of example, each slave χ likewise supplies 4 addresses on the address lines ADRO... 3 for addressing commands in the ROM, but in this status the addresses are changed only in special load commands. It is assumed by way of example that in a control system the master is always addressed with (Jar Systom address SYS "0", the slave I always with the system address SYS "1", Slaves χ with > 1. Furthermore, it is assumed that the address lines of the master ADRO ₁ .. 7 have the lowest value in the instruction addressing in the ROM and the slave address lines (each ADRO ... 3) with the numbering of the slaves assigned increasing weights (see FIG. 4).

According to FIG. 2, the status "master" is set by switching on the externally influenceable master Le..: MSTR. The slave line SLV, which is one of the two slave S ¹ : atus units, is controlled by an inverter. allows. The slave i.-control line SH is activated via the AND gate UG7 when the slave line SLV is active and if via the data lines DAT4 ... 7 with the code "1" via the decoder DC3, which decodes the system addresses , the circuit line SKI is active and, moreover, if the relevant SKM is selected in the controller system with the slave select line SLVA3W active - the latter being activated by the AND-OR gate A0G3, either when the master line MSTR is active and the data lines DAT4 ... 7 provide the code "0" and thus via the decoder DC3 the circuit line SKO is activated, ie, when the master circuit is selected, or when the slave line SLV and the slave select line SLVASW are active. In this way, a circuit configured as a slave independently recognizes at the simultaneous occurrence of the system address "1" and the activated slave selection line SLVASW that it should operate as slave 1 and stores this by setting the slave 1 flip-flop FFS, which is the slave 1 Line SLVl activated and can only be switched off by the reset line RES. The clock center TZ, which is controlled by the external clock line T, generates a 4-phase clock, which is initially routed to the 2 internal clock lines TP via peripheral drivers PT1 on synchronous clock terminals TPA. However, PT1 is only active in conjunction with the master line MSTR, ie it is passive in all slaves. All SKMs of a controller system thus receive, via the synchronous clock terminals TPA and the returned clock lines TPIM to be interconnected, the same clock phases generated by the master, which synchronize them. Lastors are decoded in the decoder DC2 so that the individual clock lines TPO... 3 arise, which control the command execution synchronously in all SKMs. With the synchronous clock terminals TPA is further connected in the connected to the controller system ROM ^1, an addressing of each 4 to a

Command belonging ι bytes executed. Dio Data Leads DATO ... 3 provide the command code for each command. They have been buffered with the clock phase TPO in the command register BREG, on the one hand the function of the command counter BZL, BZH and on the other hand, the work of controller function related assemblies, which are summarized as action control AST controlled. According to different used Aclreßbreiton of 8 bit in the status "Master" and Λ bit in Sta us "slave" is the 3ofehlszählor the SKM divided into the instruction counter BZL, to control the low address lines ADRO ... 3, dio in all status occur, and the instruction counter BZII, for controlling the high address lines ADR4... 7, which are valid only in the status "master". are. In the command decoder DC1, the control signals counting ZL, subroutine jump UPSP, unconditional jump USP, conditional jump 3SPR, subroutine jump UPR and load slave address LDSLV are formed from the outputs of the command register BREG. In the A (! D-OR gate AOG1, the instruction counting line BZ is turned on when the control line is at the ZL Η level or when the control line conditional jump causes BSPR Η level, and the condition selection line 3EDGIN representing the selected branching condition avf L The command counting line BZ is connected in the AND gate UG1 to the master line MSTR to the count command line BFZL, which is connected to the counting input Z dos command counter BZL and active only in the Maater circuit, so that when counting de3 command counter as agreed The Obertragausgang U of the command counter BZL is connected to the counting input Z dos command counter 3ΖΙΊ 1, Ti AND-OR gate A0G2, the line jump SPR then switched to Η level when either the Steuerleiturig Subprogram jump UPSP, or the control line unconditional jump USP is active, or if at the same time the control line conditional jump BSPR and dio condition input line BEDGIM are on H-Pogel, ie always when performing a program jump ict. The line SPR leads to the AND gate UG4,

which only switches the master jump line SPM, which leads to the jump control inputs SP of the instruction counters BZL, BZH, to the Η level when the status Master is programmed. Thus, the instruction counter BZL or BZH only in the status master in the clock phase TP3, which acts on the jump clock inputs CS, loaded on the contents of the data lines DATO ... 3 or DAT4 ... 7 via the jump data inputs DS , Furthermore, the line jump SPR leads to the AND gate UG2, which switches the slave 1-hunt line PLC only to Η level when with her the slave 1 line SLVl is at Η level. Thus, only the low part of the command counter BZL is loaded during jump in the status slave 1, since the slave 1-jump line PLC is only at the slave jump input SS. This has the effect that in the clock phase TP3 at the slave data input DL the applied data is taken over by the data outputs BH of the command counter BZH. The latter is connected at its loading slave input LS to the slave line SLV and at the load clock input CL to the line TPO, so that in the slave state at the outputs BH-buffered with TPO signals of the data lines DAT4 .. .7 are available, so that the instruction counter DZL correctly assumes the part of the jump address intended for slave 1. The instruction counter BZH, which is not required for instruction addresses in the slave state, serves as a buffer register in this status.

The subroutine return UPR control line is connected to the return input RS of the command counter BZL and to the AND gate UG6, which is also controlled by the master line MSTR. Its output is the master return line RSM, which is connected to the return input RS of the command counter BZH, and this only activated in the status master. The load-slave address control line LDSLV leads to the AND gate UG3, whose further inputs are connected to the selection line ASW and the slave line SLV. Its output is the load command line BEFLD, which is connected to the load slave input LS of the command counter BZL and which causes its loading in the same way as the slave jump input SS. This is

the address generated in the status slave "χ" by special command in each case a selected slave of a controller system changeable.

The output lines BL of the command counter BZL control via peripheral drivers PT3, which are constantly active, the address lines ADRO ... 3 for addressing the ROM in each state of the programmable cascadable microcontroller. The output lines BH of the command counter BZH control the address lines ADR4... 7 via the peripheral drivers PT2, which, however, are valid only in the status master by connecting the enable inputs E of the peripheral drivers PT2 to the master line MSTR. In the other status settings, the PT2 are passive, the terminals of the address lines ADR4 ... 7 are then inputs for control signals, which are only required in the slave status. According to the assignment of the instruction counter BZL and BZH to the low or high address lines ADRO ... 3 bzv /. ADR4 ... 7 stack registers SREGL, SREGII are provided for the low and high address portions, respectively, for storing the return addresses in subroutine work which operate as right / left shift registers. The instruction counters BZH / BZL are connected via their shift data terminals SD to corresponding terminals SD of the stack registers SREGII / SREGL. The connection of the stack register SREGL with the control line subroutine jump UPSP controls the right shift. In this case, the address offered by the instruction counter BZL is stored. The connection to the subroutine return UPR control line controls the left shift, with the last address received being returned to the instruction counter BZL. The stack register SREGH executes these operations only in the status master, since only then does the instruction counter BZH operate. The subroutine jump UPSP and subprogram return UPR control lines are therefore linked to the master line MSTR via the AND gates UG5 / UG6 and thereafter form the master subroutine jump line USM and the master return line RSM, respectively, to the shift control inputs SR / SL of the Stack register SREGH lead. In the status slave, the register capacity of the stack register SREGH can be used to save any needed

control additional actuator ZAKT. This is done via the charge lines for additional actuators LDZAKT generated by the action control.

The outputs of the command register BEF which control the action control action AST are connected to the enable circuit FGS whose enable input E is connected to the command command line BEFASW which is connected to the output of the command selection flip-flop FFA which in each clock phase TPO determines the state of the output. Ahlleitung ASW * stores, so that only an instruction content occurs at the output of the enable circuit FGS when the command for the considered SKM was addressed in the controller system. The action control AST receives from the enable circuit FGS this command content on the command action lines BEFAIiT and forms therefrom the charging signals for additional actuators LDZAKT, which lead to the stack register SREGH, and the actuator load signals LDAKT and other action control signals ASTL, which can control any other modules. The actuator load signals LDAKT control the actuator registers AKTREG. Their output lines AKTA are connected to the peripheral drivers PT6 whose outputs are connected to the connections of the SKM for the actuator lines AKT. The enable inputs E of the peripheral drivers PT6 are connected to the AktuatoiTuerleitung AKTE, which is activated by the output of a NAND gate when at least one of the input lines of the NAND gate, namely the slave line SLV or the additional sensor mode line ZSENSM is turned off. The latter is only active in the slave status and connected to the terminal of the address line ADR6 not used in the slave status. In the additional sensor mode slaves use all or part of the Aktuatorleitungen AKT instead of the actuator radio tion as Zusatzsensorleitungon ZSENS.

Analogously, the additional actuator mode is defined, which is also possible only in slave status. In this case, the terminals of the sensor lines SEMS or a part of them act as additional actuator terminals ZAKTA if the address line ADR5, which is not required in the slave status, acts as an additional actuator.

tormodusleitung ZAKTM switched on i3t. The latter, like the slave line SLV, is routed to the input of the AND gate UG8, whose output is connected as an additional actuator enable line EZAKT to the enable input E of the peripheral driver PT4. Their data inputs are the already mentioned additional actuator lines ZAKT coming from the status register SREGH.

The sensor lines SENS are connected to the inputs of a multiplexer MUX1, the terminals of the actuator lines AKT via the additional sensor lines ZSEMS mi ", the inputs of a multiplexer MUX2. Both multiplexer control lines are exemplary on the data lines .DATO ... 3, so that at the output of MUXl the normal condition line BEDGl a sensor selected on the Dater lines and at the output of MUX2 the additional condition line BEDGZ an additionally selected sensor on the inputs of the multiplexer MUX3, whose control input is connected to an output of the command register BREG, so that, depending on the applied command, the condition 3EDG can be selected from the set of sensors or the digit seniors. In the condition flip-flop FFB, the content of the selected condition BEDG is jumpered with j or clock phase TP2 and the state of the selection line ASW in the enable flip-flop FFU. From their outputs, the stored padding line 3EDGF providing information on the state of the selected sensor during clock phase TP2 is communicated with the data input of the peripheral driver PT5, and the condition selection line BEDGASW indicating whether the relevant SKM is in a system of multiple SKMs at the time TP2 was selected, connected to the enable input E of the same peripheral driver PT5; whose output is connected to the condition line BEDGL'angs, therefore, only becomes active if the relevant SKM was provided during the clock phase TP2 for the sensor selection. In a controller system, this can always be just one SKM. Its information, which is connected to the conditional line BEDGL, is available on this line to all SKMs in the controller system and is stored in each of these SKMs on the basis of the conditional line.

Receive SEDGL inbound condition input line BEDGIN and used to decide on conditional jumps in the manner already explained. In Fig. 3, the command structure for a cascaded, usable in a controller system SKM is exemplified so that it is processable with the logic structure described in Fig. 2.

With the command byte BO, which is always present in the clock phase TPO, the command code on the data lines DATO ... 3 is transmitted. On the data lines DAT4 ... 7 is information that depends on the type of command. For jump instructions, 4 bits become the jump address for an SKM

• transmitted in slave status. These are used for the above-described types of branch instructions in slave I and there in clock phase TP3 on dxo address lines ADRO. , .3 switched. In the case of a loading slave address, these 4 bits are taken over by any slave in clock phase TP3.

slave with the data lines DAT4. ,, 7 in the command byte B3. The command byte 31 is always read synchronously with the clock phase TPl and controls the setting of actuators or additional actuators by using the data lines DAT4 ... 7, the selection of an SKM in the controller system and the data lines DATO ... 3, the determination of switching Actuators in this circuit takes place. The defecate byte 32 is always read in synchronism with the clock phase TP2 and can execute a selection of a sensor in the controller system as a jump condition for the entire controller system for the execution of conditional jump instructions. The data lines DAT4 ... 7 select the SKM .m controller system from which a sensor is selected. The data lines DATO ... 3 determine this sensor in the selected circuit.

In the clock phase TP3 is the data byte B3. This includes for jump instructions the 8-bit jump address for the master in the controller system, which switches this address in the clock phase TP3 on its address lines ADRO ... 7. Also the connection of possibly in the data byte BOonon

Address information for a slave is always switched by this only in the clock phase TP3 on its address lines ADRO ... 3.

In Fig. 4, a controller system is shown which consists of using 4 programmable cascadable microcontrollers of Fig. 2 and a program memory ROM. Of the 4 SKMs, one is H level at the input of the master line MSTR in the master state, while the other three are L level at this input in the slave state. The system addresses SYS allocated by way of example are shown in the illustration. As is explained with reference to FIG. 2, they are exemplary encrypted by the data lines DAT4. The data lines DATO ... 7, which originate in the ROM, are connected to the corresponding data inputs DAT of all SKMs. Furthermore, the address outputs ADR4 of the SKM in the slave state, which act in this status as the slave select line SLVASW, are connected to the data lines DAT4... 7 via the selection decoder AD. In control systems up to 5 SKM, with appropriate setting of the system addresses SYS, omitting the selection decoder AD, each of the 4 slave select lines SLVASW be placed directly on each of the data outputs DAT4 ... 7 of the ROM, so that they then the circuit accordingly its specified system address SYS, which is illustrated by the system address table in FIG. It corresponds to the connection to the data line DAT4 of the system address SYS ¹¹ I ", DAT5 corresponds to SYS" 2 ", DAT6 corresponds to SYS" 4. "The 2 clock terminals TPA of the SKM are connected to each other so that the synchronization of the control system from the SKM in the master Status, they are also connected to the address inputs ADRO, 1 of the ROM, where they select 4 3ytes in each instruction., The 8 address line outputs ADRO ... 7 of the master are connected to the address line inputs ADR2 ... 9 and the Acire line outputs ADRO ... 3 of the slaves are each connected to 4 V / additional address line inputs of the ROM, but their use is only required to the extent required by the number of commands to be addressed in the ROM

Control inputs used Addressing outputs ADR5 and ADR6 of the SKM in slave status are exemplarily assigned L level or Η level so that slaves 1 and 2 operate in normal mode while slave 3 is in additional sensor mode. As a result, its actuator line outputs AKT are connected to additional sensor lines ZSENS of the controller system. Since the remaining SKMs operate in normal mode, the actuator line outputs represent AKT actuator lines AKT and the sensor line inputs SENS sensor lines SEMS of the controller system.

The condition line terminals BEDGL of all SKMs are connected to each other, so that the content of the sensor line SEMS or additional sensor line ZSENS selected as jump condition in the controller system is available to each SKM for the corresponding synchronous program execution.

Finally, the reset lines RES of all programmable cascadable microcontroller to a common reset line and their clock lines T are also connected to a common clock line.

The illustrated example of a controller system with 4 programmable cascadable microcontrollers allows the connection of four times the number of sensor lines SENS a single SKM and additional sensors ZSENS to the slave 3. It controls the triple number of actuator lines AKT a single SKM. By selecting the working mode of the circuits in the slave state, more actuator lines can be controlled than sensor line processing (additional actuator mode ZAKT by assigning address lines ADR5 to "H" and ADR6 to "L") or in normal mode of all circuits et v / a same number of both conductors: connect. The addressable ROM capacity is 2 1/2 times that of a single SKM, with the reduced number of slave line outputs ADR4... 7 required in the slave state being advantageously used as control inputs for mode selection as well as system addressing.

Claims (4)

claims A memory programmable cascadable microcontroller, which is integrable and in combination with a program memory forms a programmable logic controller for implementing binary sequencers, which is modular to a controller system erv eiterbar, receives information via sensor lines, outputs actuating commands via actuator lines, to implement its Control functions known iogiche means such as command register, command counter, stack register, action control, peripheral driver, multiplexer, decoder, enable circuit, inverter and gate used and controls the internal command processing by clock phase lines, characterized in that a determinable in their level masts - line (MSTR) each having a first input of AND gates (UGl; UG4; UG5; UG6), a first input of a first AND gate of an AMD OR gate (A0G3), the enable inputs of peripheral drivers (PT1; PT2) and the input of a Inverters (INV) w ie also its output by means of a slave line (SLV), each having a first input of AND gates (UG3; UG7; UG8), a NAMD gate, the first input of a second AND gate of the AND-OR gate (A0G3) and the LS input of a command counter (3ZH) is connected, that a slave 1 line (SLVl) the first Input of an AND gate (UG2) to the output of a flip-flop (FFS) connects a two-pole external component connection (TPA) to both the outputs of the peripheral drivers (PT1) and to the input of a decoder (DC2), a terminal of the high address line (ADR4) with a second input of the AND gate (UG7) as well as with a further input of the second Ui.'D gate of the AND gate (A0G3), as well as with an Ausyang the peripheral driver (PT2) is connected in that the output of the AND-OR gate (A0G3) via a line (ASW) to the second input of the AND gate (UG3), the D input of a flip-flop (FFA) and the D input of another Flip-flops (FFU) is connected, that a second input of the first AND gate of the AND-OR gate (A0G3) dom output (AO) of a decoder (DC3), whose inputs to the data lines (DATO ... 3) are assigned, that is the terminal of a conditional line (BEDGL) with dom output of a peripheral driver (PT5) whose Freigangeingjng is on the output of the flip-flop (FFU), and an input of the AND gate of an AND-OR gate (A0G2) means that the outputs of a command register (3REG) are interconnected to the control inputs of a multiplexer (MUX3) and the data inputs of a release latch (FGS), the output of which is the output of the flip-flop (FFA) and the outputs of the action control (AST), that the count input of a command counter (OZL) to the output of the AND gate (UGl), the jump control input of the instruction counter (BZL, 3ZM) to the output of the AND gate (UG4) and the slave jump input of Befehlszähl ers (GZL) together with the output of the AND gate (UG2) and the data outputs of the command counter (BZH) to the slave data inputs of the command counter (BZL) are connected. 2. Memory Programmable cascadable microcontroller according to claim 1, characterized in that the terminals of the actuator (AKT) with both the outputs of the peripheral driver (PTG) whose release inputs led to the output of the NAND gate, as juch with the data inputs of a multiplexer (MUX2 ), the output of which is connected to a data input of a downstream multiplexer (MUX3), that the signals of the sensor lines (SEfJS) are connected to the outputs of the peripheral drivers (PT4), whose i ^: input inputs to the output of the AND gate (UG8 ) and their data inputs to the outputs of a stack register (SREGII) whose load inputs with outputs of the action control (AST) and its shift control inputs (SR; SL) ^ it the output of the AND gate (UG5) and AND gate (UG6) ver - are connected, and that further terminals of the high address lines, namely (ADR5) with another input of the UMD gate (UG8), (ADR6) with another input of the NAND gate, as well as each individual terminal with further outputs of the peripheral driver (PT2). 3. Programmable memory cascadable microcontroller according to claim I ₁ gekonnzeichnet characterized in that the set input of a flip-flop (FFS) to the output of the UMD gate (UG7) whose other input connected to an Al output of the decoder (DC3) is connected , 4. A memory programmable cascadable microcontroller according to claims 1 to 3, characterized in that when cascading SKM dxe synchronous clock terminals (TPA) of all SKM are connected to each other and address lines of a program memory (ROM), the master line (MSTR) of a first SKM fixed at Η level and those of the other SKM are fixed at L level, the terminal of the address line (ADR4) said further SKM with the ¹ , associated output of a selection decoder (AD) whose inputs with data lines (DAT) occupied and that terminals of further address lines (ADR5; ADR6) of said further SKM for determining the operating mode of the respective SKH are fixed at '-! level''at L level. For this 6 pages drawings