CS242370B1 - Device for synchronizing access to the display memory by a control microprocessor type Z 80 with its reading during image restoration - Google Patents

Abstract

The device relates to the field of computer technology applications and solves the synchronization of access to the memory of a color graphic display by a control microprocessor of the Z 80 type with its reading during image renewal. The advantage of the device is that the described synchronization allows access to the memory for the entire duration of the image and the information transfer is therefore significantly faster than in the conventional method.

Description

SUMMARY OF THE INVENTION The present invention provides a device for synchronizing access to display memory by a control microprocessor of the Z80 type with reading thereof in image refresh.

So far, microprocessor access to the image memory has only been allowed during image decomposition at the time of blanking pulses / ie. approximately one-sixth of the image duration. Access blocked for the remaining time.

The above drawback is overcome by deriving a screen refresh clock and a microprocessor control frequency according to the invention, wherein the memory cycles are divided into screen refresh cycles and microprocessor access cycles, while simultaneously refreshing the information in dynamic memories for refreshing the screens. To ensure that the microprocessor has access to memory only in the cycles dedicated to it, the WAIT signal is generated during that cycle if the microprocessor requires memory access and that the period of these cycles is twice the clock frequency of the microprocessor. Because the microprocessor only tests the WAIT signal at the falling edge of the clock cycle T2 or Tw, there is always one of two cases:

the microprocessor requires memory access in a designated cycle - at the time of the falling edge T2 there is a signal

- 2,242,370

WAIT at log level 1 and access will take place immediately

- the microprocessor requires memory access in the screen refresh cycle - at the time of falling edge T2 the WAIT signal is at log level 0 and a waiting cycle ^T w »is inserted at the falling edge where the WAIT signal is at log level 1 and the previous case is delayed by one hour cycle.

An advantage of the device according to the invention is that the described synchronization will allow access to the memory for the entire duration of the frame and the transmission of information thus proceeds substantially faster than in the case of a conventional connection. , '

The device according to the invention is shown on a block _; The output of oscillator 1 is connected to the input of the four-digit binary counter 2, Output C of this four-digit binary counter 2 is connected to the clock input CLK of the microprocessor 2 · Output D of the four-digit binary counter 2 is connected to the first input circuit a logic total, while the second input of this logic sum circuit 6 is connected to the MRQ request output 2 of the microprocessor 2 ^{and the} output of the logical sum circuit 6 is connected to the input WAIT input of the microprocessor 2 wait cycle.

Giant. Figures 2 and 3 show the waveforms of the individual signals when the microprocessor requests memory access in the dedicated cycle (Fig. 2) and when the microprocessor requires memory access in the image recovery cycle (Fig. 3). The cycles of the TA screen shake cycles and the microprocessor access cycles are periodically alternated ΤΒ »These cycles are distinguished from each other by the logic level at the output D of the 4-digit binary reader 2. In the case of FIG. at the falling edge of T2, the WAIT signal is at log level 1 - TX time - access

- 3 -

242 370 runs immediately. In the case of FIG. 3, a memory access request is made in the video recovery cycle, the WAIT signal is at log 0 -times TX1 at the falling edge T2, and a wait cycle TW is inserted. at the falling edge of which the WAIT signal is already at log 1 — Sas TX2, and access is made at this time, delayed by the original request for one hour cycle ·

Claims (1)

Object of the invention Device for display memory syndrome access control by a microprocessor type Z 80 with reading thereof during image refreshing, characterized in that the output of the oscillator (1) is connected to the input of the four-digit binary counter (2), the output C of the four-digit binary counter (2) is connected to the clock input CLK of the microprocessor (3) and the D output of the 4 digit binary counter (2) is connected to the first input of the logical-sum circuit (4), and the MRQ output of the request microprocessor memory access (3) and logic sum circuit (4) output is connected to the WAIT input of the microprocessor wait cycle request (3) ·