CN86205229U

CN86205229U - Portable digital circuit meter

Info

Publication number: CN86205229U
Application number: CN 86205229
Authority: CN
Inventors: 屠锡余
Original assignee: Individual
Current assignee: Individual
Priority date: 1986-07-17
Filing date: 1986-07-17
Publication date: 1987-08-26

Abstract

The utility model discloses an electronic device for testing a digit circuit. The tester adopts sweep test comparative approach and test card technology, which simplifies circuit construction and breaks down cost. The test of the tester has big capacity, which is convenient for extending test of new species. The utility model has the advantages of visual display, convenient operation, small size, light weight, convenience for carrying, and can test various integrated circuits with less than 28 connecting feet.

Description

Portable digital circuit meter

The utility model is a kind of electronic device of testing digital circuit.

Along with developing by leaps and bounds of electronics industry, digital integrated circuit is applied to every field increasingly extensively, the use amount sharp increase.Wide in variety owing to integrated circuit, profile is different, logic function is complicated and pin has no reasons such as rule, make the design and make a kind of general integrated circuit tester and brought bigger difficulty.At present, integrated circuit tester both domestic and external usually adopts two kinds of methods, and the one, relative method, it takes need are surveyed the method that integrated circuit and preferred circuit compare, the NY3122 type digital IC tester that for example state-run Nanchang radio instrument factory produces; The 2nd, computing method, it takes a circuit-under-test output signal to be compressed into eigenwert by the band compression theory, is the method that generally adopts both at home and abroad in the recent period, for example the 370A digital IC tester of American I ST company.Because the integrated circuit tester circuit structure complexity of taking above method to make, the cost height, can only test the following integrated circuit of 24 pins at present, and can not show pin numbering and the inefficacy character (logical OR level) that lost efficacy, thereby can not generally be adopted with numeral.

The purpose of this utility model provides a kind ofly can test the following various digital circuits of 28 pins, and can demonstrate the pin numbering that lost efficacy takes place, and has the portable digital circuit tester that test capacity is big, cost is low, volume is little, simple to operate.

The utility model takes following technical scheme to realize:

1. scanning comparator circuit.In order to simplify the circuit structure of instrument, reduce cost, and can show the pin numbering of inefficacy character and inefficacy, this instrument adopts each pin to circuit-under-test and preferred circuit to carry out the synchronous scanning test relatively.Differentiate whether circuit-under-test lost efficacy.In test, signal generator (1) pulsing signal by scanning monitor (2) control electronic selection switch (10), (11), carries out synchronous scanning to each corresponding pin of preferred circuit (8) and circuit-under-test (9) and tests.Under the state of determining, through scanning compare test to all pins, after CP counter (3) has reached predetermined value, send a condition change signal and issue sequence, condition generator (4), CP signal and state are transformed into the required fiduciary level signal of circuit-under-test through level converter (7), make preferred circuit (8) and circuit-under-test (9) change test mode, the scanning compare test of new state is carried out in electronic selection switch (10), (11) under the control of scanning monitor (2).After all states all carry out sweep test, output conforms to standard if the circuit-under-test output level is with logic, then sends signal by sequence state generator (4), and qualified display (5) demonstrates qualified signal, synchronous signal generator (1) stops to send signal, whole end of test (EOT).In each sweep test, if the output logic of circuit-under-test (9) is different with the output logic of preferred circuit (8), by the signal of level converter (12) and level Discr. (13) output by logic comparator (14) relatively after, make inefficacy display (15) demonstrate the logic disablement signal; When if the output level of circuit-under-test (9) does not meet standard, level Discr. (13) sends signal, makes inefficacy display (15) demonstrate the level disablement signal.When inefficacy display (15) demonstrates disablement signal, make signal generator (1) stop to send signal, scanning monitor (2) stops scanning, and type scanner (6) promptly demonstrates the numbering of inefficacy pin.

2. test card circuit.The compatibility test problem of, different cultivars circuit dissimilar in order to solve effectively, this instrument is contained in various preferred circuits on the connector for circuit board that has test condition, constitutes various test cards.When the different types of circuit of test, need only the conversion test card and just can realize, both be beneficial to automatic test, bring convenience for the new varieties extend testing again.

3. normalization technology.Because the integrated circuit kind is a lot, pin is arranged has no rule, and each pin all might be input, output, power supply or empty pin, in order to reduce the workload of artificial cognition, this instrument each pin when test is all regarded output terminal as and is tested, and promptly is called the normalization technology.

The utility model compared with prior art has the following advantages:

1. circuit structure is simple, and cost is low;

2. test capacity is big, is convenient to the new varieties extend testing;

3. intuitive display, can not only display circuit whether qualified, and can display circuit be that logic lost efficacy or level lost efficacy, and the numbering that shows the inefficacy pin.

Volume little, in light weight, be easy to carry, easy and simple to handle.

Fig. 1 is the circuit block diagram of this instrument;

Fig. 2 is an electron scanning test philosophy synoptic diagram.

The utility model can be taked following scheme implementation:

By four Sheffer stroke gates of two input ends and resistance, electric capacity looping oscillator as signal generator (1).Scanning monitor (2) is made up of tetrad synchronous addition counter, the conversion of signals of its automatic signal generator in future (1) becomes 8421 yards control electronic selection switch (10), (11), and the type scanner of forming by the fluorescent charactron (6) shows, simultaneously, scanning monitor (2) is also exported a signal and is given the CP counter of being made up of tetrad synchronous addition counter (3), CP counter (3) sends the CP pulse and exports the CP pulse (for sequential circuit by level converter (7) to preferred circuit (8) and circuit-under-test (9), if combinational circuit then needn't use), when the CP pulse arrives predetermined value, send a state pulse and give sequence state generator (4); The sequence state generator of forming by two two tetrad synchronous addition counters (4)---maximum can produce 216 various may under the various combination test signal, this signal passes through level converter (7) to preferred circuit (8) and circuit-under-test (9), provide various tests required various combination fiduciary level signal, level converter (7) is made up of switch triode and variable voltage source, its effect is that the conversion of signals that sequence state generator (4) produces is become the needed standard testing level of circuit-under-test, because the standard testing level difference of all kinds of circuit, so can control variable voltage source by selector switch, obtain required standard testing level.

The realization of scan testing techniques as shown in Figure 2, electronic selection switch (10), (11) are formed with four eight tunnels analogy converters 4051 respectively, for the ease of the pin numbering that shows that circuit-under-test (9) lost efficacy, under the control of scanning monitor (2), two rows pin to circuit-under-test (9) and preferred circuit (8) divides two groups simultaneously row on the circuit-under-test and following row to be carried out sweep test relatively, by two groups of logic comparators and level Discr. control fails display (15).Inefficacy display (15) drives four light emitting diodes respectively by four six anti-phase buffer converters, shows that the level of upper and lower row's pin of circuit-under-test lost efficacy and the logic inefficacy.Logic comparator (14) is made up of two groups of XOR gate, when the circuit-under-test and the logic of preferred circuit are exported when consistent, the XOR gate output low level, if the logic of circuit-under-test and preferred circuit is exported when inconsistent, XOR gate output high level, make and indicate the row's of going up logic inefficacy in the inefficacy display (15) or arrange the lumination of light emitting diode that logic lost efficacy down, the logic that indicates circuit lost efficacy, simultaneously by charactron reading scan state, in case scanning monitor stops scanning, this moment, display then showed the pin number of this inefficacy pin.

For the ease of the integrated circuit of conversion test different cultivars, preferred circuit is directly installed on the test card of tape test condition, just can carry out the test of variety classes circuit as long as change test card.

Claims

1, a kind of portable digital circuit tester of testing digital circuit, by signal generator [1], scanning monitor [2], CP counter [3], sequence state generator [4], qualified display [5], type scanner [6] and inefficacy display compositions such as [15], it is characterized in that the signal that signal generator [1] sends passes through scanning monitor [2] control electronic selection switch [10], [11], each pin of preferred circuit [8] and circuit-under-test [9] is carried out the synchronous scanning test relatively, and the output signal of level converter [12] and level Discr. [13] is through logic comparator [14] control fails display [15] demonstration of losing efficacy; CP counter [3] sends the state variation pulse when arriving predetermined value, and the various composite signals that sequence state generator [4] sends are transformed into the required various standard measuring signals of circuit-under-test by level converter [7], and control qualified display [5]; Type scanner [6] shows inefficacy pin numbering by scanning monitor [2] control.

2,, it is characterized in that electronic selection switch (10), (11) are made up of the four eight tunnels analogy converters that upper and lower two row's pins of control criterion circuit (8) and circuit-under-test (9) carry out sweep test simultaneously respectively according to the tester described in the claim 1.

3,, it is characterized in that preferred circuit is installed on the plugboard of tape test condition and form test card according to the tester described in the claim 1.