CN223884947U - POE protection circuit - Google Patents

Abstract

This application provides a PoE protection circuit, which includes an input terminal for inputting electrical signals and an output terminal for supplying power to the internal chip of the PoE. A PMOS transistor is connected between the input terminal and the output terminal, with the source and drain of the PMOS transistor connected to the input terminal and the output terminal, respectively. The gate of the PMOS transistor is connected to a first ground terminal. The circuit also includes a first current-limiting and voltage-regulating component, a first voltage-regulating component, and an NMOS transistor connected in sequence. The end of the first current-limiting and voltage-regulating component away from the first voltage-regulating component is connected between the input terminal and the source of the PMOS transistor. The drain of the NMOS transistor is connected between the gate of the PMOS transistor and the first ground terminal. The source of the NMOS transistor is connected to the first voltage-regulating component, and the gate of the NMOS transistor is connected between the first voltage-regulating component and the first current-limiting and voltage-regulating component. This application reduces the possibility of damage to the internal chip of the PoE when the current is too high, ensuring the normal operation of the PoE.

Description

POE protection circuit

Technical Field

The application relates to the technical field of POE circuits, in particular to a POE protection circuit.

Background

POE (Power over Ethernet) is a technology for simultaneously transmitting data and power through a network cable so that a remote device can obtain power supply without an additional cable, and is widely used in applications such as VoIP phones, wireless phones, and monitoring cameras. With further development of scientific technology, POE is not only used for traditional network devices, but also plays an important role in the field of internet of things and intelligent architecture.

The POE design within the current electronics industry is basically dependent on the POE inter-integrated chips. Many POEs are inside not to design the circuit that is used for protecting the chip, often can cause the damage of the inside chip of POEs when the too big condition of input current appears in the input of POEs, and difficult maintenance behind the POE chip damage, and the chip price is higher, cost of maintenance is also high, has influenced the use of POEs greatly.

Disclosure of utility model

In order to overcome the defect that the chip inside the POE is damaged when the input current of the input end of the traditional POE is overlarge, the application provides a POE protection circuit.

The application provides a POE protection circuit, which comprises an input end for inputting an electric signal and an output end for supplying power to a POE internal chip, wherein a PMOS (P-channel metal oxide semiconductor) tube is connected between the input end and the output end, a source electrode and a drain electrode of the PMOS tube are respectively connected with the input end and the output end, a grid electrode of the POMS tube is connected with a first grounding end, the POE protection circuit further comprises an overcurrent protection component, the overcurrent protection component comprises a first current-limiting voltage-stabilizing component, a first voltage-regulating component and an NMOS (N-channel metal oxide semiconductor) tube which are sequentially connected, one end of the first current-limiting voltage-stabilizing component, which is far away from the first voltage-regulating component, is connected between the input end and the source electrode of the PMOS tube, a drain electrode of the NMOS tube is connected between the grid electrode of the PMOS tube and the first grounding end, the source electrode of the NMOS tube is connected with the first voltage-regulating component, the grid electrode of the NMOS tube is connected between the first voltage-regulating component and the first current-limiting voltage-stabilizing component, and the first voltage-regulating component is used for regulating the connection and disconnection of the NMOS tube, and when the current of the input end is larger than a current preset value.

In some embodiments, the first voltage regulating component comprises an NPN triode and a first regulating resistor for regulating a current preset value, two ends of the first regulating resistor are respectively connected with an emitter and a base of the NPN triode, a collector of the NPN triode is connected with the first current-limiting voltage-stabilizing component, the base of the NPN triode is connected between the first regulating resistor and a source of the NMOS tube, and an emitter of the NPN triode is connected with a second grounding end.

In some embodiments, the POE protection circuit further includes an under-voltage protection component, one end of the under-voltage protection component is connected to the gate of the NMOS transistor, and the other end of the under-voltage protection component is connected to the source of the NMOS transistor, and when the input voltage at the input end is less than the first preset voltage value, the NMOS transistor is disconnected.

In some embodiments, the under-voltage protection component comprises a second adjusting resistor and a first diode which are connected in parallel, wherein the anode of the first diode is connected with the grid electrode of the NMOS tube, and the cathode of the first diode is connected with the source electrode of the NMOS tube.

In some embodiments, the undervoltage protection assembly further includes a filter device in parallel with the second regulation resistor.

In some embodiments, the first current-limiting voltage-stabilizing component comprises a first current-limiting resistor and a first voltage-stabilizing diode which are mutually connected in series, wherein the positive electrode of the first voltage-stabilizing diode is connected with the first current-limiting resistor, and the negative electrode of the first voltage-stabilizing diode is connected with the collector electrode of the NPN triode.

In some embodiments, the POE protection circuit further includes an overvoltage protection component, the overvoltage protection component includes a second current-limiting voltage-stabilizing component connected in parallel with the overcurrent protection circuit and a second voltage-regulating component connected between the second current-limiting voltage-stabilizing component and the PMOS transistor, one end of the second current-limiting voltage-stabilizing component is connected between the source and the input end of the PMOS transistor, the other end is connected between the drain and the first ground end of the NMOS transistor, one end of the second voltage-regulating component is connected between the gate and the first ground end of the PMOS transistor, the other end is connected between the source and the input end of the PMOS transistor, and when the input voltage of the input end is greater than a second predetermined voltage value, the PMOS transistor is disconnected.

In some embodiments, the second current-limiting voltage-stabilizing component includes a second current-limiting resistor and a second zener diode connected in series, wherein a cathode of the second zener diode is connected between a drain electrode of the NMOS tube and the first ground terminal, an anode of the second zener diode is connected with the second current-limiting resistor, and an end of the second current-limiting resistor, which is far away from the second zener diode, is connected between the input terminal and a source electrode of the PMOS tube.

In some embodiments, the second voltage regulating component includes a PNP triode, a base of the PNP triode is connected between the second current limiting resistor and the second zener diode, an emitter of the PNP triode is connected between the input terminal and the source of the PMOS, a collector of the PNP triode is connected between the gate of the PMOS and the first ground terminal, the second voltage regulating component further includes a first voltage regulating resistor connected between the second current limiting resistor and the base of the PNP triode, a second voltage regulating resistor connected between the collector of the PNP triode and the source of the PMOS, and a third voltage regulating resistor connected between the gate of the PMOS and the source of the second zener diode, an end of the first voltage regulating resistor away from the PNP triode is connected between the second current limiting resistor and the second zener diode, an end of the second voltage regulating resistor away from the PNP triode is connected between the input terminal and the source of the PMOS, and the collector of the PNP triode is simultaneously connected between the PMOS and the third voltage regulating resistor and the second regulating resistor and the third regulating resistor.

In some embodiments, the first, second, and third conditioning resistors have the same resistance.

The technical scheme of the application at least comprises the following advantages:

1. According to the POE protection circuit, when the input current is smaller than or equal to the current preset value, the voltage of the grid electrode and the source electrode of the NMOS tube is regulated through the first voltage regulating component, so that the grid electrode voltage of the NMOS tube is larger than the source electrode voltage, the NMOS tube is conducted, the PMOS tube is conducted at the moment, the input end of the POE can normally supply power to the POE internal chip, and the POE can normally supply power. When the input current is greater than the current preset value, under the action of the first voltage regulating component, the grid voltage of the NMOS tube is pulled down, the NMOS tube is disconnected, the PMOS tube is disconnected at the moment, the input end of the POE is not supplied with power to the internal chip, the possibility that the POE internal chip is damaged when the current is overlarge is reduced, and normal use of the POE is ensured.

2. Not only the too big damage that can cause the inside chip of POE of electric current, current POE all can damage the inside chip of POE when input voltage is too little (under-voltage) or too big (excessive pressure), influences the use of POE. The under-voltage protection component reduces the possibility of damage of the POE internal chip when the voltage of the input end is too small, and the over-voltage protection component reduces the possibility of damage of the POE internal chip when the input voltage is too high, so that the POE internal chip is protected in overvoltage.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a POE protection circuit according to an exemplary embodiment of the present application.

Reference numerals illustrate:

1. The power supply comprises an input end, an output end, a 3-filter device, a 4-first grounding end, a 5-second grounding end, a Q1-PMOS (P-channel metal oxide semiconductor) tube, a Q2-NMOS (N-channel metal oxide semiconductor) tube, a Q3-NPN triode, a Q4-PNP triode, an R1-first regulating resistor, an R2-second regulating resistor, an R3-first current limiting resistor, an R4-second current limiting resistor, an R5-first voltage regulating resistor, an R6-second voltage regulating resistor, an R7-third voltage regulating resistor, a D1-first diode, a D2-first voltage stabilizing diode, a D3-second voltage stabilizing diode.

Detailed Description

The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intermediate medium, and in communication with each other between two elements, and wirelessly connected, or wired. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.

Referring to fig. 1, the application provides a POE protection circuit, which comprises an input terminal 1 for inputting an electrical signal and an output terminal 2 for supplying power to a POE internal chip, wherein a PMOS transistor Q1 is connected between the input terminal 1 and the output terminal 2, a source electrode and a drain electrode of the PMOS transistor Q1 are sequentially connected with the input terminal 1 and the output terminal 2 respectively, and a gate electrode of the poms transistor Q1 is connected with a first grounding terminal 4. The POE protection circuit further comprises an overcurrent protection component, the overcurrent protection component comprises a first current-limiting voltage-stabilizing component, a first voltage-regulating component and an NMOS tube Q2 which are sequentially connected, one end, far away from the first voltage-regulating component, of the first current-limiting voltage-stabilizing component is connected between the input end 1 and the source electrode of the PMOS tube Q1, the drain electrode of the NMOS tube Q2 is connected between the grid electrode of the PMOS tube Q1 and the first grounding end 4, the source electrode of the NMOS tube Q2 is connected with the first voltage-regulating component, the grid electrode of the NMOS tube Q2 is connected between the first voltage-regulating component and the first current-limiting voltage-stabilizing component, the first voltage-regulating component is used for regulating the connection and disconnection of the NMOS tube Q2, and when the current of the input end 1 is larger than a current preset value, the NMOS tube Q2 is disconnected.

Foretell POE protection circuit, when input current is less than or equal to the electric current default, through the voltage of first voltage regulating assembly regulation NMOS pipe Q2 grid and source for NMOS pipe Q2's grid voltage is greater than source voltage, and NMOS pipe Q2 switches on, and PMOS pipe Q1 switches on this moment, and POE's input 1 can normally supply power to the inside chip of POE, and POE can normally supply power promptly. When the input current is greater than the current preset value, under the action of the first voltage regulating component, the grid voltage of the NMOS tube Q2 is pulled down, the NMOS tube Q2 is disconnected, the PMOS tube Q1 is disconnected at the moment, the input end 1 of the POE is not supplied to the internal chip any more, the possibility that the POE internal chip is damaged when the current is overlarge is reduced, and normal use of the POE is guaranteed.

In some embodiments, referring to fig. 1, the first voltage regulating component includes an NPN triode Q3 and a first regulating resistor R1 for regulating a current preset value, two ends of the first regulating resistor R1 are respectively connected with an emitter and a base of the NPN triode Q3, a collector of the NPN triode Q3 is connected with the first current-limiting voltage-stabilizing component, a base of the NPN triode Q3 is connected between the first regulating resistor R1 and a source of the NMOS tube Q2, and an emitter of the NPN triode Q3 is connected with the second ground terminal 5. When the input current of the input end 1 is smaller than or equal to a current preset value, the NPN triode Q3 is disconnected, the NMOS tube Q2 and the PMOS tube Q1 are conducted, POE is powered normally at the moment, when the current of the input end 1 is larger than the current preset value, the base voltage of the NPN triode Q3 is larger than the emitter voltage, the NPN triode Q3 is conducted at the moment, the emitter and the collector of the NPN triode Q3 are communicated to the ground, the grid voltage of the NMOS tube Q2 is lowered, the NMOS tube Q2 is disconnected, the input end 1 of the POE does not supply power to the POE internal chip any more, and damage of the POE internal chip under overlarge current can be prevented. Specifically, by adjusting the blocking of the first adjusting resistor R1, the magnitude of the current threshold, that is, the magnitude of the overcurrent, can be adjusted.

In some embodiments, referring to fig. 1, the first current-limiting voltage stabilizing component includes a first current-limiting resistor R3 and a first zener diode D2 connected in series, the positive electrode of the first zener diode D2 is connected to the first current-limiting resistor R3, and the negative electrode of the first zener diode D2 is connected to the collector of the NPN triode Q3. The first current limiting resistor R3 plays a role in current limiting, stability of the protection circuit is improved, and the first zener diode D2 is used for judging the magnitude of the input voltage. Specifically, the first zener diode D2 is a 30V zener diode, the resistance of the first current limiting resistor R3 is 10kΩ, and the resistance of the first adjusting resistor R1 is 0.25 Ω.

Not only the too big damage that can cause the inside chip of POE of electric current, current POE all can damage the inside chip of POE when input 1 voltage is too little (under-voltage) or too big (excessive pressure), influences the use of POE.

In some embodiments, referring to fig. 1, the protection circuit further includes an under-voltage protection component, one end of the under-voltage protection component is connected to the gate of the NMOS transistor Q2, and the other end is connected to the source of the NMOS transistor Q2, and when the input voltage of the input terminal 1 is less than the first preset voltage value, the NMOS transistor Q2 is turned off. When the value of the input voltage is smaller than the conducting voltage of the first zener diode D2, the first zener diode D2 cannot be conducted, POE cannot normally supply power, when the input voltage is larger than the conducting value of the first zener diode D2 and smaller than a first preset voltage value, the grid voltage of the NMOS tube Q2 is lower than the conducting voltage of the NMOS tube Q2, the NMOS tube Q2 is disconnected, POE cannot normally supply power, and the possibility that an internal chip of the POE is damaged when the voltage of the input end 1 is too small is reduced.

Further, referring to fig. 1, the under-voltage protection component includes a second adjusting resistor R2 and a first diode D1 connected in parallel, where an anode of the first diode D1 is connected to a gate of the NMOS transistor Q2, and a cathode of the first diode D1 is connected to a source of the NMOS transistor Q2. When the voltage input by the input end 1 is larger than the conducting voltage of the first zener diode D2 and smaller than the first voltage preset value, the first zener diode D2 is conducted, the voltage cannot break down the first diode D1 after the first zener diode D2 is conducted, the grid voltage of the NMOS tube Q2 is lower than the conducting voltage of the NMOS tube Q2, the NMOS tube Q2 is disconnected, POE cannot supply power to the internal chip, and the possibility of damage of the internal chip when the voltage of the input end 1 is too small is reduced. When the input voltage is greater than or equal to a first preset voltage value, the first zener diode D2 is conducted, the NMOS tube Q2 is conducted, the PMOS tube Q1 is conducted, the input end 1 of the POE can normally supply power to the internal chip, and the POE can normally supply power. When the input voltage is greater than or equal to a first preset voltage value and the voltage of the turned-on first zener diode D2 can break down the first diode D1, the first diode D1 is turned on, the gate voltage of the NMOS tube Q2 reaches the turn-on voltage of the NMOS tube Q2 and stabilizes at the turn-on voltage of the first diode D1, and the NMOS tube Q2 and the PMOS tube Q1 are both turned on, so that POE can stably supply power to an internal chip, and the stability of POE power supply is improved.

Specifically, taking the on voltage of the first diode D1 as an example, when the input voltage of the input terminal 1 is greater than 30V and less than 33V, the first zener diode D2 is turned on, the voltage after being turned on cannot break down the first diode D1, the gate voltage of the NMOS transistor Q2 is less than 3V, the NMOS transistor Q2 is turned off, and POE cannot supply power normally. When the voltage of the input end 1 is greater than or equal to 33V and the input voltage is less than 12V, the gate voltage of the gate of the NMOS transistor Q2 is greater than or equal to the turn-on voltage of the NMOS transistor Q2, the NMOS transistor Q2 is turned on, and POE can supply power normally. Further, when the voltage of the input end 1 is greater than or equal to 42V, the first zener diode D2 is conducted, the conducted voltage can enable the grid voltage of the NMOS tube Q2 to be stabilized at 12V, so that POE can stably supply power to an internal chip, and the stability of POE power supply is improved. The voltage under-voltage protection value of the under-voltage protection component can be changed by adjusting the value of the on voltage of the first zener diode D2.

In some embodiments, the undervoltage protection assembly further comprises a filter device 3 connected in parallel with the second regulation resistor R2. The filter device 3 is a capacitor, has the function of delaying the opening of the NMOS tube Q2, and the filter device 3 is charged firstly when the protection circuit is electrified, so that the grid voltage of the NMOS tube Q2 is linearly increased, the phenomenon that other devices are burnt out due to overlarge current in the instant of electrifying is prevented, and the stability of POE power supply is further improved.

In some embodiments, referring to fig. 1, the poe protection circuit further includes an overvoltage protection component, where the overvoltage protection component includes a second current-limiting voltage-stabilizing component connected in parallel with the overcurrent protection circuit and a second voltage-regulating component connected between the second current-limiting voltage-stabilizing component and the PMOS transistor Q1, one end of the second current-limiting voltage-stabilizing component is connected between the source electrode of the PMOS transistor Q1 and the input terminal 1, the other end is connected between the drain electrode of the NMOS transistor Q2 and the first ground terminal 4, one end of the second voltage-regulating component is connected between the gate electrode of the PMOS transistor Q1 and the first ground terminal 4, the other end is connected between the source electrode of the PMOS transistor Q1 and the input terminal 1, and when the input voltage of the input terminal 1 is greater than a second preset voltage value, the PMOS transistor Q1 is disconnected.

When the input voltage of the input end 1 is larger than a second preset voltage value, the PMOS tube Q1 is disconnected, the POE input end 1 cannot normally supply power to the POE internal chip, the possibility that the POE internal chip is damaged when the input voltage is too high is reduced, and therefore the POE internal chip is protected in overvoltage.

In some embodiments, referring to fig. 1, the second current-limiting voltage stabilizing component includes a second current-limiting resistor R4 and a second zener diode D3 connected in series with each other, a cathode of the second zener diode D3 is connected between the drain of the NMOS transistor Q2 and the first ground terminal 4, an anode of the second zener diode D3 is connected to the second current-limiting resistor R4, and an end of the second current-limiting resistor R4 away from the second zener diode D3 is connected between the input terminal 1 and the source of the PMOS transistor Q1. The second voltage regulating component comprises a PNP triode Q4, wherein a base electrode of the PNP triode Q4 is connected between a second current limiting resistor R4 and a second voltage stabilizing diode D3, an emitter electrode of the PNP triode Q4 is connected between an input end 1 and a source electrode of a PMOS, a collector electrode of the PNP triode Q4 is connected between a grid electrode of the PMOS tube Q1 and a first grounding end 4, the second voltage regulating component further comprises a first voltage regulating resistor R5 connected between the second current limiting resistor R4 and a base electrode of the PNP triode Q4, a second voltage regulating resistor R6 connected between a collector electrode of the PNP triode Q4 and a source electrode of the PMOS tube Q1 and a third voltage regulating resistor R7 connected between a grid electrode of the PMOS tube Q1 and the source electrode of the second voltage stabilizing diode D3, one end of the first voltage regulating resistor R5, which is far away from the PNP triode Q4, is connected between the second current limiting resistor R4 and the second voltage stabilizing diode D3, one end of the second voltage regulating resistor R6, which is far away from the PNP triode Q4, is connected between the input end 1 and the PMOS tube Q1, and the third voltage regulating resistor R7 is connected between the first voltage regulating resistor R7 and the third voltage regulating resistor R2. The resistance values of the first adjusting resistor R1, the second adjusting resistor R2 and the third adjusting resistor are the same.

Specifically, the conducting voltage of the second zener diode D3 is a second preset voltage value, when the input voltage is lower than the second preset voltage value, the second zener diode D3 cannot be conducted, at this time, the base voltage and the emitter voltage of the PNP triode Q4 are equal, the PNP triode Q4 is turned off, the source voltage of the PMOS tube Q1 is higher than the gate voltage, the PMOS tube Q1 is normally conducted, the input terminal 1 of the POE normally supplies power to the POE internal chip, and the POE normally supplies power. When the input voltage is greater than or equal to a second preset voltage value, the second zener diode D3 is conducted, the base voltage of the PNP triode Q4 is smaller than the emitter voltage, the PNP triode Q4 is conducted, the voltages of the second voltage regulating resistor R6 and the third voltage regulating resistor R7 are pulled up to the voltage value of the input end 1 by the PNP triode Q4 at the moment, the grid voltage of the PMOS tube Q1 is equal to the source voltage, the PMOS tube Q1 is disconnected, the POE input end 1 cannot normally supply power to the POE internal chip, the possibility that the POE internal chip is damaged when the input voltage is too high is reduced, and the POE internal chip is protected when overvoltage.

Specifically, the on voltage of the second zener diode D3 may be 58V, and the voltage overvoltage protection value of the overvoltage protection component may be adjusted by adjusting the on voltage value of the second zener diode D3.

It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.

Claims (10)

1. The POE protection circuit is characterized by comprising an input end for inputting an electric signal and an output end for supplying power to a POE internal chip, wherein a PMOS (P-channel metal oxide semiconductor) tube is connected between the input end and the output end, a source electrode and a drain electrode of the PMOS tube are respectively connected with the input end and the output end, a grid electrode of the POMS tube is connected with a first grounding end, the POE protection circuit further comprises an overcurrent protection component, the overcurrent protection component comprises a first current-limiting voltage-stabilizing component, a first voltage-regulating component and an NMOS (N-channel metal oxide semiconductor) tube which are sequentially connected, one end of the first current-limiting voltage-stabilizing component, far from the first voltage-regulating component, is connected between the input end and the source electrode of the PMOS tube, a drain electrode of the NMOS tube is connected between the grid electrode of the PMOS tube and the first grounding end, the source electrode of the NMOS tube is connected with the first voltage-regulating component, the grid electrode of the NMOS tube is connected between the first voltage-regulating component and the first current-limiting voltage-stabilizing component, and the first voltage-regulating component is used for regulating the connection and disconnection of the NMOS tube, and when the current of the input end is larger than a current preset value.

2. The POE protection circuit of claim 1, wherein said first voltage regulating assembly comprises an NPN triode and a first regulating resistor for regulating a preset current value, two ends of said first regulating resistor are respectively connected with an emitter and a base of said NPN triode, a collector of said NPN triode is connected with said first current limiting and voltage stabilizing assembly, a base of said NPN triode is connected between said first regulating resistor and a source of said NMOS, and an emitter of said NPN triode is connected with said second ground terminal.

3. The POE protection circuit of claim 2, further comprising an under-voltage protection component, wherein one end of said under-voltage protection component is connected to the gate of the NMOS transistor, and the other end is connected to the source of the NMOS transistor, and when the input voltage at the input terminal is less than the first preset voltage value, the NMOS transistor is disconnected.

4. A POE protection circuit as recited in claim 3 wherein said undervoltage protection assembly comprises a second regulating resistor and a first diode connected in parallel with each other, the positive electrode of the first diode being connected to the gate of the NMOS and the negative electrode being connected to the source of the NMOS.

5. The POE protection circuit of claim 4, wherein said undervoltage protection assembly further comprises a filter device in parallel with the second regulator resistor.

6. A POE protection circuit as recited in claim 3 wherein said first current limiting and voltage stabilizing assembly comprises a first current limiting resistor and a first voltage stabilizing diode connected in series with each other, the positive electrode of the first voltage stabilizing diode being connected to the first current limiting resistor, the negative electrode of the first voltage stabilizing diode being connected to the collector of the NPN triode.

7. The POE protection circuit of claim 5, further comprising an overvoltage protection component, said overvoltage protection component comprising a second current limiting voltage stabilizing component connected in parallel with the overcurrent protection circuit and a second voltage regulating component connected between the second current limiting voltage stabilizing component and the PMOS transistor, one end of the second current limiting voltage stabilizing component being connected between the source and the input terminal of the PMOS transistor, the other end being connected between the drain of the NMOS transistor and the first ground terminal, one end of the second voltage regulating component being connected between the gate of the PMOS transistor and the first ground terminal, the other end being connected between the source and the input terminal of the PMOS transistor, the PMOS transistor being disconnected when the input voltage of the input terminal is greater than a second predetermined voltage value.

8. The POE protection circuit of claim 7, wherein said second current limiting and voltage stabilizing assembly comprises a second current limiting resistor and a second zener diode connected in series with each other, the cathode of the second zener diode being connected between the drain of the NMOS transistor and the first ground, the anode of the second zener diode being connected to the second current limiting resistor, the end of the second current limiting resistor remote from the second zener diode being connected between the input terminal and the source of the PMOS transistor.

9. The POE protection circuit of claim 8, wherein said second voltage regulator assembly comprises a PNP transistor, a base of the PNP transistor is connected between the second current limiting resistor and the second zener diode, an emitter of the PNP transistor is connected between the input terminal and the source of the PMOS, a collector of the PNP transistor is connected between the gate of the PMOS and the first ground terminal, the second voltage regulator assembly further comprises a first voltage regulator resistor connected between the second current limiting resistor and the base of the PNP transistor, a second voltage regulator resistor connected between the collector of the PNP transistor and the source of the PMOS, and a third voltage regulator resistor connected between the gate of the PMOS and the second zener diode, an end of the first voltage regulator resistor remote from the PNP transistor is connected between the second current limiting resistor and the second zener diode, an end of the second voltage regulator resistor remote from the PNP transistor is connected between the input terminal and the source of the PMOS, and the collector of the PNP transistor is simultaneously connected between the PMOS and the third voltage regulator resistor.

10. The POE protection circuit of claim 8, wherein said first, second and third conditioning resistors have the same resistance.