CN223471116U

CN223471116U - Chip test fixture

Info

Publication number: CN223471116U
Application number: CN202422717174.1U
Authority: CN
Inventors: 成玉磊; 董自勇; 卞剑涛; 花於锋; 严双超; 夏懂炎
Original assignee: Jiangsu Sunfy Photoelectronic Tech Co ltd
Current assignee: Jiangsu Sunfy Photoelectronic Tech Co ltd
Priority date: 2024-11-08
Filing date: 2024-11-08
Publication date: 2025-10-24
Anticipated expiration: 2034-11-08

Abstract

The present application relates to the technical field of chip testing, and in particular to a chip testing tool, comprising an adapter board for mounting a chip to be tested, a detection port for placing the chip to be tested, and a bottom wall of the detection port provided with a plurality of slots for inserting the chip pins; a test fixture, the test fixture being mounted on the adapter board, the test fixture being used to clamp the chip to be tested on the adapter board, the test fixture being provided with a card hole for the chip to be clamped and then fall into the detection port; an FPC line interface, the FPC line interface being mounted on the adapter board so that after the pins of the chip to be tested are inserted into the slots, the output end of the pins of the chip to be tested is connected to the connection end of the FPC line interface through a circuit; and the FPC line interface being externally connected to a data acquisition system. The present application has the advantages of facilitating chip testing, improving chip testing efficiency, and ensuring test quality.

Description

Chip test fixture

Technical Field

The application relates to the technical field of chip testing, in particular to a chip testing tool.

Background

At present, a chip can be specially tested during packaging, but equipment investment is large, investment is not considered for some small-quantity or experimental products, and the chip is tested after being directly SMT on a circuit board instead, but the influence of factors such as poor chip welding, abnormality of the chip, abnormality of a PCB and the like exists, whether the chip is poor cannot be judged correctly, and PCBA finished product yield is low. Therefore, reliable testing tools are urgently needed to screen incoming materials of incoming material chips so as to judge the chip state and improve the yield of the detector.

Disclosure of utility model

In order to solve the above-mentioned problems in the background art, the present application provides a chip testing tool.

The application provides a chip testing tool which adopts the following technical scheme:

The chip testing tool comprises an adapter plate, a testing fixture, an FPC wire interface, a data acquisition system and a circuit connection device, wherein the adapter plate is used for installing a chip to be tested, a detection port for placing the chip to be tested is formed in the adapter plate, a plurality of slots for inserting pins of the chip to be tested are formed in the bottom wall of the detection port, the testing fixture is installed on the adapter plate and used for clamping the chip to be tested on the adapter plate, a clamping hole for enabling the chip to fall into the detection port after the chip is clamped in is formed in the testing fixture, the FPC wire interface is installed on the adapter plate, after the pins of the chip to be tested are inserted into the slots, the pin output ends of the chip to be tested are connected with the connection ends of the FPC wire interface through the circuit, and the FPC wire interface is externally connected with the data acquisition system.

Preferably, the clamping hole is square, the four vertex angles of the clamping hole are provided with abdication grooves, and the notch of each abdication groove is provided with a flexible protection pad.

Preferably, auxiliary holes communicated with the clamping holes are respectively formed in the periphery of the test fixture.

Preferably, the inner side wall of the slot is provided with a conductive layer, and the thickness of the conductive layer is 5-10 mu m.

Preferably, the bottom of the adapting plate is provided with supporting feet with adjustable height, and the adapting plate can be kept horizontal on different planes through the supporting feet.

Preferably, the supporting legs comprise supporting columns and hemispherical bases, one ends of the supporting columns in the length direction are fixedly connected to the bases, the other ends of the supporting columns are connected to the adapter plates in a threaded mode, and one sides of hemispherical cambered surfaces of the bases are used for being abutted to a placing plane.

Preferably, the adapting plate is provided with a plurality of heat dissipation channels, and the heat dissipation channels are communicated with the detection port.

In summary, the chip testing fixture has the following beneficial effects that when the chip testing fixture is actually used, the chip to be tested is aligned to the clamping hole of the testing fixture and is placed in the clamping hole, the chip falls into the detection port of the adapting plate through the clamping hole, and the chip pins are inserted into the slots on the bottom wall of the detection port. At this moment, the chip is fixed by the chucking of test fixture, and the chip pin forms circuit connection through slot inside wall conducting layer and FPC line interface, and external data acquisition system can begin to test the chip that awaits measuring, and then has guaranteed the test efficiency of chip, the quality of chip of assurance also.

Drawings

Fig. 1 is a top view of a chip test fixture according to an embodiment of the present application.

Fig. 2 is a front view of a chip test fixture according to an embodiment of the present application.

The reference numerals indicate that 1, an adapter plate, 2, a detection port, 3, a slot, 31, a conductive layer, 4, a test fixture, 41, a clamping hole, 42, a yielding groove, 43, an auxiliary hole, 5, supporting feet, 51, a base, 52, a supporting column, 6, a heat dissipation channel, 7 and an FPC wire interface.

Detailed Description

The application is described in further detail below with reference to fig. 1-2.

The embodiment of the application discloses a chip testing tool. Referring to fig. 1 and 2, the test fixture comprises an adapter plate 1, wherein the adapter plate 1 is used for installing a chip to be tested, a detection port 2 for placing the chip to be tested is arranged on the adapter plate 1 in a downward sunken mode, a plurality of slots 3 for inserting pins of the chip to be tested are arranged on the bottom wall of the detection port 2, a conductive layer 31 is arranged on the inner side wall of each slot 3, the conductive layer 31 is a copper plating layer, the thickness of the conductive layer is 5-10 mu m, good electric connection between the pins of the chip and a test circuit is guaranteed, a test fixture 4 is arranged on the adapter plate 1, the test fixture 4 is used for clamping the chip to be tested on the adapter plate 1, a clamping hole 41 for enabling the chip to be tested to fall into the detection port 2 after being clamped in is formed in the test fixture 4, an FPC wire interface 7 is arranged on the adapter plate 1, after the pins of the chip to be tested are inserted into the slots 3, output ends of the pins of the chip to be tested are connected to the connection ends of the FPC wire interface 7 through circuits, and the FPC wire interface 7 is externally connected with a data acquisition system.

Referring to fig. 1 and 2, the clamping hole 41 is square, and the four vertex angles of the clamping hole 41 are provided with the giving-up grooves 42, so that the setting of the giving-up grooves 42 is convenient for a worker to take and put a chip to be tested, and a finger is convenient to put. Auxiliary holes 43 communicated with the clamping holes 41 are respectively formed around the test fixture 4. The bottom of adapter board 1 is provided with height-adjustable's supporting legs 5, can make adapter board 1 keep the level on different planes through supporting legs 5, and supporting legs 5 include support column 52 and hemispherical base 51, and support column 52 length direction's one end fixed connection is in base 51, and the other end threaded connection is in adapter board 1, and hemispherical cambered surface one side of base 51 is used for the butt to place the plane. The adapter plate 1 is provided with a plurality of heat dissipation channels 6, and the heat dissipation channels 6 are communicated with the detection port 2, so that heat dissipation of the chip in the testing process is facilitated.

The implementation principle of the chip testing tool provided by the embodiment of the application is that when the chip testing tool is actually used, the adapting plate 1 is firstly placed on a proper plane and kept horizontal through the adjusting supporting legs 5. Then, the chip to be tested is aligned to the clamping hole 41 of the test fixture 4, the chip falls into the detection port 2 of the adapter plate 1 through the clamping hole 41, and the chip pins are inserted into the slots 3 on the bottom wall of the detection port 2. At this time, the chip is fixed by the chucking of test fixture 4, and the chip pin forms circuit connection through slot 3 inside wall conducting layer 31 and FPC line interface, and external data acquisition system can begin to test the chip that awaits measuring, and in the test process, heat dissipation channel 6 can be for the chip heat dissipation, guarantees test environment's stability.

The above embodiments are not intended to limit the scope of the application, so that the equivalent changes of the structure, shape and principle of the application are covered by the scope of the application.

Claims

1. The chip testing tool is characterized by comprising an adapter plate (1), wherein the adapter plate (1) is used for installing a chip to be tested, a detection port (2) for placing the chip to be tested is arranged on the adapter plate (1) in a downward sinking mode, and a plurality of slots (3) for inserting pins of the chip are formed in the bottom wall of the detection port (2);

The test fixture (4), the test fixture (4) is installed on the adapting plate (1), the test fixture (4) is used for clamping the chip to be tested on the adapting plate (1), and the test fixture (4) is provided with a clamping hole (41) for the chip to fall into the detection port (2) after being clamped in;

the FPC wire interface (7), the FPC wire interface (7) is installed on the adapter board (1) to enable the pin output end of the chip to be tested to be connected with the connecting end of the FPC wire interface (7) through a circuit after the pin of the chip to be tested is inserted into the slot (3), and the FPC wire interface (7) is externally connected with a data acquisition system.

2. The chip testing fixture as set forth in claim 1, wherein the clamping hole (41) is square, and the four vertex angles of the clamping hole (41) are provided with yielding grooves (42).

3. The chip testing fixture as claimed in claim 2, wherein auxiliary holes (43) communicated with the clamping holes (41) are respectively formed around the testing fixture (4).

4. The chip testing fixture of claim 1, wherein the inner side wall of the slot (3) is provided with a conductive layer (31) with a thickness of 5-10 μm.

5. The chip testing fixture of claim 1, wherein the bottom of the adapting plate (1) is provided with supporting feet (5) with adjustable height, and the adapting plate (1) can be kept horizontal on different planes through the supporting feet (5).

6. The chip testing fixture of claim 5, wherein the supporting legs (5) comprise supporting columns (52) and hemispherical bases (51), one ends of the supporting columns (52) in the length direction are fixedly connected to the bases (51), the other ends of the supporting columns are connected to the adapter plates (1) in a threaded mode, and one sides of hemispherical cambered surfaces of the bases (51) are used for being abutted to a placing plane.

7. The chip testing fixture of claim 1, wherein the adapter plate (1) is provided with a plurality of heat dissipation channels (6), and the heat dissipation channels (6) are communicated with the detection port (2).