CN223168209U - Charge-discharge management circuit of energy storage element - Google Patents
Charge-discharge management circuit of energy storage elementInfo
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- CN223168209U CN223168209U CN202421843000.3U CN202421843000U CN223168209U CN 223168209 U CN223168209 U CN 223168209U CN 202421843000 U CN202421843000 U CN 202421843000U CN 223168209 U CN223168209 U CN 223168209U
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Abstract
本实用新型公开了一种储能元件的充放电管理电路，包括输入端Vin、输出端Vout、直通回路，充电回路、放电控制回路和防反充电路；输入端Vin和电源连接，输出端Vout和负载连接；直通回路包括二极管D1，在供电时，直接从输入端vin给负载供电；充电回路包括二极管D2、限流电阻R1和储能电容C1，电源通过二极管D2和限流电阻R1给储能电容C1充电；储能电容C1通过放电控制回路和防反充电路给负载供电；放电控制回路包括第一开关管Q1和控制输入端口，控制输入端口输入控制信号关断所述第一开关管Q1，以关断所述储能电容C1的输出。该电路实现了带储能电容等储能元件的供电电路快速上电和快速断电功能。
The utility model discloses a charge and discharge management circuit for an energy storage element, comprising an input terminal Vin, an output terminal Vout, a through-circuit, a charging circuit, a discharge control circuit, and an anti-reverse charging circuit. The input terminal Vin is connected to a power source, and the output terminal Vout is connected to a load. The through-circuit includes a diode D1, which directly supplies power to the load from the input terminal Vin when power is supplied. The charging circuit includes a diode D2, a current-limiting resistor R1, and an energy storage capacitor C1, and the power source charges the energy storage capacitor C1 through the diode D2 and the current-limiting resistor R1. The energy storage capacitor C1 supplies power to the load through the discharge control circuit and the anti-reverse charging circuit. The discharge control circuit includes a first switch tube Q1 and a control input port, and a control signal input to the control input port turns off the first switch tube Q1, thereby shutting off the output of the energy storage capacitor C1. This circuit implements fast power-on and power-off functions for a power supply circuit with energy storage elements such as energy storage capacitors.
Description
Technical Field
The present disclosure relates to electronic technology, and particularly to a charge and discharge management circuit for an energy storage element.
Background
In some power supply occasions of electronic circuits, a larger energy storage element (such as a large capacitance element) exists in the power supply circuit, so that the output of the back-end voltage stabilizing chip can rise slowly, or the output of the voltage stabilizing chip can fall slowly after power is off, and under the power supply condition, the MCU at the back end of power supply can be halted and does not run.
In the process, this approach brings the following problems:
1. the power supply rises too slowly, resulting in bad power-on reset of the MCU.
2. The power failure drops too slowly, and due to different working and running voltage ranges of different chips, abnormal circuit states can be caused, and even the MCU is dead or not running.
Disclosure of utility model
In order to solve the above problems in the prior art, the present utility model provides a charge and discharge management circuit for an energy storage element. The technical proposal is as follows:
A charge and discharge management circuit of an energy storage element comprises an input end Vin, an output end Vout, a through loop, a charging loop, a discharge control loop and an anti-reverse charge circuit;
The input end Vin is connected with a power supply, and the output end Vout is connected with a load;
The direct-connection loop comprises a diode D1, wherein the diode D1 is used for directly supplying power to a load from an input end Vin when power is supplied, the anode of the diode D1 is connected with the input end Vin, and the cathode of the diode D1 is connected with the output end Vout;
The charging loop comprises a diode D2, a current limiting resistor R1 and an energy storage capacitor C1, wherein the power supply charges the energy storage capacitor C1 through the diode D2 and the current limiting resistor R1;
The energy storage capacitor C1 supplies power to a load through the discharge control loop and the anti-reverse charging circuit;
The discharging control loop comprises a first switching tube Q1 and a control input port, wherein a control signal is input to the control input port to turn off the first switching tube Q1 so as to turn off the output of the energy storage capacitor C1.
Further, the first switching tube Q1 is a PMOS tube, the source electrode of the PMOS tube is connected with the positive electrode of the energy storage element, and the drain electrode of the PMOS tube is connected with the input end of the anti-reverse charging circuit.
Further, the control end of the first switching tube Q1 is connected with at least one discharging control branch, the discharging control branch comprises a second switching tube, the input end of the second switching tube is connected with the control end of the first switching tube Q1, the output end of the second switching tube is grounded, and the control end of the second switching tube is connected with the control input port.
Further, the second switching tube is an NPN triode or an NMOS tube.
Further, the circuit also comprises a delay circuit, wherein the output end of the delay circuit is connected with the control end of the first switching tube Q1 and is used for realizing the voltage slow-down control of the control end of the first switching tube Q1.
Further, the delay circuit includes a resistor R2 and a capacitor C2, one end of the resistor R2 is connected with the positive electrode of the energy storage capacitor C1, the other end of the resistor R2 is connected with one end of the capacitor C2 and the control end of the first switching tube Q1, and the other end of the capacitor C2 is grounded.
Further, the anti-reverse charging circuit comprises a MOS tube Q2, a switch tube Q3 and a switch tube Q4, wherein the input end of the anti-reverse charging circuit is connected with the drain electrode of the MOS tube Q2 and the emitter electrode of the switch tube Q3, the output end of the anti-reverse charging circuit is connected with the source electrode of the MOS tube Q2 and the emitter electrode of the switch tube Q4, the base electrode of the switch tube Q3 is connected with the collector electrode of the switch tube Q3 and the base electrode of the switch tube Q4, the collector electrode of the switch tube Q3 is grounded through a resistor R5, and the collector electrode of the switch tube Q4 is connected with the gate electrode of the MOS tube Q2 and is grounded through a resistor R6.
Further, the anti-reverse charging circuit comprises a diode D5, and a cathode of the diode D5 is connected with the output terminal Vout.
Further, the charge and discharge management circuit of the energy storage element further comprises a power failure detection circuit, wherein the input end of the power failure detection circuit is connected with the input end Vin, and the output end of the power failure detection circuit is connected with the control input port of the discharge control loop and is used for outputting a high-level signal when detecting that the input voltage is smaller than a set threshold value.
The utility model realizes the following technical effects:
The circuit realizes the functions of quick power-on and quick power-off of the power supply circuit with energy storage elements such as the energy storage capacitor. Therefore, the problems that the power supply rises slowly, the MCU is powered on and reset poorly, the circuit state is abnormal due to the fact that the power failure falls slowly, and even the MCU is halted and cannot operate are solved.
Drawings
FIG. 1 is a system block diagram of a charge and discharge management circuit of an energy storage element of the present utility model;
FIG. 2 is a first embodiment of a charge and discharge management circuit of an energy storage element of the present utility model;
FIG. 3 is a second embodiment of a charge and discharge management circuit of an energy storage element of the present utility model;
FIG. 4 is a third embodiment of a charge and discharge management circuit of an energy storage element of the present utility model;
Fig. 5 is a power down detection circuit example.
Detailed Description
For further illustration of the various embodiments, the utility model is provided with the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments and together with the description, serve to explain the principles of the embodiments. With reference to these matters, one of ordinary skill in the art will understand other possible embodiments and advantages of the present utility model.
The utility model will now be further described with reference to the drawings and detailed description.
As shown in fig. 1, the present utility model provides a charge and discharge management circuit for an energy storage element, which mainly includes a diode D1, a diode D2, a charge current limiting resistor R1, an energy storage capacitor C1, a discharge control circuit 10, and an anti-reverse charge circuit 20. Wherein:
Diode D1 forms a pass-through loop. The diode D1 is connected between the input end Vin and the output end Vout of the charge-discharge circuit of the energy storage capacitor C1, so that the voltage of the output end Vout can be directly obtained by the input end Vin after passing through the diode D1 in the slow rising process of the charge of the energy storage capacitor C1, the voltage of the output end Vout is enabled to rise rapidly, and the problem of bad MCU power-on reset caused by too slow rising of power supply is effectively solved.
The diode D2, the resistor R1 and the energy storage capacitor form a charging loop, and the power supply supplies power to the energy storage capacitor C1 through the diode D2 and the resistor R1. The diode D2 is a reverse connection preventing diode, and prevents the reverse current of the energy storage capacitor C1 from flowing out of the Vin end when the voltage of the Vin drops.
Preferably, the diode D2 is a high-power, low-drop schottky rectifier diode.
The resistor R1 is a charging current-limiting resistor, the resistance value and rated power value of the resistor can be set according to actual circuit requirements, the requirement on instantaneous current output of power supply equipment can be effectively reduced, and better applicability is realized.
The discharge control loop 10 includes a switching device and a control input port. The switching device can be turned off by controlling the input port to input a control signal so as to turn off the output of the energy storage capacitor C1, and the abnormal problem caused by the fact that the power-off of the output end Vout drops too slowly is solved. The control input port can be controlled by the MCU at the rear end, can also be connected to a power failure detection circuit at the input position of the front end Vin, responds to power failure, and meanwhile, controls the energy storage element to close the output, so that the energy saving effect is achieved, and unnecessary energy storage consumption is reduced.
The anti-reverse charging circuit prevents the output end Vout from reversely charging the energy storage capacitor C1.
Example 1:
In the present embodiment, the discharge control circuit is composed of Q1, R2, C2, Q5, Q6, R4, R7, R8, R3, and the like. Wherein, Q5, R4, R7, R3, R8 and Q6 form two parallel discharge branches which are respectively controlled by discharge control signals Ctrl1 and Ctrl 2. The discharge control signals Ctrl1 and Ctrl2 may be provided by the MCU or other protection circuits.
In this embodiment, the Q1 is a PMOS transistor. Because the PMOS tube is provided with the body diode for loop protection, in order to effectively cut off the output of the energy storage capacitor, the source electrode of the PMOS tube is used as an input end and the drain electrode is used as an output end when the PMOS tube is applied.
In this embodiment, a delay circuit is also included. The delay circuit is composed of R2 and C2, can set delay closing time, and provides multi-level power supply voltage protection requirements.
In this embodiment, the delay circuit may also use a chip scheme similar to NE555 for delay triggering, but may increase energy consumption of the energy storage element.
In this embodiment, the anti-reverse charging route is composed of Q2, Q3, Q4, R5, R6. The connection relation is that Q2 is a PMOS tube, Q3 and Q4 are PNP triodes, the output end of a discharge control loop is connected with the drain electrode of Q2 and the emitter electrode of Q3, the output end Vout is connected with the source electrode of Q2 and the emitter electrode of Q4, the base electrodes of Q3 and Q4 are connected and connected with the collector electrode of Q3, the collector electrode of Q3 is grounded through a resistor R5, and the collector electrode of Q4 is connected with the grid electrode of Q2 and grounded through a resistor R6. In the circuit, the reverse charging of the output end Vout to the energy storage element can be avoided by the Q2, and the low-on-resistance PMOS tube is adopted by the Q2, so that smaller voltage drop output can be realized, heat loss is reduced, and efficiency is improved. The functions of Q3 and Q4 are to control the gate voltage of Q2, so as to control the on and off of Q2. The Q3 and Q4 adopt triode, can form a stable voltage difference of 0.7V at the base electrode and the emitter electrode, because the base electrodes of Q3 and Q4 are connected together, when the voltage of the drain electrode of Q2 is higher than the voltage of the source electrode of Q2, the base electrode voltage of Q3 is lower than the emitter electrode of Q3, and then the Q3 is conducted, because the base electrode and the collector electrode of Q3 are connected together and are connected with the base electrode of Q4, the conduction of Q3 leads the voltage clamp of the base electrode (also the base electrode of Q4) of Q3 to be positioned at the voltage of the drain electrode of Q2 minus 0.7V, and because the voltage of the drain electrode of Q2 is higher than the voltage of the source electrode of Q2, the voltage difference of the base electrode and the emitter electrode of Q4 is smaller than 0.7V, and when the voltage of the drain electrode of Q2 is lower than the voltage of the source electrode of Q2, the base electrode of Q4 and the emitter electrode of Q4 are equal to 0.7V, and the voltage difference of Q2 is in the reverse charge state, so that the voltage of the drain electrode of Q2 is in the reverse charge state, and the voltage of the drain electrode of Q2 is in the reverse charge state. In addition, the self-discharge current of the energy storage element circuit can be controlled by selecting proper resistance values of the resistors R5 and R6.
Example 2:
As shown in fig. 3, in the present embodiment, the anti-reverse charge circuit 20 is composed of a diode D5, the anode of D5 is connected to the output terminal of the discharge control circuit, and the cathode of D5 is connected to the output terminal Vout. Preferably, diode D5 is a low drop schottky rectifier diode.
The switching device Q7 in the main loop in the discharge control loop may also be a power transistor, as allowed by the charge loss.
In this embodiment, more discharge branches may be provided to achieve more flexible discharge output control. The switching devices Q8, Q9, Q10 and Q11 of the discharging branch can be triodes or MOS (metal oxide semiconductor) tubes.
Example 3:
As shown in fig. 4, the charge/discharge management circuit of the present energy storage element further includes a power-down detection circuit 30, and the power-down signal generated by the power-down detection circuit 30 is used as a discharge control signal or one of the discharge control signals to turn off the output of the energy storage capacitor C1. As shown in fig. 5, a specific circuit example of a simple power-down detection circuit 30 is given, where Vin is a power supply and Ctrl is a discharge control signal.
The utility model realizes the following technical effects:
The circuit realizes the functions of quick power-on and quick power-off of the power supply circuit with energy storage elements such as the energy storage capacitor. Therefore, the problems that the power supply rises slowly, the MCU is powered on and reset poorly, the circuit state is abnormal due to the fact that the power failure falls slowly, and even the MCU is halted and cannot operate are solved.
While the utility model has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the utility model as defined by the appended claims.
Claims (10)
1. The charge and discharge management circuit of the energy storage element is characterized by comprising an input end Vin, an output end Vout, a through loop, a charging loop, a discharge control loop and an anti-reverse charging circuit;
The input end Vin is connected with a power supply, and the output end Vout is connected with a load;
The direct-connection loop comprises a diode D1, wherein the diode D1 is used for directly supplying power to a load from an input end Vin when power is supplied, the anode of the diode D1 is connected with the input end Vin, and the cathode of the diode D1 is connected with the output end Vout;
The charging loop comprises a diode D2, a current limiting resistor R1 and an energy storage capacitor C1, wherein the power supply charges the energy storage capacitor C1 through the diode D2 and the current limiting resistor R1;
The energy storage capacitor C1 supplies power to a load through the discharge control loop and the anti-reverse charging circuit;
The discharging control loop comprises a first switching tube Q1 and a control input port, wherein a control signal is input to the control input port to turn off the first switching tube Q1 so as to turn off the output of the energy storage capacitor C1.
2. The charge and discharge management circuit of the energy storage element according to claim 1, wherein the first switching tube Q1 is a PMOS tube, a source electrode of the PMOS tube is connected with a positive electrode of the energy storage element, and a drain electrode of the PMOS tube is connected with an input end of the anti-reverse charge circuit.
3. The charge and discharge management circuit of the energy storage element according to claim 1, wherein the control end of the first switching tube Q1 is connected with at least one discharge control branch, the discharge control branch comprises a second switching tube, the input end of the second switching tube is connected with the control end of the first switching tube Q1, the output end of the second switching tube is grounded, and the control end of the second switching tube is connected with the control input port.
4. The charge and discharge management circuit of the energy storage element of claim 3, wherein the second switching tube is an NPN triode or an NMOS tube.
5. The charge and discharge management circuit of the energy storage element of claim 1, further comprising a delay circuit, wherein an output end of the delay circuit is connected with a control end of the first switching tube Q1, and the delay circuit is used for realizing voltage slow drop control of the control end of the first switching tube Q1.
6. The charge and discharge management circuit of the energy storage element according to claim 5, wherein the delay circuit comprises a resistor R2 and a capacitor C2, one end of the resistor R2 is connected with the positive electrode of the energy storage capacitor C1, the other end of the resistor R2 is connected with one end of the capacitor C2 and the control end of the first switching tube Q1, and the other end of the capacitor C2 is grounded.
7. The charge and discharge management circuit of the energy storage element according to claim 1, wherein the anti-reverse charging circuit comprises a MOS tube Q2, a switch tube Q3 and a switch tube Q4, an input end of the anti-reverse charging circuit is connected with a drain electrode of the MOS tube Q2 and an emitter electrode of the switch tube Q3, an output end of the anti-reverse charging circuit is connected with a source electrode of the MOS tube Q2 and an emitter electrode of the switch tube Q4, a base electrode of the switch tube Q3 is connected with a collector electrode of the switch tube Q3 and a base electrode of the switch tube Q4, a collector electrode of the switch tube Q3 is grounded through a resistor R5, and a collector electrode of the switch tube Q4 is connected with a gate electrode of the MOS tube Q2 and grounded through a resistor R6.
8. The charge/discharge management circuit of the energy storage element as set forth in claim 1, wherein said anti-reverse charge circuit comprises a diode D5, and a cathode of said diode D5 is connected to said output terminal Vout.
9. The charge/discharge management circuit of the energy storage element as set forth in claim 1, wherein said diode D2 is a Schottky rectifier diode.
10. The charge/discharge management circuit of the energy storage element as set forth in claim 1, further comprising a power-down detection circuit, wherein an input terminal of the power-down detection circuit is connected to an input terminal Vin, and an output terminal of the power-down detection circuit is connected to a control input port of the discharge control circuit for outputting a high-level signal when detecting that the input voltage is less than a set threshold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202421843000.3U CN223168209U (en) | 2024-08-01 | 2024-08-01 | Charge-discharge management circuit of energy storage element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202421843000.3U CN223168209U (en) | 2024-08-01 | 2024-08-01 | Charge-discharge management circuit of energy storage element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN223168209U true CN223168209U (en) | 2025-07-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202421843000.3U Active CN223168209U (en) | 2024-08-01 | 2024-08-01 | Charge-discharge management circuit of energy storage element |
Country Status (1)
| Country | Link |
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| CN (1) | CN223168209U (en) |
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2024
- 2024-08-01 CN CN202421843000.3U patent/CN223168209U/en active Active
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