CN223052756U - Circuit capable of inhibiting surge voltage and surge current - Google Patents
Circuit capable of inhibiting surge voltage and surge current Download PDFInfo
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- CN223052756U CN223052756U CN202422093474.7U CN202422093474U CN223052756U CN 223052756 U CN223052756 U CN 223052756U CN 202422093474 U CN202422093474 U CN 202422093474U CN 223052756 U CN223052756 U CN 223052756U
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Abstract
本实用新型提供一种能抑制浪涌电压和浪涌电流的电路，其包括：电阻R100，其一端与电源输入端相连，其另一端与电源输出端相连；滤波电容C100，其一端与电源输出端相连，其另一端接地；开关控制电路，其包括MOS管Q100、电阻R101和电阻R102；第一电压采样电路；第二电压采样电路；电压转换电路，其供电输入端与电源输出端相连；主控电路，其供电输入端与电压转换电路的供电输出端相连，其第一输入端与第一电压采样电路的输出端相连，其第二输入端与第二电压采样电路的输出端相连；驱动电路，其输入端与主控电路的第一输出端相连，其输出端与节点A相连。与现有技术相比，本实用新型既能实现抑制输入端的浪涌电流、IC端的浪涌电压，又几乎不影响到原电路设计。
The utility model provides a circuit capable of suppressing surge voltage and surge current, which includes: a resistor R100, one end of which is connected to the power input end, and the other end of which is connected to the power output end; a filter capacitor C100, one end of which is connected to the power output end, and the other end of which is grounded; a switch control circuit, which includes a MOS tube Q100, a resistor R101 and a resistor R102; a first voltage sampling circuit; a second voltage sampling circuit; a voltage conversion circuit, whose power supply input end is connected to the power output end; a main control circuit, whose power supply input end is connected to the power supply output end of the voltage conversion circuit, whose first input end is connected to the output end of the first voltage sampling circuit, and whose second input end is connected to the output end of the second voltage sampling circuit; a drive circuit, whose input end is connected to the first output end of the main control circuit, and whose output end is connected to node A. Compared with the prior art, the utility model can suppress the surge current at the input end and the surge voltage at the IC end, and hardly affects the original circuit design.
Description
[ Field of technology ]
The utility model relates to the technical field of circuit design, in particular to a circuit capable of inhibiting surge voltage and surge current.
[ Background Art ]
The surge current, the surge voltage and the power supply voltage ripple are taken as important parameters of the circuit, contradictory parameters are adopted in the circuit design, and a larger filter capacitor is needed for reducing the power supply voltage ripple to meet the design requirement, so that the corresponding surge current can possibly fail to exceed the specification requirement. Or due to too large an inductance component on the power supply harness, too large a surge voltage caused by the inductance in series in the circuit, there is a risk of breakdown of the IC (INTEGRATED CIRCUIT, i.e., integrated circuit).
Referring to fig. 1, a schematic diagram of a circuit capable of suppressing surge voltage and surge current in the prior art is shown, which employs an inductor L100 to suppress surge current, and a TVS (TRANSIENT VOLTAGE SUPPRESSOR, transient voltage suppression tube) D100 to suppress input terminal surge voltage.
Problems and disadvantages of the prior art solution shown in fig. 1:
① . The inductance L100 is affected by the operating current of the product, and a larger load RL requires a larger current-carrying capacity of the inductance L100. The cost increases with increasing current.
② . The larger the load RL consumes power, the larger the filter capacitance C100 is, and the larger the inductance L100 is required to suppress the larger surge current. The cost increases with the filter capacitance C100.
③ . The inductor L100 with a large current and a large inductance is too large in size, and requires a relatively large space. So that the structural design is limited.
④ . TVS tube D100 can clamp only the input terminal voltage and cannot directly protect the surge voltage at the IC terminal.
Therefore, a new solution is needed to solve the above problems.
[ utility model ]
An object of the present utility model is to provide a circuit capable of suppressing a surge voltage and a surge current, which can suppress a surge current at an input terminal and a surge voltage at an IC terminal, and hardly affects an original circuit design.
According to one aspect of the present utility model, there is provided a circuit capable of suppressing surge voltage and surge current, comprising a resistor R100 having one end connected to a power input terminal Vin and the other end connected to a power output terminal Vout; one end of the filter capacitor C100 is connected with the power supply output end Vout, and the other end of the filter capacitor C100 is grounded; the switch control circuit comprises a MOS tube Q100, a resistor R101 and a resistor R102, wherein a first connecting end of the MOS tube Q100 is connected with the power input end Vin, and a second connecting end of the MOS tube Q100 is connected with the power output end Vout; the MOS transistor comprises a MOS transistor Q100, a resistor R101, a voltage conversion circuit, a main control circuit, a voltage conversion circuit and a voltage conversion circuit, wherein one end of the resistor R101 is connected with a power input end Vin, the other end of the resistor R102 is connected with a control end of the MOS transistor Q100, one end of the resistor R102 is connected with the control end of the MOS transistor Q100, the other end of the resistor R is connected with a node A, the input end of the resistor R is connected with the power input end Vin, the output end of the resistor R is used for outputting a first sampling voltage ADC_vin, the first sampling voltage ADC_vin is generated by the voltage sampling circuit based on the voltage of the power input end Vin, the input end of the first sampling voltage ADC_vin is connected with the power output end Vout, the first sampling voltage ADC_Vout is connected with the power input end VCC 1 of the voltage conversion circuit, the first sampling voltage ADC_Vout is output by the output end VCC 1 of the voltage conversion circuit, the first sampling circuit is connected with the first output end VCC sampling circuit, the second sampling voltage is output by the first sampling circuit is connected with the first output end VCC sampling circuit, the input end D of the control circuit is connected with the first output end of the main control circuit, and the output end of the control circuit is connected with the node A.
Compared with the prior art, the utility model can realize the purposes of instantaneously restraining the surge current at the input end of the circuit and the surge voltage at the IC end when power is on, and can switch back to the original circuit design state after the IC is awakened and the MCU starts to work normally, so that the original circuit design is hardly affected. In addition, whether the working current of the load exceeds the upper limit value can be monitored, and the power supply end series resistor is correspondingly set to be opened to limit the surge current.
[ Description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a schematic diagram of a prior art circuit capable of suppressing surge voltage and surge current;
fig. 2 is a schematic diagram of a circuit capable of suppressing surge voltage and surge current in one embodiment of the utility model.
[ Detailed description ] of the invention
In order that the above-recited objects, features and advantages of the present utility model will become more readily apparent, a more particular description of the utility model will be rendered by reference to the appended drawings and appended detailed description.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the utility model. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless specifically stated otherwise, the terms coupled, connected, or connected, as used herein, mean either direct or indirect connection, such as a and B, and include both direct electrical connection of a and B, and connection of a to B through electrical components or circuitry.
In the description of the present utility model, it should be understood that the terms "upper", "lower", "front", "rear", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present utility model.
Referring to fig. 2, a schematic diagram of a circuit capable of suppressing surge voltage and surge current according to an embodiment of the utility model is shown. The circuit capable of suppressing surge voltage and surge current shown in fig. 2 includes a resistor R100, a filter capacitor C100, a switch control circuit 210, a first voltage sampling circuit 220, a second voltage sampling circuit 230, a voltage conversion circuit U1, a main control circuit U2, and a driving circuit 240. In the embodiment shown in fig. 2, the master circuit U2 is an MCU (Microcontroller Unit, i.e., a micro control unit), and the voltage conversion circuit U1 is an IC (INTEGRATED CIRCUIT, i.e., an integrated circuit).
One end of the resistor R100 is connected with the power input end Vin, and the other end of the resistor R is connected with the power output end Vout; one end of the filter capacitor C100 is connected with the power supply output end Vout, and the other end of the filter capacitor C is grounded; the switch control circuit 210 includes a MOS transistor (metal oxide semiconductor, field effect transistor for short) Q100, a resistor R101, and a resistor R102, where a first connection end of the MOS transistor Q100 is connected to the power input end Vin, and a second connection end of the MOS transistor Q100 is connected to the power output end Vout; one end of the resistor R101 is connected with a power input end Vin, the other end of the resistor R102 is connected with a control end of the MOS tube Q100, one end of the resistor R102 is connected with the control end of the MOS tube Q100, the other end of the resistor R is connected with a node A, the input end of the first voltage sampling circuit 220 is connected with the power input end Vin, the output end of the first voltage sampling circuit 220 outputs a first sampling voltage ADC_vin which is generated based on the voltage of the power input end Vin, the input end of the second voltage sampling circuit 230 is connected with a power output end Vout, the output end of the second voltage sampling circuit 230 outputs a second sampling voltage ADC_Vout which is generated based on the voltage of the power output end Vout, the power input end of the voltage conversion circuit U1 is connected with the power output end Vout through the power output end Vout1, the conversion voltage is generated by the voltage conversion circuit U1 which is subjected to voltage conversion based on the voltage of the power output end Vout, the power input end VCC of the main control circuit U2 is connected with the power output end of the first voltage sampling circuit 230, the power input end VCC of the first voltage sampling circuit 220 is connected with the first output end of the main control circuit U2, the power input end of the first voltage sampling circuit is connected with the power output end of the first voltage of the main control circuit 230 is connected with the power output end of the first voltage sampling circuit 240 of the first voltage sampling circuit 230, the output end of the power supply is connected with the node A.
At system power-on instant (or at power-on instant of power input Vin), voltage conversion circuit U1 is in sleep state, main control circuit U2 does not work, first output terminal I/O1 of main control circuit U2 outputs invalid drive signal, drive circuit 240 controls MOS pipe Q100 to turn off (or cut off) based on the invalid drive signal, after system power-on instant (or after power-on instant of power input Vin), voltage conversion circuit U1 is awakened, voltage conversion circuit U1 supplies power to main control circuit U2 through its power supply output terminal Vout1, main control circuit U2 works, if main control circuit U2 detects that voltage/current of power input terminal Vin has stabilized based on first sampling voltage ADC_vin and second sampling voltage ADC_Vout, first output terminal I/O1 of main control circuit U2 outputs valid drive signal, drive circuit 240 controls MOS pipe Q100 to turn on based on the valid drive signal. In this way, when the power supply (or the power input end Vin) is powered on instantaneously, the control MOS tube Q100 is turned off, the surge current is reduced by connecting the resistor R100 in series between the power input end Vin and the power output end Vout, and the surge voltage of the power supply input end VCC of the voltage conversion circuit U1 is restrained through the action of voltage division, after the voltage/current of the power input end Vin is stabilized, the control MOS tube Q100 is turned on, the series resistor R100 is short-circuited, and the original circuit design state is restored, so that the surge current of the power input end Vin and the surge voltage of the power supply input end VCC of the voltage conversion circuit U1 are restrained, and the original circuit design is hardly influenced.
The driving circuit 240 includes a resistor R103, a resistor R104, and a transistor Q101. One end of the resistor R103 is connected to the input end D (or node D) of the driving circuit 240, the other end thereof is connected to the node E, one end of the resistor R104 is connected to the node E, the other end thereof is grounded, the first connection end of the transistor Q101 is connected to the node a, the second connection end thereof is grounded, and the control end thereof is connected to the node E.
The first voltage sampling circuit 220 includes a resistor R105 and a resistor R106, wherein one end of the resistor R105 is connected to the power input terminal Vin, the other end is connected to the node B, one end of the resistor R106 is connected to the node B, the other end is grounded, the node B is an output terminal of the first voltage sampling circuit 220, and the voltage of the node B is the first sampling voltage adc_vin.
The second voltage sampling circuit 230 includes a resistor R107 and a resistor R108, where one end of the resistor R107 is connected to the power output terminal Vout, and the other end of the resistor R107 is connected to the node C, one end of the resistor R108 is connected to the node C, and the other end of the resistor R is grounded, the node C is an output terminal of the second voltage sampling circuit 230, and the voltage of the node C is the second sampling voltage adc_vout.
In the embodiment shown in fig. 2, the driving circuit 240 further includes a capacitor C101, one end of the capacitor C101 is connected to the node E, and the other end of the capacitor C101 is grounded, the switch control circuit 210 further includes a capacitor C102, one end of the capacitor C102 is connected to the power input terminal Vin, and the other end of the capacitor C102 is connected to the control terminal of the MOS transistor Q100. The capacitor C101 and the capacitor C102 are unnecessary components, the capacitor C101 has the function that the triode Q101 is switched from an off (or off) state to a saturated (or on) state to be smoother, and the capacitor C102 has the function that the field effect transistor Q100 is switched from the off (or off) state to the saturated (or on) state to be smoother.
In the embodiment shown in fig. 2, the MOS transistor Q100 is a PMOS transistor, and the first connection end, the second connection end, and the control end of the MOS transistor Q100 are respectively a source, a drain, and a gate of the PMOS transistor;
The triode Q101 is an NPN triode, and the first connecting end, the second connecting end and the control end of the triode Q101 are respectively a collector electrode, an emitter electrode and a base electrode of the NPN triode.
The circuit capable of suppressing surge voltage and surge current shown in fig. 2 further includes a load RL, a power supply terminal of the load RL is connected to the power supply output terminal Vout, and an enable terminal EN of the load RL is connected to the second output terminal I/O2 of the master control circuit U2. At the system power-on instant (or at the power input end Vin), the second output end I/O2 of the main control circuit U2 outputs an invalid enabling signal disable to Enable the load RL to be not operated, and after the system power-on instant, if the second output end I/O2 of the main control circuit U2 outputs an valid enabling signal Enable, the load RL is enabled to be operated.
In the circuit capable of suppressing surge voltage and surge current shown in fig. 2, the voltage conversion circuit U1 includes signal ports (e.g., can_h interface and can_l interface) for receiving a wake-up signal, and when the wake-up signal is not received, the voltage conversion circuit U1 is in a sleep state, and when the wake-up signal is received, the voltage conversion circuit U1 is awakened.
In the specific embodiment shown in fig. 2, the signal port of the voltage conversion circuit U1 includes a can_h interface and a can_l interface, which are connected to the can_h interface and the can_l interface in the connector J1 through a can_h line and a can_l line, respectively. In addition, the VCC interface in the connector J1 is connected to the power supply input terminal Vin, and the GND interface in the connector J1 is grounded.
In the field of electrical control, CAN is an abbreviation for controller area network (Controller Area Network). It is a bus technology used in automotive control systems to transfer data and information. And "L" and "H" are used to distinguish two different CAN lines, where "L" represents a low level and "H" represents a high level. These two wires play an important role in the automotive control system, and specific use cases can be seen in the prior art, and are not described here again.
In the circuit capable of suppressing surge voltage and surge current shown in fig. 2, the voltage conversion circuit U1 is provided with communication ports (e.g., rx interface and Tx interface), the main control circuit U2 is provided with communication ports (e.g., rx interface and Tx interface), and the communication ports of the voltage conversion circuit U1 are communicatively connected with the communication ports of the main control circuit U2. When the voltage conversion circuit U1 does not transmit a driving instruction to the main control circuit U2 through the communication ports (e.g., the Rx interface and the Tx interface), the second output terminal I/O2 of the main control circuit U2 outputs an disable Enable signal disable to disable the load RL, and when the voltage conversion circuit U1 transmits a driving instruction to the main control circuit U2 through the communication ports (e.g., the Rx interface and the Tx interface), the second output terminal I/O2 of the main control circuit U2 outputs an Enable signal Enable to Enable the load RL.
In the specific embodiment shown in fig. 2, the communication port of the voltage conversion circuit U1 includes an Rx (receive) interface and a Tx (transmit) interface, and the communication port of the master circuit U2 includes an Rx (receive) interface and a Tx (transmit) interface, where the Rx interface of the voltage conversion circuit U1 is connected to the Tx interface of the master circuit U2, and the Tx interface of the voltage conversion circuit U1 is connected to the Rx interface of the master circuit U2. The specific use of Tx and Rx communications is referred to in the prior art and will not be described in detail herein.
The operation of the circuit shown in fig. 2 for suppressing surge voltage and surge current will be described in detail.
1. At system power-up instant (or at power input Vin):
The enable end EN of the load RL is designed to default to an enabled state (i.e. the second output end I/O2 of the master circuit U2 outputs an Disabled enable signal Disabled), so that the load RL does not work. The voltage conversion circuit U1 is an IC (i.e., an integrated circuit) with a sleep function, which does not receive a wake-up signal through can_ H, CAN _l or before the IC is not initialized, the power supply output terminal Vout1 of the voltage conversion circuit U1 has no output voltage (about 0V), so the first output terminal I/O1 of the master circuit U2 outputs 0V (i.e., the inactive driving signal is at a low level), vbe (Vbe refers to a voltage difference between the base and the emitter of the triode) of the triode Q101 is about 0V, a conduction voltage drop (e.g., an on voltage drop is 0.7V) of less than Vbe, the triode Q101 is in an off (or off state), ic_q101 (IC is a collector current of the triode) is about 0A, the currents of the resistor R101 and the resistor R102 are about 0A, the operating voltage of the resistor R101 is about 0V, that is, the Vgs voltage of the fet Q100 (i.e., the gate source voltage of the fet) is about 0V, and Vgs of the fet Q100 is currently smaller than Vgs (i.e., the on voltage of the fet is in the off state).
The circuit load resistance at power-on instant is about R100+ESR_C100, and the transient surge current is:
I_inrush≈Vin÷(R100+ESR_C100)
ESR is Equivalent SERIES RESISTANCE, the Equivalent series resistance.
Meanwhile, due to the capacitor C100, the operating voltage of the power-on transient IC (i.e., the voltage conversion circuit U1) is about:
Vout≈Vin*(ESR_C100/(ESR_C100+R100))
The larger the resistor R100 is, the smaller the corresponding surge current is.
Due to the capacitor C100, the operating voltage of the power-on instant U1 IC (i.e., the operating voltage of the power supply input VCC of the voltage conversion circuit U1) is approximately:
Vout is equal to Vin (esr_c100/(esr_c100+r100)), the larger R100 is, the smaller the surge voltage at the U1 IC terminal is.
That is, since the surge voltage at the IC terminal (i.e., the power supply input terminal VCC of the voltage conversion circuit U1) is not directly supplied from the power supply input terminal Vin, the surge voltage at the IC terminal is smaller as the resistor R100 is larger due to the series voltage division between the esr_c100 and the resistor R100. Since the voltage conversion circuit U1 is in a sleep state at the system power-on instant (or at the power input terminal Vin), the voltage conversion circuit U1 does not send a driving command to the main control circuit U2 through the communication connection, so that the second output terminal I/O2 of the main control circuit U2 outputs an disable enable signal disable (or the enable terminal EN is designed to default to the disable state at this time), and therefore, the load RL does not operate.
That is, at the system power-on instant (or at the power input Vin), the voltage conversion circuit U1 is in a sleep state, the main control circuit U2 does not operate, and the first output I/O1 of the main control circuit U2 outputs an inactive driving signal, which turns off the transistor Q101 in the driving circuit 240, so as to control the voltage of the node a to turn off the MOS transistor Q100.
2. After the system power-up instant (or after the power-up instant at the power input Vin):
After the voltage conversion circuit U1 is initialized and receives the wake-up signal through the can_ H, CAN _l, the power supply output terminal Vout1 of the voltage conversion circuit U1 supplies power to the output voltage, the main control circuit U2 starts to work after obtaining the power supply output terminal Vout1 of the voltage conversion circuit U1 to supply power, and the main control circuit U2 detects whether the power supply voltage/current of the power supply input terminal Vin is stable through the first sampling voltage adc_vin and the second sampling voltage adc_vout. If the main control circuit U2 detects that the supply voltage/current of the power input terminal Vin is stable based on the first sampling voltage adc_vin and the second sampling voltage adc_vout (for example, the first sampling voltage adc_vin and the second sampling voltage adc_vout are substantially equal), the first output terminal I/O1 of the main control circuit U2 outputs a high level (which is an effective driving signal), vbe of the transistor Q101 is about 0.7V through the resistors R103 and R104, the transistor Q101 is in a saturated (or conducting) state, vce_q101 (Vce is a voltage difference between the collector and the emitter of the transistor) is less than 0.3V, that is, vgs voltage of the field effect transistor Q100 is about- (Vin-0.3V) (R101/(r101+r102)), and Vgs of the field effect transistor Q100 is designed to be greater than Vgs (th) (that is, the on voltage), the field effect transistor Q100 is in a saturated (or conducting) state, the power input terminal Vin is shorted in series with the resistor R100, and the original circuit design state is restored. The series resistance R100 is about 10mΩ of the DC on-resistance of the FET Q100, and hardly affects the original circuit design.
That is, after the power input terminal Vin is powered on instantaneously, the voltage conversion circuit U1 is woken up, the main control circuit U2 works, and if the main control circuit U2 detects that the power supply voltage/current of the power input terminal Vin is stable based on the first sampling voltage adc_vin and the second sampling voltage adc_vout, the first output terminal I/O1 of the main control circuit U2 outputs an effective driving signal, and the effective driving signal makes the transistor Q101 in the driving circuit 240 conductive, so that the voltage of the control node a makes the MOS transistor Q100 conductive.
3. After detecting that the supply voltage/current of the power supply input terminal Vin is stable, the Enable terminal EN of the load RL is allowed to switch from the Disabled state to the enabled state.
Specifically, after detecting that the supply voltage/current of the power input terminal Vin is stable, when the voltage conversion circuit U1 does not transmit a driving instruction to the main control circuit U2 through the communication ports (e.g., the Rx interface and the Tx interface), the second output terminal I/O2 of the main control circuit U2 outputs an disable Enable signal disable to disable the load RL, and when the voltage conversion circuit U1 transmits a driving instruction to the main control circuit U2 through the communication ports (e.g., the Rx interface and the Tx interface), the second output terminal I/O2 of the main control circuit U2 outputs an Enable signal Enable to Enable the load RL.
4. When the load RL operates instantaneously or in the process that surge current exists, whether the working current of the load RL exceeds the upper limit current is judged by capturing the difference value of the first sampling voltage ADC_vin and the second sampling voltage ADC_Vout, if the working current of the load RL exceeds the upper limit current, the I/O1 can be set to be low level, so that the field effect transistor Q100 is in a cut-off (or cut-off) state, and the resistor R100 is connected in series to the circuit to inhibit the surge current. After the circuit is stable, the switching setting I/O1 is set to be high level, so that the field effect transistor Q100 is in a saturated (or passing) state, and the circuit is restored to the original circuit state. The surge current influence caused by the load RL is effectively restrained.
That is, when the load RL is running instantaneously or there is an inrush current during the operation of the load RL, if the master control circuit U2 detects that the working current of the load RL exceeds the upper limit current based on the first sampling voltage adc_vin and the second sampling voltage adc_vout, the first output terminal I/O1 of the master control circuit U2 outputs an inactive driving signal (e.g., a low level), the driving circuit 240 controls the MOS transistor Q100 to be turned off based on the inactive driving signal, and if the master control circuit U2 detects that the working current of the load RL does not exceed the upper limit current based on the first sampling voltage adc_vin and the second sampling voltage adc_vout, the first output terminal I/O1 of the master control circuit U2 outputs an active driving signal (e.g., a high level), and the driving circuit 240 controls the MOS transistor Q100 to be turned on based on the active driving signal.
What needs to be specifically stated is:
1. Resistor R100 may be a parallel connection of a plurality of resistors;
2. The field effect tube Q100 can be in other driving modes or other types of MOS tubes, and has the core that the resistor R100 can be short-circuited, meanwhile, the direct current resistor R100 can be conducted by using the field effect tube Q100, and whether the working current of the load RL exceeds the upper limit value can be calculated by dividing the difference between two ends of the saturated state of the field effect tube Q100 by the direct current resistor R100 conducted by the first voltage sampling circuit 220 and the second voltage sampling circuit 230;
3. The main control circuit U2 may be any other IC with a sleep function, the power supply output terminal Vout1 is the power supply corresponding to the sleep wake-up, and the sleep wake-up signal may be other level signals.
4. Before the load RL is not started, the operating current of the IC (i.e. the master circuit U2) is only about several tens of mA, and the voltage drop caused by the power resistor R100 does not affect the normal operation of the IC.
In summary, in the circuit capable of suppressing surge voltage and surge current provided by the utility model, the resistor R100 is connected in series between the power input terminal Vin and the power output terminal Vout, and the MOS transistor Q100 is connected in parallel to the resistor R100. In this way, when the power supply (or the power supply input end Vin) is powered on instantaneously, the MOS transistor Q100 is controlled to be turned off, the surge current is reduced by connecting the resistor R100 in series between the power supply input end Vin and the power supply output end Vout, the surge voltage of the power supply input end VCC of the voltage conversion circuit U1 is restrained by the action of resistor voltage division, the IC with the dormancy wakeup function (namely the voltage conversion circuit U1) can output the power supply output voltage Vout1 after being awakened, so that the MCU (namely the main control circuit U2) starts working, and after the voltage difference between the two ends of the series resistor R100 of the power supply input end Vin is compared through the first sampling voltage ADC_vin and the second sampling voltage ADC_Vout, the voltage/current of the power supply input end Vin is judged to be stable, the field effect transistor Q100 is driven to be conducted, the power supply end series resistor R100 is short-circuited, and the original circuit design state is restored. Therefore, the surge current of the power input end Vin and the surge voltage of the IC end are restrained, the series resistor R100 of the power end can be connected in series after the IC dormancy awakens, the original circuit design is restored, and the original circuit design is hardly affected. In addition, the utility model can also monitor whether the working current of the load RL exceeds the upper limit value, and correspondingly set the power end series resistor R100 to be opened to limit the surge current.
It should be noted that any modifications to the specific embodiments of the utility model may be made by those skilled in the art without departing from the scope of the utility model as defined in the appended claims. Accordingly, the scope of the claims of the present utility model is not limited to the foregoing detailed description.
Claims (11)
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| CN202422093474.7U CN223052756U (en) | 2024-08-27 | 2024-08-27 | Circuit capable of inhibiting surge voltage and surge current |
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| CN202422093474.7U CN223052756U (en) | 2024-08-27 | 2024-08-27 | Circuit capable of inhibiting surge voltage and surge current |
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