CN222637282U

CN222637282U - Chip packaging structure and electronic equipment

Info

Publication number: CN222637282U
Application number: CN202420465596.1U
Authority: CN
Inventors: 豆全亮; 崔波; 高阳
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2024-03-07
Filing date: 2024-03-07
Publication date: 2025-03-18
Anticipated expiration: 2034-03-07

Abstract

The application provides a chip packaging structure and an electronic device, the chip packaging structure comprises at least one chip, a carrier plate, a heat conduction insulating layer and a packaging shell. The bottom surface of the chip is arranged on the carrier plate, and the heat conduction insulating layer and the chip are packaged in the packaging shell. The packaging shell comprises a heat dissipation part and a plastic packaging part, wherein the heat dissipation part and the plastic packaging part are sequentially stacked in a first direction, at least part of the top surface of the chip, the heat conduction insulating layer and the heat dissipation part are sequentially contacted, the surface of the heat dissipation part, which is away from at least one chip in the first direction, is exposed relative to the outer surface of the plastic packaging part, the first direction is parallel to the thickness direction of the chip packaging structure, and the top surface and the bottom surface of the chip are oppositely arranged in the first direction. The application can improve the heat radiation capability of the chip packaging structure and is beneficial to the stable operation of the chip.

Description

Chip packaging structure and electronic equipment

Technical Field

The present application relates to the field of electrical components, and in particular, to a chip package structure and an electronic device.

Background

The chip packaging is to package the chip in the packaging shell and lead out the electrode of the chip outside the packaging shell so as to electrically connect the packaged chip packaging structure with other structures. On the one hand, through encapsulating the chip in the encapsulation casing, can provide a stable operational environment for the chip, prevent that external steam, dust etc. from contacting the chip circuit to corrode and interfere it, cause electrical property to descend, and then interfere the work of chip even electronic equipment. On the other hand, after the chips are packaged, the packaged chips can be used as a stable whole, so that the chips are convenient for batch transportation and modularized installation.

A typical chip package structure includes a chip, a carrier, and a package housing. The bottom surface of the chip is mounted on the carrier plate through curing of a curing material (such as glue), and the chip and the carrier plate are packaged in a plastic package shell formed by curing of a plastic package material, so that a chip package structure is formed. The plastic package shell formed after the plastic package material is solidified can be used as the whole package shell of the chip package structure.

However, as the performance of the current chip becomes stronger, the power consumption of the chip is also increased, and the temperature of the chip is increased due to the increasing heating value. The high temperature can cause the electronic increase of the components in the chip, the transmission speed of the circuit signal is reduced, the working speed and the calculation efficiency of the chip are reduced, and the performance of the chip is influenced. Meanwhile, the high temperature has a great influence on the service life of the chip and the carrier plate. The chip packaging structure exposes the problem of poor heat dissipation performance in the face of chips with larger and larger thermal power.

Firstly, the heat dissipation effect of the chip packaging structure is poor, and when the heat dissipation is carried out, the chip packaging structure mainly carries out heat exchange with the outside air through a plastic package shell formed by solidifying plastic package materials, so that the heat dissipation process is completed. However, because the thermal resistance of the plastic packaging material is larger, the heat exchange efficiency between the chip packaging structure and the air is lower, so that the chip packaging structure cannot radiate heat well, and further the chip inside the chip packaging structure cannot radiate heat in time, so that the temperature of the chip packaging structure is too high.

And secondly, the heat conduction effect inside the chip packaging structure is poor. On the one hand, the heat generated by the chip is difficult to transfer to the outer surface of the plastic package shell, so that the temperature difference between the chip and the outer surface of the plastic package shell is large, and the chip is difficult to dissipate heat. On the other hand, in order to balance the power consumption and the performance, the chip in the electronic device at present partially adopts a large core (namely a large chip and a small chip) framework, and in a high-load scene, the large core with high power consumption is responsible for main work, at the moment, the large core has higher temperature, the small core has lower power and lower temperature, a larger temperature difference occurs between the large core and the small core, and the gap between the chips is filled with the cured plastic packaging material, so that the heat conduction effect is poor, and the heat accumulation of the large core is more serious and cannot be dissipated. And a large temperature difference occurs between the large core and the small core, which can greatly influence the service life and the service performance of the chip.

From the above, the existing chip packaging structure has poor heat dissipation performance, which is not beneficial to the stable operation of the chip.

Disclosure of utility model

The embodiment of the application provides a chip packaging structure and electronic equipment, which solve the problems that the chip packaging structure in the prior art is poor in heat dissipation performance and is not beneficial to stable operation of chips.

The embodiment of the application provides a chip packaging structure which comprises at least one chip, a carrier plate, a heat conduction insulating layer and a packaging shell. The bottom surface of at least one chip is installed in the carrier plate, and heat conduction insulating layer and at least one chip are packaged in the encapsulation casing.

The packaging shell comprises a heat dissipation part and a plastic packaging part, wherein in a first direction, a carrier plate, at least one chip, a heat conduction insulating layer and the heat dissipation part are sequentially stacked, at least part of the top surface of the at least one chip, the heat conduction insulating layer and the heat dissipation part are sequentially contacted, the surface of the heat dissipation part, which is away from the at least one chip, is exposed relative to the outer surface of the plastic packaging part in the first direction, the first direction is parallel to the thickness direction of the chip packaging structure, and the top surface and the bottom surface of the at least one chip are oppositely arranged in the first direction.

The chip is used as a heating device, the generated heat is transferred to the heat dissipation piece through the heat conduction insulating layer, and the heat dissipation piece with better heat dissipation capacity exchanges heat with air, and the whole heat dissipation process is completed.

Compared with the mode that after the chip in the full plastic package structure generates heat, the heat is conducted to the outer surface of the plastic package shell and is radiated by heat exchange between the plastic package shell and air, the radiating mode of the chip package structure provided by the embodiment of the application is obviously higher in efficiency. This makes the temperature lower in the case where the chip heating values are the same, and the heating value that can be tolerated in the case where the chip temperatures are the same is larger. The chip with stronger performance and higher power consumption is favorably adapted, the stable operation of the chip is better ensured, and the performance of the chip is released.

Meanwhile, the chip is still packaged in the packaging shell formed by the heat dissipation piece and the plastic package piece, so that the stability and the safety of the chip can be ensured while the heat dissipation performance of the chip is enhanced.

In summary, the chip packaging structure provided by the embodiment of the application has better heat dissipation performance, and is beneficial to the stable operation of chips.

In some embodiments, the heat spreader includes a first heat sink having at least a portion of a top surface of the at least one chip, the thermally conductive and insulating layer, and the heat spreader in contact in sequence in a first direction, the surface of the first heat sink facing away from the at least one chip being exposed relative to an outer surface of the molding. By arranging the heat sink to comprise the first heat sink, on the one hand the packaging difficulty of the chip is reduced, and on the other hand the cost of the heat sink is relatively low, which is beneficial for cost control of the whole chip packaging structure.

In some embodiments, the heat dissipation piece further comprises a plurality of second heat dissipation fins, each of the plurality of second heat dissipation fins is of a ladder structure and comprises a first portion and a second portion, one end of the first portion is connected with the outer edge of the first heat dissipation fin, the other end of the first portion is connected with one end of the second portion, the first portion is packaged in the plastic package piece, and the surface, away from the heat conducting insulating layer, of the second portion forms at least part of the outer side face of the package shell. On the one hand, through being provided with the second fin, part in each side of chip packaging structure also is used as the cooling surface to dispel the heat, has further promoted the heat dispersion of heat dissipation piece. On the other hand, by arranging the second heat sink in a stepped structure, the outer peripheral edge portion of the top of the chip package structure is still filled with the plastic package, thereby ensuring the impact resistance of the chip package structure.

In some embodiments, the plurality of second heat sinks are sequentially connected on a plane perpendicular to the first direction to form an annular frame structure. It can be understood that the parts of the sides of the chip packaging structure are all provided with radiating surfaces, so that the radiating area of the chip packaging structure is further increased, and the radiating capacity of the chip packaging structure is improved.

In some embodiments, the heat dissipation element further includes a plurality of connection pins arranged at intervals on a plane perpendicular to the first direction, one end of each connection pin in the plurality of connection pins is connected with the first heat dissipation plate and is relatively fixed, and each connection pin extends along the first direction. The outer periphery of the carrier plate is provided with a plurality of protruding parts protruding outwards and corresponding to the plurality of connecting pins, each protruding part of the plurality of protruding parts is provided with a clamping hole, and the other end of each connecting pin of the plurality of connecting pins is clamped in the clamping hole on the corresponding protruding part so as to fixedly connect the heat dissipation piece with the carrier plate.

The heat sink is provided with a plurality of connecting pins, the outer edge of the carrier plate is provided with a plurality of protruding parts, and the protruding parts are provided with a plurality of clamping holes which are in one-to-one correspondence with the connecting pins. When the radiator is installed, the installation can be completed only by clamping each connecting pin of the radiator with the corresponding clamping hole. The design can guarantee on the one hand that the installation is comparatively simple, on the other hand, can guarantee to connect comparatively stably, improves the holistic life of chip packaging structure.

In some embodiments, the connecting pin has an elastic clamping section, the elastic clamping section is provided as a hollow elastic structure, and the elastic structure penetrates through the clamping hole and is elastically abutted with the hole wall of the clamping hole. Through being provided with elasticity joint section, can effectively reduce the circumstances that the cooperation structure cooperation that leads to because the machining tolerance is not accurate enough in the course of working, when being convenient for assemble, provide connection reliability.

In some embodiments, when the heat dissipation element further includes a plurality of second heat dissipation fins, each of the second heat dissipation fins has a step structure and includes a first portion and a second portion, one end of each of the plurality of connection pins is connected to and relatively fixed to the other end of the second portion, so that one end of each of the plurality of connection pins is connected to the first heat dissipation fin through the corresponding second heat dissipation fin. The connecting pins are connected with the first radiating fins through the second radiating fins, so that the length angles required by the connecting pins are formed, and the structure of the radiating piece is simplified.

In some embodiments, the projection of the first heat sink completely covers the projection of the at least one chip on a plane perpendicular to the first direction. Thereby further increasing the surface area of the first radiating fin and enhancing the radiating effect of the first radiating fin.

In some embodiments, the material of the thermally conductive insulating layer is a curable thermally conductive insulating material.

In some embodiments, the heat sink is connected to the thermally conductive insulating layer by curing. During processing, the heat dissipation part is only required to be placed on the heat conduction insulating layer, and the heat dissipation part can be fixed through solidification of the heat conduction insulating layer, so that the processing is simple, the required working hours are short, and the cost is low.

In some embodiments, the thermally conductive insulating layer covers the entire top surface of the at least one chip. The top surface of the chip can be guaranteed to be in contact with the heat conducting insulating layer integrally, so that the chip can be used for radiating heat uniformly as a whole, and the situation that part of the chip is free from path radiation because the part of the chip is not in contact with the heat conducting insulating layer is avoided.

In some embodiments, the thermally conductive insulating layer also covers at least one side of the at least one chip. Through increasing the area of contact of chip and heat conduction insulating layer, further promote the efficiency of chip and heat conduction insulating layer heat exchange.

In some embodiments, the thermally conductive insulating layer also covers all sides of the at least one chip. Thereby the contact area of the chip and the heat conduction insulating layer is increased to the greatest extent.

In some embodiments, the at least one chip is a plurality of chips arranged at intervals on a plane perpendicular to the first direction, and the heat conductive insulating layer is further filled in a gap between any two adjacent chips in the plurality of chips and contacts two opposite sides of any two adjacent chips. Therefore, under the multi-chip scene, the large core (i.e. the large chip) with larger heating value can transfer part of heat to the small core (i.e. the small chip) with smaller heating value, so that the temperatures of the chips tend to be consistent on one hand, and the chip damage caused by overlarge temperature difference is avoided. On the other hand, the temperature of the large core can be lower, and local overheating caused by heat cannot be transmitted can be avoided.

In some embodiments, the top surface of the at least one chip has at least one first electrical connector, the chip package structure further includes at least one second electrical connector disposed corresponding to the at least one first electrical connector, the at least one second electrical connector is located on a lower surface of the molding compound and/or the thermally conductive insulating layer, and the at least one second electrical connector is exposed with respect to an outer surface of the molding compound, and each of the at least one first electrical connector is electrically connected to the corresponding second electrical connector through a lead. Therefore, the chip is electrically connected with the second electric connecting piece, and the second electric connecting piece is used as an external interface, so that the chip packaging structure is electrically connected with other parts of the electronic equipment conveniently. The usability and versatility of the chip package structure as a module are enhanced.

In some embodiments, the heat dissipation element is an integral structure, and the heat dissipation element is made of metal. At least a portion of the carrier plate is configured as a thermally conductive structure having a surface facing away from the at least one die exposed with respect to an outer surface of the molding compound. Through setting up the radiating piece as an organic whole structure, can simplify part quantity, reduce processing step, be favorable to reduce cost. And the radiating piece is made of metal, so that the radiating piece is easy to process and has a good radiating effect. At least part of the carrier plate is set to be a heat conducting structure, and at least part of the surface of the carrier plate far away from the chip is used as a radiating surface, so that heat generated by the chip can be radiated through the carrier plate, and the radiating capacity of the chip packaging structure is improved to the greatest extent.

The application also provides electronic equipment, which comprises the chip packaging structure in any embodiment. The electronic equipment is enabled to run more stably and have better performance.

Drawings

FIG. 1a is a schematic top view of a chip package structure;

FIG. 1b is a schematic cross-sectional view taken along the direction A-A in FIG. 1 a;

FIG. 1c is a schematic top view of FIG. 1a with the package housing removed;

FIG. 1d is a schematic bottom view of a chip package structure;

FIG. 2 is a schematic diagram of another chip package structure;

FIG. 3 is a schematic top view of a first embodiment of a chip package structure according to an embodiment of the present application;

FIG. 4a is a schematic cross-sectional view in the direction B-B in FIG. 3;

FIG. 4b is an enlarged view of portion C of FIG. 4 a;

FIG. 4c is an enlarged view of portion H of FIG. 4 a;

FIG. 5 is a schematic top view of the package body and the thermally conductive insulating layer of FIG. 3 removed;

FIG. 6 is a schematic bottom view of a first embodiment of a chip package structure according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a process flow of a chip package structure according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a second embodiment of a chip package structure according to an embodiment of the present application;

FIG. 9 is a schematic top view of a third embodiment of a chip package structure according to the present application;

FIG. 10a is a cross-sectional view taken along the direction D-D in FIG. 9;

FIG. 10b is a cross-sectional view taken along the direction E-E in FIG. 9;

FIG. 11 is a schematic top view of the package body and the thermally conductive insulating layer of FIG. 9 removed;

FIG. 12 is a schematic bottom view of a third embodiment of a chip package structure according to the present application;

fig. 13a is a schematic diagram of a structure before and after deformation of a connection pin of a chip package structure according to an embodiment of the present application;

FIG. 13b is a schematic diagram illustrating an assembly of connection pins of a chip package structure according to an embodiment of the present application;

FIG. 14 is a schematic diagram illustrating a processing flow of a third embodiment of a chip package structure according to the present application;

FIG. 15 is a schematic top view of a fourth embodiment of a chip package structure according to the present application;

FIG. 16a is a schematic cross-sectional view taken in the direction F-F of FIG. 15;

FIG. 16b is a schematic cross-sectional view in the direction G-G of FIG. 15;

FIG. 17 is a schematic top view of FIG. 15 with the package housing and thermally conductive insulating layer removed;

FIG. 18 is a schematic bottom view of a fourth embodiment of a chip package structure according to an embodiment of the present application;

Fig. 19 is a schematic side view of a fourth implementation of a chip package structure according to an embodiment of the present application.

Reference numerals illustrate:

The prior art comprises the following steps:

100', chip packaging structure;

1', chip, 11', big core, 12', small core;

2', a carrier plate and 3', a plastic package shell.

The application comprises the following steps:

100. A chip packaging structure;

1. Chip, 101, top surface, 102, bottom surface, 103, side surface, 11, big core, 12, small core;

2. a carrier plate; 21, a bulge part, 211, a clamping hole, 22, an adhesive layer;

3. The packaging structure comprises a packaging shell, 31, a heat radiating piece, 311, a first heat radiating fin, 312, a second heat radiating fin, 312A, a first part, 312B, a second part, 313, a connecting pin, 313A, an elastic clamping section, 32 and a plastic packaging piece;

4. a thermally conductive insulating layer;

51. 52, second electric connector, 53, lead wire;

z, first direction.

Detailed Description

Further advantages and effects of the present application will become apparent to those skilled in the art from the disclosure of the present specification, by describing the embodiments of the present application with specific examples. While the description of the application will be presented in connection with certain embodiments, it is not intended to limit the features of this application to only this embodiment. Rather, the purpose of the present application is to cover other alternatives or modifications, which may be extended by the claims based on the application. The following description contains many specific details for the purpose of providing a thorough understanding of the present application. The application may be practiced without these specific details. Furthermore, some specific details are omitted from the description in order to avoid obscuring the application. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.

It should be noted that in this specification, like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "top," "bottom," and the like indicate an azimuth or a positional relationship based on that shown in the drawings, and are merely for convenience of description and to simplify the description, but do not indicate or imply that the apparatus or elements to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

In the description of the present application, it should be understood that "electrically connected" in the present application may be understood as that components are in physical contact and electrically connected, and may be understood as that different components in a circuit configuration are connected by a printed circuit board (printed circuit board, PCB) copper foil or a wire or other physical circuit capable of transmitting an electrical signal.

In the description of the present application, it should be noted that the mutual perpendicularity in the present application is not absolute perpendicularity, and that the approximate perpendicularity (for example, the included angle between two structural features is 89.9 °) due to the machining error and the assembly error is also within the scope of the mutual perpendicularity in the present application. The mutual parallelism in the present application is not absolute, and approximate parallelism (e.g., an angle of 0.1 ° between two structural features) due to machining errors and assembly errors is also within the scope of the mutual parallelism in the present application. The axial symmetry in the present application is not absolute, and approximate axial symmetry (e.g., a partial structure offset by a distance or angle with respect to the symmetry axis) due to machining errors and assembly errors is also within the scope of the axial symmetry in the present application. The present application is not particularly limited thereto.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Some chip package structures are first described with reference to the accompanying drawings.

Referring to fig. 1a to 1d, fig. 1a is a schematic top view of a chip package structure, fig. 1b is a schematic cross-sectional view of fig. 1a along a direction A-A, fig. 1c is a schematic top view of fig. 1a with a package housing removed, and fig. 1d is a schematic bottom view of a chip package structure.

As shown in fig. 1 a-1 d, the chip package structure 100 'includes a chip 1', a carrier plate 2', and a plastic package 3'. The bottom surface of the chip 1 'is mounted on the carrier plate 2' by curing a curing material (such as glue), and the chip is encapsulated in a plastic package housing 3 'formed by curing the plastic package material, so as to form the chip package structure 100'. (here or it can be understood that the plastic package body 3 'formed after the curing of the plastic package material serves as the entire package body of the chip package structure 100')

At this time, the heat generated from the chip 1' is transferred to the plastic package case 3', and heat exchange is performed with air through the plastic package case 3', thereby completing the entire heat dissipation process. The heat conduction and heat dissipation capability of the plastic package 3 'are weak, and the heat dissipation capability of the chip package structure 100' is poor.

The chip package structure shown in fig. 1b, for example, has:

P=(T_j-T_x)/θ

Wherein, P is the heat dissipation power of the chip packaging structure, P _b refers to the heat dissipation power of the bottom surface of the chip packaging structure, P _c refers to the heat dissipation power of the top surface of the chip packaging structure, and P _a refers to the total heat dissipation power of the chip packaging structure, and the unit is W. T _j is the temperature of the chip, T _x is the ambient temperature (i.e. the temperature outside the chip package structure), the temperature unit is the temperature, θ is the thermal coefficient of the chip to air under various conditions, θ _jb is the thermal coefficient of the chip to the bottom surface of the chip package structure, and θ _jc is the thermal coefficient of the chip to the top surface of the chip package structure.

Taking a common plastic packaging material as epoxy resin, taking a heat dissipation structure and a copper material as an example as the carrier plate 2', only considering the heat dissipation of the top surface and the bottom surface of the chip packaging structure, setting the temperature T _j of the chip to 125 ℃ and setting the ambient temperature T _x to 119 ℃ to calculate the heat dissipation power of the chip packaging structure 100'. The thermal resistance parameters of the chip to air at this time are:

θ_jb＝1.2℃/W、θ_jc=12°C/W

The heat dissipation power P _b of the bottom surface of the chip packaging structure is calculated as P _b = (125-119 ℃) and 1.2 ℃/W=5W

The heat dissipation power P _c of the bottom surface of the chip packaging structure is as follows:

P_c=(125°C-119°C)/12°C/W=0.5W

At this time, the total heat dissipation power P _a of the chip package structure is:

P_a＝P_b+P_c=5.5W

As can be obtained from the above calculation, the maximum heat dissipation power of the entire chip package structure 100' is 5.5W. It can be seen that the heat dissipation capability of the chip package structure 100' at this time is poor.

And, when the chip is a plurality of chips, other problems may occur. Problems with the multi-chip structure will be described below with reference to the accompanying drawings.

Referring to fig. 2, fig. 2 is a schematic structural diagram of another chip package structure.

As shown in fig. 2, the chip package structure may specifically include a plurality of chips. The multiple chips are divided into two specifications, one is called a large core 11 '(i.e., a large chip), and the other is called a small core 12' (i.e., a small chip). In operation, the large core 11 'typically generates a higher temperature due to a higher heat generation, while the small core 12' generates a lower heat generation and a lower temperature. And there is no reliable heat transfer path between the large and small cores 12' at this time, resulting in a state where the temperature difference between them is large. In this case, first, the temperature inside the chip package structure 100' is not uniform, which affects the overall service life of the chip package structure 100' during long-term use, and second, the large core 11' lacks a heat dissipation path, and the generated heat cannot be dissipated. In use, the large core 11' is easy to cause rapid excessive heat and a large amount of heat cannot be dissipated (or can be simply called as heat accumulation of the large core 11 '), further the large core 11' is unstable in work and short in service life, and the whole performance cannot be exerted.

In summary, the chip package structure provided in the prior art has poor heat dissipation performance, which is not beneficial to the stable operation of the chip.

Therefore, the chip packaging structure provided by the application has a good heat dissipation effect and is beneficial to the stable operation of the chip.

The application also provides electronic equipment, and the chip packaging structure applying the application. The electronic equipment is enabled to run more stably and have better performance. The electronic device in the embodiment of the present application is a device with a data processing function, and may include, but is not limited to, a cellular phone (cellular phone), a smart phone (smart phone), a laptop (laptop computer), a smart watch (SMART WATCH), a smart bracelet (smart wristband), and the like.

Referring to fig. 3-6, fig. 3 is a schematic top view of a first embodiment of a chip package structure according to an embodiment of the present application, fig. 4a is a schematic cross-sectional view along a direction B-B in fig. 3, fig. 4B is an enlarged view of a portion C in fig. 4a, fig. 4C is an enlarged view of a portion H in fig. 4a, fig. 5 is a schematic top view of the package body and the heat conductive insulating layer removed in fig. 3, and fig. 6 is a schematic bottom view of the first embodiment of the chip package structure according to an embodiment of the present application. The chip package structure is understood to be a structure obtained by packaging a chip.

As shown in fig. 3-6, the chip package structure 100 includes at least one chip 1, a carrier 2, a thermally conductive and insulating layer 4, and a package housing 3. It will be understood by those skilled in the art that at least one chip 1 as described herein may refer to one chip or a chipset formed by a plurality of chips, and the present application is not limited herein.

For example, as shown in fig. 4a, in one embodiment, at least one chip 1 may be one chip 1, thereby achieving higher single core performance or simplifying the structure for cost saving. In yet another alternative embodiment, at least one chip 1 may be a plurality of chips (or be understood as a plurality of large core structures or a plurality of small core structures) of the same size, so as to obtain better multi-threaded performance of the electronic device. In yet another alternative embodiment, at least one chip may be a plurality of chips of different sizes (or may be understood as a large core structure), as will be described in more detail below.

It should be noted that, the plurality of large core structures mentioned herein may be understood as structures between a single core structure and a large core structure, and the principle is consistent with the combination of the single core structure and the large core structure. Therefore, for simplicity of explanation, the single large core structure and the large core structure will be respectively exemplified below, and the multiple large core schemes will not be described again.

Further, in the present application, the type of the chip 1 is not limited. For example, in some embodiments, the chip 1 may be a silicon substrate chip, where the chip is manufactured by integrating a transistor, a resistor, a capacitor, and other microelectronic devices with a silicon substrate. Such a chip is widely used in a variety of applications,

The cost is lower, the large-scale production and processing are convenient, and the cost of the electronic equipment can be saved. In other embodiments, the chip may be a sapphire substrate chip, a silicon carbide substrate chip or a diamond substrate chip, so as to improve the structural strength or durability. The application is not limited in this regard.

It should be noted that, the chip 1 may be a single bare chip or a stacked bare chip, or a functional module formed by stacking chips. The bare chip is usually in the form of a large wafer or a single frequency chip, and becomes a component of a semiconductor element, an integrated circuit or a more complex circuit after being packaged, and the stacked bare chip refers to a chip formed by stacking a plurality of bare chips together.

As shown in fig. 4a to 4c, the chip 1 has a top surface 101 and a bottom surface 102 disposed opposite to each other in a first direction z, and a side surface 103 connected between the top surface 101 and the bottom surface 102. The top surface 101 may also be referred to as a front surface or an active surface, and is a surface with potential, in which microelectronic components such as transistors, resistors, capacitors, etc. are integrated in the chip 1, and it is understood that the chip 1 includes components or circuits that require a power source to perform functions, and the components or circuits located in the chip 1 may be electrically connected to the outside through pins or pads. In one example, the chip 1 is already soldered with pins or pads on the active surface of the chip 1 before shipment, the pins or pads having an electrically conductive effect, through which electrical connection of the chip 1 to external devices is achieved. Opposite the top surface 101 in the first direction z of the chip 1 is a bottom surface 102, which bottom surface 102 may be referred to as back surface. The side surface 103 is each surface between the top surface 101 and the bottom surface 102, or may be understood as a surface other than the top surface 101, the bottom surface 102 of the outer surface of the chip 1.

The first direction z described herein may be understood as a thickness direction of the chip 1, and may be understood as a thickness direction of the chip package structure 100.

As shown in fig. 4a to 4c, the bottom surface 102 of the chip 1 is mounted on the carrier 2, and the heat conductive insulating layer 4 and the chip 1 are encapsulated in the encapsulation housing 3. Further, as shown in fig. 4c and understood in conjunction with fig. 4a, in one embodiment, the top surface 101 of the chip has at least one first electrical connector 51, the chip package structure 100 further includes at least one second electrical connector 52 disposed corresponding to the at least one first electrical connector 51, and the second electrical connector 52 is located on the lower surface of the plastic package 32 and/or the thermally conductive insulating layer 4 and is exposed outside the chip package structure 100, and each first electrical connector 51 is electrically connected to the corresponding second electrical connector 52 through a lead 53.

Here or as it can be understood that the top surface 101 of the chip 1 is provided with the first electrical connector 51 and the second electrical connector 52 is led out at the outer surface of the chip package structure 100, and the first electrical connector 51 and the second electrical connector 52 are electrically connected by the lead 53. And the second electrical connector 52 is disposed to be exposed with respect to the chip package structure 100, so that when the chip 1 needs to be connected with an external electronic device, the external electronic device needs only to be electrically connected with the exposed second electrical connector 52, and the electrical connection between the external electronic device and the chip 1 can be achieved. Thereby facilitating electrical connection of the chip package structure 100 with other electronic devices of the electronic apparatus. The ease of use and versatility of the chip package structure 100 as a module is enhanced.

By way of example, the chip package structure is connected to other electronic devices of the electronic device, which may include, but are not limited to, a circuit board (motherboard or sub-board), speakers, various sensors, etc., through a second electrical connector, the application is not limited thereto.

As shown in fig. 4a and 4c, the specific structures of the first electrical connector 51, the second electrical connector 52 and the lead 53 are not limited.

As illustrated in fig. 4a and 4c, the first electrical connection 51 may be embodied as a pad or pin (also referred to as a pin) in one embodiment. And the second electrical connector 52 may be a pin or pad for an external interface terminal. The lead 53 may be a metal wire, specifically, may be gold wire (Au), aluminum wire (Al), aluminum silicon wire, or the like (si—al), may be a wire, may be an FPC, or the like, as long as the first electrical connector 51 and the second electrical connector 52 can be electrically connected, and the present application is not limited herein. The pads mentioned above may be metal pads, such as aluminum pads or the like.

It will be appreciated by those skilled in the art that the specific number of first electrical connectors 51, second electrical connectors 52 and leads 53 is likewise not limited and may be one or more, and those skilled in the art may flexibly adjust to design requirements.

The above is a structural description of the chip included in the embodiment of the present application, and the carrier will be described below with reference to the accompanying drawings.

As shown in fig. 3 to 6, the carrier plate 2 according to the embodiment of the present application is mainly used as a carrier of the chip 1 and is used as a basic structure of the chip package structure 100 to facilitate processing, such as mounting the chip 1 and the package housing 3. The carrier plate 2 may also have other functions, for example, in one embodiment the chip 1 may also be grounded via the carrier plate 2, etc. The application is not limited in this regard.

Those skilled in the art will appreciate that the specific materials of the carrier plate 2 described herein are not limited. In one embodiment, the carrier plate 2 may be made of metal with better thermal conductivity, so as to facilitate mass production and ensure low cost. In another alternative embodiment, the carrier plate may be made of a more complex material, such as a copper-nickel-tin alloy, to further enhance the strength and thermal conductivity of the carrier plate. The application is not limited in this regard.

The above is a description of the action and the material of the carrier, and in order to use the surface of the chip package structure as a heat dissipation surface to the greatest extent, at least part of the carrier 2 may be configured as a heat conduction structure.

As shown in fig. 6 and understood in connection with fig. 4a, in one embodiment at least part (part or whole) of the carrier plate 2 is provided as a thermally conductive structure (e.g. a metal sheet or metal plate) with a surface facing away from the chip 1 being exposed with respect to an outer surface of the plastic package 32. Here or it may be understood that at least a portion of the surface of the carrier 2 away from the chip 1 is also used as a heat dissipation surface, so that heat generated by the chip 1 can be dissipated through the carrier 2, thereby enhancing the heat dissipation capability of the chip package structure 100 to the greatest extent.

It should be noted that the specific connection manner of the chip 1 and the carrier plate 2 is not limited as well.

As shown in fig. 4b and understood in connection with fig. 4a, in one embodiment, the chip 1 may be adhesively secured to the carrier plate 2 by means of an adhesive layer 22. The chip 1 and the carrier plate 2 are ensured to be fixed stably, and the processing difficulty is also ensured to be lower during processing. In yet another alternative embodiment, the chip 1 and the carrier plate 2 may be fixed by curing a curing material, which is not limited herein.

The specific structure of the adhesive layer described herein is not limited.

In an embodiment, the bonding layer 22 may be an electrically conductive and heat conductive material, such as graphene glue, so as to cooperate with the carrier plate 2 set to a heat conductive structure in the foregoing, so that the chip 1 may further dissipate heat through the heat conductive structure of the carrier plate 2, so as to obtain a better heat dissipation effect, and make the chip 1 grounded through the carrier plate 2. In another alternative embodiment, the adhesive layer 22 may be formed by applying glue and curing, or a double sided tape may be used, which is not limited herein.

The foregoing describes basic components of the chip package structure 100 according to the embodiment of the present application, and the following describes specific embodiments of the present application.

As shown in fig. 3-6, the package housing 3 includes a heat sink 31 and a molding member 32, and the heat sink 31 is connected to the molding member 32 and fixed relative to the molding member 32. In the first direction z, the carrier 2, the chip 1, the heat conductive insulating layer 4 and the heat sink 31 are stacked in order, and at least part of the top surface 101 of the chip 1, the heat conductive insulating layer 4 and the heat sink 31 are in contact in order. And the surface of the heat sink 31 facing away from the chip 1 in the first direction z is exposed with respect to the outer surface of the molding compound 32.

It may be understood here that, in the first direction z, the chip 1, the heat conductive insulating layer 4 and the heat dissipation member 31 are sequentially stacked and sequentially contacted, so that a heat dissipation channel is formed inside the chip package structure 100, that is, the chip 1 serves as a heat generating device, heat generated by the heat generating device is transferred to the heat dissipation member 31 through the heat conductive insulating layer 4, and heat exchange is performed between the heat dissipation member 31 having a better heat dissipation capability and air, and the entire heat dissipation process is completed.

Compared with the heat dissipation mode that the heat is conducted to the plastic package shell after the heat is generated by the chip in the full plastic package structure and the heat is exchanged by the plastic package shell and the air, the heat dissipation performance of the chip package structure provided by the embodiment of the application is greatly improved, and the heat dissipation mode that the heat is conducted to the heat dissipation piece 31 by the heat conduction insulating layer 4 after the heat is generated by the chip 1 provided by the embodiment of the application and the heat exchange is conducted by the heat dissipation piece 31 and the air is obviously higher in efficiency. This can make the temperature lower in the case where the chip heating values are the same, and the heating value that can be tolerated in the case where the chip temperatures are the same is larger. The method is beneficial to adapting chips with stronger performance and higher power consumption and better releasing the performance.

Meanwhile, the package housing 3 formed by the heat dissipation element 31 and the plastic package element 32 can still completely package the chip, so that the stability and the safety of the chip package structure 100 can be ensured while the heat dissipation performance of the chip package structure 100 is enhanced.

To better illustrate the effectiveness of embodiments of the present application, quantitative calculations are performed below in conjunction with exemplary data.

The chip package structure shown in FIG. 4a has, according to the thermodynamic formula

P=(T_j-T_x)/θ

Taking copper as an example of the material of the heat dissipation element 31 and the carrier 2 (other calculation conditions are the same as those of the foregoing exemplary calculation of the prior art), the heat dissipation power of the chip package structure 100 is calculated. At this time, the thermal resistance parameters of the chip package structure are:

θ_jb＝1.2K/W、θ_jc=1.2K/W

The heat dissipation power P _b of the bottom surface of the chip package structure is calculated as follows:

P_b=(125°C-119°C)/1.2°C/W=5W

P_c=(125°C-119°C)/1.2°C/W=5W

P_a＝P_b+P_c=10W

Substituting the calculated result, the overall heat dissipation power of the chip package structure 100 is 10W, and thus the heat dissipation effect of the chip package structure 100 is obviously improved. Compared with the chip packaging structure in the prior art, if the junction temperature of the device is kept the same, the heat consumption of the device can be increased to 10W.

The foregoing is a description of the basic concepts and principles of the chip package structure according to the present application, and the following detailed description of possible specific structures of each component will be given with reference to the accompanying drawings.

The heat conductive insulating layer will be described first with reference to the drawings.

Those skilled in the art will appreciate that the specific coverage area of the thermally conductive and insulating layer is not limited.

As shown in fig. 4a, in one embodiment, the thermally conductive insulating layer 4 covers the entire top surface 101 of the chip 1. The top surface 101 of the chip 1 is ensured to be integrally contacted with the heat conducting insulating layer 4, so that the heat dissipation can be uniformly carried out as a whole, and the situation that part of the chip 1 does not have path heat dissipation because the part is not contacted with the heat conducting insulating layer 4 is avoided. It will be appreciated by those skilled in the art that in other alternative embodiments, the thermally conductive insulating layer 4 may also cover a portion of the top surface 101 of the chip 1, as the application is not limited in this regard.

Further, in one embodiment, to further improve the heat conduction efficiency, the heat conduction insulating layer 4 may further cover at least one side 103 of the chip 1. Here or as can be appreciated, at least one side 103 of the chip 1 is also in contact with the thermally conductive and insulating layer 4, further improving the efficiency of heat exchange between the chip 1 and the thermally conductive and insulating layer 4 by increasing the contact area between the chip 1 and the thermally conductive and insulating layer 4.

In one embodiment, the thermally conductive insulating layer 4 may also cover all sides 103 of the chip 1 in order to maximize the thermally conductive efficiency. Here or it may be understood that all the side surfaces 103 of the chip 1 are in contact with the heat conductive insulating layer 4, so that the contact area between the chip 1 and the heat conductive insulating layer 4 is increased to the greatest extent, and the heat exchange efficiency between the chip 1 and the heat conductive insulating layer 4 is improved.

The heat conductive insulating layer 4 may cover only a portion of the side 103 of the chip 1, or may not cover the side 103 of the chip 1, which is not limited by the present application.

In the above embodiments, the heat conductive capability of the chip 1 is enhanced by increasing the contact area between the chip 1 and the heat conductive insulating layer 4 by taking the chip 1 as a whole. When a plurality of chips 1 are provided, the temperature between the chips can be balanced by filling gaps between the chips 1 with the heat conductive insulating layer 4.

The specific material of the heat conductive insulating layer 4 is not limited as well.

As shown in fig. 4a, in one embodiment, the material of the thermally conductive insulating layer 4 is a curable thermally conductive insulating material, such as curable thermally conductive insulating silicone or curable thermally conductive insulating gel. In yet another alternative embodiment, the material of the thermally conductive insulating layer 4 is a non-curable thermally conductive insulating material, such as thermally conductive silicone grease and thermally conductive oil, etc. The heat conduction insulating layer with better fluidity is obtained, so that the heat conduction insulating layer is in full contact with the surface of the chip, and the heat exchange efficiency of the heat conduction insulating layer 4 and the chip 1 is improved. The application is not limited in this regard.

The specific material of the heat conductive insulating layer 4 is described above, and the specific material of the plastic package 32 is not limited.

As shown in fig. 4a, in one embodiment, the material of the plastic package 32 may be Epoxy Resin (Epoxy Resin) to obtain a plastic package with high mechanical strength, excellent heat resistance and chemical stability, and the Epoxy Resin has low cost, which is beneficial to the cost reduction of the chip package structure. In another alternative embodiment, the material of the plastic package 32 may be Polyester Resin (Polyester Resin), crystal glue (Silicone) and Organic Silicone (Organic Silicone), so as to improve the service life and electrical insulation of the plastic package. The application is not limited in this regard.

The specific structure of the plastic package 32 is described above, and the specific structure and materials of the heat sink 31 will be described below with reference to the accompanying drawings.

As shown in fig. 3 and 4a, it will be understood by those skilled in the art that the specific material of the heat sink 31 is not limited.

Illustratively, the heat sink 31 may be made of a metal material (e.g., copper, aluminum, silver, etc.) with good heat dissipation performance, and on the one hand, the metal material generally has good heat dissipation performance and can exchange heat with air with high efficiency. On the other hand, the metal material is generally simpler to process and shape, and is convenient for mass production.

In another alternative embodiment, the heat dissipation element 31 may also be made of a non-metal material with better heat dissipation performance (such as heat conducting ceramic and polymer) to improve the overall insulation performance of the package housing, so that the property of the package housing is more stable and the service life is longer.

As shown in fig. 3 and 4a, in one embodiment, the heat sink 31 includes a first heat sink 311, and at least a portion of the top surface 101 of the chip 1, the thermally conductive insulating layer 4, and the heat sink 31 are sequentially in contact in a first direction z, and a surface of the first heat sink 311 facing away from the chip 1 is exposed with respect to an outer surface of the molding compound 32 in the first direction z. The first heat sink 311 may be understood as constituting part of the outer surface of the chip package structure 100, exposed with respect to the outer surface of the molding compound 32, so that it may directly exchange heat with air.

By providing the heat sink 31 to include the first heat sink 311, on the one hand, the difficulty in processing the entire chip package structure 100 is reduced, and on the other hand, the cost of the heat sink 31 is relatively low, which is beneficial for cost control of the entire chip package structure 100.

Further, as shown in fig. 4a, in one embodiment, the projection of the first heat sink 311 completely covers the projection of the chip 1 on a plane perpendicular to the first direction z. Thereby further increasing the surface area of the first heat sink 311 and enhancing the heat dissipation effect of the first heat sink 311.

The fixing method of the heat sink 31 is not limited.

As shown in fig. 4a, in an embodiment, when the heat conductive insulating layer 4 is formed by using the curable heat conductive insulating material, the heat dissipation member 31 may be cured and connected by using the curable heat conductive insulating layer 4, so that the chip package structure is simple to process and low in cost.

In order to better explain the feature of low processing difficulty of the chip package structure according to the embodiment of the present application, please refer to fig. 7, fig. 7 is a schematic diagram of a processing flow of the chip package structure according to the embodiment of the present application.

As shown in fig. 7, and as will be understood in connection with fig. 4a, when the thermally conductive insulating layer 4 is formed using the aforementioned curable thermally conductive insulating material, the heat sink 31 may be cured and connected by the curable thermally conductive insulating layer 4. At this time, the chip packaging structure in the embodiment of the application has the packaging flow that firstly, a large wafer is thinned, and the thickness of the wafer is reduced by polishing. And then cutting the large wafer to obtain single chips 1, assembling the chips 1 with the carrier plate prefabricated member (the carrier plate 2 and the second electric connecting piece 52 are obtained after cutting the frame on the periphery of the carrier plate prefabricated member), and electrically connecting the chips 1 with pins (namely the second electric connecting piece 52) on the carrier plate prefabricated member. A thermally conductive and insulating material is then filled or coated over the chip 1, and a first heat sink 311 is placed over the thermally conductive and insulating material. After the heat conducting insulating material is cured, a heat conducting insulating layer 4 is formed, and the heat conducting insulating layer 4 and the first radiating fins 311 are fixedly connected through the heat conducting insulating material curing. And filling gaps among the parts by using a plastic packaging material, and packaging the heat conduction insulating layer 4 and the chip 1 to form a plastic package 32. Finally, the carrier plate prefabricated member is cut to form a final carrier plate 2 through electroplating, printing and other processes. Compared with the chip packaging structure processing flow in the prior art, only the steps of filling or coating the heat-conducting insulating material and placing the first radiating fins 311 are added, and when in processing, the heat radiating piece 31 is only required to be placed in the heat-conducting insulating material, and the heat radiating piece 31 can be fixed through the solidification of the heat-conducting insulating material, so that the front and rear working procedures are not required to be added, the processing is easy, and the cost of the chip packaging structure is not excessively increased.

In yet another alternative embodiment, the heat sink 31 may be secured in other ways to make the connection more stable, such as by providing a connection foot on the heat sink. This scheme will be described in detail hereinafter.

The foregoing is a detailed description of basic embodiments of the application, and several additional alternative embodiments of the application are described below.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a second implementation of a chip package structure according to an embodiment of the application.

As shown in fig. 8, as described above, in another alternative embodiment, at least one chip may be a plurality of chips 1 having different sizes. At least one chip is also referred to as a large core structure because it includes a larger chip (also known as a large core 11, which typically consumes more power and performs more strongly) and several smaller chips (also known as small cores 12, which typically consume less power and perform less strongly). One large nucleus 11 and several small nuclei 12 are arranged at intervals in a plane perpendicular to the first direction z. One large core 11 and several small cores 12 may be electrically connected to each other, for example, by electrically connecting first electrical connectors on the top surface of each chip via leads.

The structure enables the electronic equipment to be operated by different numbers or kinds of chips under different working conditions. For example, high load tasks are handled by a single large core 11, thereby providing optimal performance and minimal latency. While low load tasks are handled by multiple corelets 12, thereby enhancing energy consumption performance. Therefore, the energy consumption and the performance are integrated, the chip can work with proper power consumption under different scenes, and enough computing power is provided when needed, so that the performance and the endurance time of the electronic equipment are integrated, and the use experience of a user is greatly improved.

As shown in fig. 8, at least one chip 1 is a large core 11 and a plurality of small cores 12 arranged at intervals on a plane perpendicular to the first direction z, and the heat conductive insulating layer 4 is also filled in a gap between any two adjacent chips 1 in the plurality of chips 1 and contacts two side surfaces 103 opposite to any two adjacent chips 1. Here or it can be understood that by filling the thermally conductive and insulating layer 4 into the gaps between the chips 1, heat exchange between the chips 1 can also take place with a high efficiency.

By the design, under the multi-chip scene, the large core 11 with larger heating value can transfer part of heat to the small core 12 with smaller heating value, so that the temperatures of the chips tend to be consistent, the temperature difference between the chips is reduced, and the chip damage caused by overlarge temperature difference is avoided. On the other hand, the temperature of the large core 11 can be made lower, and local overheating due to heat failing to be dissipated can be avoided.

The above is an illustration of an embodiment of a chip package structure in a multi-core scenario, and as described above, in another alternative embodiment, the fixing of the heat dissipation element may also be implemented by using a connection pin.

Referring to fig. 9-12, fig. 9 is a schematic top view of a third embodiment of a chip package structure according to an embodiment of the present application, fig. 10a is a cross-sectional view along the D-D direction in fig. 9, fig. 10b is a cross-sectional view along the E-E direction in fig. 9, fig. 11 is a schematic top view of the package body and the heat conductive insulating layer removed in fig. 9, and fig. 12 is a schematic bottom view of a third embodiment of a chip package structure according to an embodiment of the present application.

As shown in fig. 9 to 12, the heat dissipation element 31 may further include a plurality of connection pins 313 arranged at intervals on a plane perpendicular to the first direction z, wherein one end of each connection pin 313 is connected to and fixed relative to the first heat dissipation plate 311, and each connection pin 313 extends along the first direction z. The outer peripheral edge of the carrier plate 2 is provided with a plurality of protruding parts 21 protruding outwards and corresponding to the plurality of connecting pins 313, each protruding part 21 of the plurality of protruding parts 21 is provided with a clamping hole 211, and the other end of each connecting pin 313 of the plurality of connecting pins 313 is clamped with the clamping hole 211 on the corresponding protruding part 21 so as to fixedly connect the heat dissipation part 31 with the carrier plate 2.

Here or it may be understood that the plurality of connection pins 313 are disposed on the heat dissipation element 31, the plurality of protruding portions 21 are disposed on the outer edge of the carrier 2, and the plurality of clamping holes 211 are disposed on the protruding portions 21 and correspond to the plurality of connection pins 313 one by one. In the mounting process, the connection pins 313 of the heat dissipation element 31 are only required to be clamped with the corresponding clamping holes 211, so that the mounting can be completed. The design can guarantee on the one hand that the installation is comparatively simple, on the other hand, can guarantee to connect comparatively stably, improves the holistic life of chip packaging structure. At this time, the fixing of the heat dissipation element 31 is mainly achieved through the cooperation of the connecting pins 313 and the clamping holes 211 on the protruding portions 21, so that there is no requirement on whether the heat conducting and insulating layer is a curable material, and the application range is wider.

The specific structure of the protruding portion 21 is not limited, and in one embodiment, the protruding portion 21 and the carrier plate 2 are integrally formed. In yet another alternative embodiment, the protruding portion 21 and the carrier plate 2 are a separate structure fixed to each other, which is not limited herein.

The specific structure of the connection pins 313 is not limited.

Further, in order to secure the fixing effect after installation, improvement can be made with respect to the connection pins.

Fig. 13 a-13 b show schematic views of the structure of the chip package structure before and after deforming the connection pins, and fig. 13b shows schematic views of the structure of the chip package structure assembled.

As shown in fig. 13A-13 b, in one embodiment, the connection leg 313 also has a resilient snap-fit segment 313A. The elastic clamping section 313A is configured as a hollow elastic structure (or can be understood as a fish-eye structure), and the elastic structure penetrates through the clamping hole 211 and elastically abuts against the hole wall of the clamping hole 211. Or it may be understood that the width of the elastic clamping section 313A is greater than the width of the clamping hole 211 when not under force, and when installed, the elastic clamping section 313A is forced in the width direction and compressed in the width direction and then placed into the clamping hole 211. So that the elastic clamping section 313A can elastically abut against the clamping hole 211 after entering the clamping hole 211. The design can effectively reduce the condition that the fit structure is not matched precisely enough due to machining tolerance in the machining process, and the connection reliability is provided while the assembly is convenient.

In order to illustrate that the heat sink is simply processed by the fixing manner of the connecting pins 313, refer to fig. 14, and fig. 14 is a schematic process flow of the third embodiment of the chip package structure according to the embodiment of the application.

As shown in fig. 14, and as will be understood with reference to fig. 9-13 b, the heat dissipation element 31 is fixed to the carrier plate 2 by the connection pins 313, and compared with the process in the prior art, only the steps of filling the heat conductive insulating material, placing the first heat dissipation plate 311, and inserting the connection pins 313 into the clamping holes 211 are added (other steps are described above, and are not repeated here). During processing, the fixing of the heat dissipation element 31 can be completed only by inserting the connecting pins 313 on the heat dissipation element 31 into the clamping holes. The processing difficulty of the chip packaging structure is not excessively increased.

The above is a description of the first fin structure and its possible fixing means. In order to further increase the heat dissipation area of the package housing of the chip package structure, the heat dissipation member may further include a plurality of second heat dissipation fins.

Referring to fig. 15-19, fig. 15 is a schematic top view of a fourth embodiment of a chip package structure according to an embodiment of the present application, fig. 16a is a schematic cross-sectional view of the chip package structure according to an embodiment of the present application, fig. 16b is a schematic cross-sectional view of the chip package structure according to an embodiment of the present application, fig. 17 is a schematic top view of the chip package structure according to an embodiment of the present application after the package shell and the heat conductive insulating layer are removed, fig. 18 is a schematic bottom view of the fourth embodiment of the chip package structure according to an embodiment of the present application, and fig. 19 is a schematic side view of the fourth embodiment of the chip package structure according to an embodiment of the present application.

As shown in fig. 15-19, in one embodiment, the heat dissipation element 31 further includes a plurality of second heat dissipation fins 312, and each of the plurality of second heat dissipation fins 312 has a stepped structure and includes a first portion 312A and a second portion 312B, wherein one end of the first portion 312A is connected to an outer edge of the first heat dissipation fin 311, and the other end is connected to one end of the second portion 312B. The first portion 312A is encapsulated in the plastic package 32, and the surface of the second portion 312B remote from the thermally conductive and insulating layer 4 forms at least part of the outer side of the encapsulation housing 3. On the one hand, by providing the second heat sink 312, portions in the respective sides of the chip package structure 100 are also used as heat dissipation surfaces for heat dissipation, further improving the heat dissipation performance of the heat sink 31. On the other hand, by providing the second heat sink 312 in a stepped structure, the outer peripheral portion of the top of the chip package structure 100 is still filled with the plastic package 32, thereby ensuring the impact resistance of the chip package structure 100.

As shown in fig. 15-19, in one embodiment, the plurality of second fins 312 are sequentially connected in a plane perpendicular to the first direction z to form an annular frame structure. Here or it may be understood that portions of each side of the chip package structure 100 are provided as heat dissipation surfaces, further enhancing the heat dissipation area of the chip package structure 100, thereby enhancing the heat dissipation capability of the chip package structure 100.

It should be noted that the specific fixing manner of the heat sink including the second heat sink is not limited. In one embodiment, the connection may be cured by a curable thermally conductive insulating layer, as described above. In another embodiment, the heat sink may be fixed to the carrier by the connection pins.

Taking the way of providing connection pins as an example, as shown in fig. 15-19, when the heat dissipation element 31 further includes a plurality of second heat dissipation fins 312, each of the second heat dissipation fins 312 has a step structure and includes a first portion 312A and a second portion 312B, one end of each of the plurality of connection pins 313 is connected to and relatively fixed to the other end of the second portion 312B, so that one end of each of the connection pins 313 is connected to the first heat dissipation fin 311 through the corresponding second heat dissipation fin 312, thereby simplifying the structure of the heat dissipation element 31.

The connection between the components of the heat sink 31 is not limited as well.

In one embodiment, the heat sink 31 is an integrally formed, unitary structure. The number of parts is reduced, and the processing difficulty is reduced. In yet another alternative embodiment, the components of the heat sink 31 may be separate structures fixedly attached to each other. The application is not limited in this regard.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. The chip packaging structure is characterized by comprising at least one chip, a carrier plate, a heat conduction insulating layer and a packaging shell, wherein the bottom surface of the at least one chip is arranged on the carrier plate, and the heat conduction insulating layer and the at least one chip are packaged in the packaging shell;

The packaging shell comprises a heat dissipation part and a plastic packaging part, wherein in a first direction, the carrier plate, the at least one chip, the heat conduction insulating layer and the heat dissipation part are sequentially stacked, at least part of the top surface of the at least one chip, the heat conduction insulating layer and the heat dissipation part are sequentially contacted, the surface of the heat dissipation part, which is away from the at least one chip in the first direction, is exposed relative to the outer surface of the plastic packaging part, the first direction is parallel to the thickness direction of the chip packaging structure, and the top surface and the bottom surface of the at least one chip are oppositely arranged in the first direction.

2. The chip package structure of claim 1, wherein the heat spreader includes a first heat sink, at least a portion of a top surface of the at least one chip, the thermally conductive insulating layer, and the heat spreader are in contact in sequence in the first direction, a surface of the first heat sink facing away from the at least one chip being exposed relative to an outer surface of the plastic package in the first direction.

3. The chip package structure of claim 2, wherein the heat spreader further comprises a plurality of second heat sinks, each of the plurality of second heat sinks having a stepped structure and comprising a first portion and a second portion, one end of the first portion being connected to an outer edge of the first heat sink, and the other end being connected to one end of the second portion;

The first part is encapsulated in the plastic package, and the surface of the second part, which is far away from the heat conducting insulating layer, forms at least part of the outer side surface of the encapsulation shell.

4. The chip package structure of claim 3, wherein the plurality of second heat sinks are sequentially connected on a plane perpendicular to the first direction to form an annular frame structure.

5. The chip package structure according to any one of claims 2 to 4, wherein the heat spreader further comprises a plurality of connection pins arranged at intervals on a plane perpendicular to the first direction, one end of each of the plurality of connection pins is connected to the first heat sink and is fixed relatively, and each of the connection pins extends along the first direction;

The outer peripheral edge of the carrier plate is provided with a plurality of protruding parts protruding outwards and corresponding to the plurality of connecting pins, each protruding part of the plurality of protruding parts is provided with a clamping hole, and the other end of each connecting pin of the plurality of connecting pins is clamped in the corresponding clamping hole on the protruding part so as to fixedly connect the heat dissipation piece with the carrier plate.

6. The chip package structure of claim 5, wherein the connecting pins have elastic clamping sections, the elastic clamping sections are hollow elastic structures, and the elastic structures penetrate through the clamping holes and elastically abut against the hole walls of the clamping holes.

7. The chip package structure of claim 6, wherein when the heat spreader further comprises a plurality of second heat sinks, each of the second heat sinks has a stepped structure and includes a first portion and a second portion, one end of each of the plurality of connection pins is connected to and fixed relative to the other end of the second portion, such that one end of each of the connection pins is connected to the first heat sink through the corresponding second heat sink.

8. The chip package structure of any of claims 2-4, wherein the projection of the first heat sink completely covers the projection of the at least one chip in a plane perpendicular to the first direction.

9. The chip package structure of any one of claims 1-4, wherein the thermally conductive insulating layer is a curable thermally conductive insulating material.

10. The chip package structure of claim 9, wherein the heat spreader is connected to the thermally conductive and insulating layer by curing.

11. The chip package structure of any of claims 1-4, wherein the thermally conductive insulating layer covers an entire top surface of the at least one chip.

12. The chip package structure of any of claims 1-4, wherein the thermally conductive insulating layer further covers at least one side of the at least one chip.

13. The chip package structure of claim 12, wherein the thermally conductive insulating layer also covers all sides of the at least one chip.

14. The chip package structure according to any one of claims 1 to 4, wherein the at least one chip is a plurality of chips arranged at intervals on a plane perpendicular to the first direction, and the thermally conductive insulating layer is further filled in a gap between any two adjacent chips of the plurality of chips and is in contact with two sides opposite to the any two adjacent chips.

15. The chip package structure of any of claims 1-4, wherein the top surface of the at least one chip has at least one first electrical connector, the chip package structure further comprising at least one second electrical connector disposed in correspondence with the at least one first electrical connector, the at least one second electrical connector being located on a lower surface of the plastic package and/or the thermally conductive insulating layer, and the at least one second electrical connector being exposed with respect to an outer surface of the plastic package, each of the at least one first electrical connector being electrically connected to a corresponding second electrical connector by a lead.

16. The chip package structure according to any one of claims 1 to 4, wherein the heat sink is of an integral structure, and the heat sink is made of a metal material;

At least a portion of the carrier plate is configured as a thermally conductive structure having a surface facing away from the at least one chip exposed with respect to an outer surface of the plastic package.

17. An electronic device comprising a chip package structure as claimed in any one of claims 1-16.