Disclosure of utility model
The application mainly aims to provide a four-two wire conversion circuit for baseband transmission, so as to realize direct loading of baseband signals on two core wires for transmission and reduce wiring cost.
In order to achieve the above object, the present application provides a four-two-wire conversion circuit for baseband transmission, comprising:
The PHY chip is electrically connected with a transformer;
The transformer comprises a primary winding A, a secondary winding C, a primary winding E, a secondary winding F, a primary winding B and a secondary winding E;
The TX+ pin of the PHY chip is connected with the corresponding primary winding A, and the TX-pin is connected with the corresponding primary winding B;
RX+ and RX-pins of the PHY chip are respectively connected with two ends of the secondary winding E;
The two ends of the primary winding E are respectively connected with one end of the primary winding A and one end of the primary winding B, and the two ends of the secondary winding F are connected with two-core wires and output PODL+ and PODL-.
Further, the tx+ pin of the PHY chip is connected to the corresponding intermediate tap of the primary winding a, and the TX-pin of the PHY chip is connected to the corresponding intermediate tap of the primary winding B.
Further, an end of the primary winding a away from the primary winding E is connected to an end of the primary winding B away from the primary winding E through an impedance resistor and a second blocking capacitor.
Further, one end of the secondary winding F outputting the PODL-is connected to one of the two-core wires through a first blocking capacitor.
Further, the impedance of the impedance resistor, i.e. the impedance of the first blocking capacitor, is equal to the impedance of the primary winding E, so as to cancel the TX signal on the primary winding B, thereby avoiding the PHY chip from receiving the TX signal.
Further, both ends of the secondary winding C are connected through a resistor.
Further, the primary winding a is divided into a primary winding A1 and a primary winding A2 by a center tap, the other end of the primary winding A1 is connected to the impedance resistor R1, and the other end of the primary winding A2 is connected to one end of the primary winding E.
Further, the primary winding B is divided into a primary winding B1 and a primary winding B2 through a middle tap, the other end of the primary winding B1 is connected with the second blocking capacitor, and the other end of the primary winding B2 is connected with one end, far away from the primary winding A2, of the primary winding E.
Furthermore, the number of the PHY chips and the number of the transformers are two, the connection of the two PHY chips and the transformers is mirror image, and the two transformers are connected through the two-core wires.
The four-two wire conversion circuit for baseband transmission provided by the utility model directly loads baseband signals to the two core wires for transmission, avoids large-scale rewiring, can effectively solve the problem of circuit self-loop through circuit design, and has the advantages of simple circuit structure and more convenient debugging and maintenance.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description of the present application and the above-described drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the present application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate an azimuth or a positional relationship based on that shown in the drawings. These terms are only used to better describe the present application and its embodiments and are not intended to limit the scope of the indicated devices, elements or components to the particular orientations or to configure and operate in the particular orientations.
Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the present application will be understood by those of ordinary skill in the art according to the specific circumstances.
In addition, the term "plurality" shall mean two as well as more than two.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
Referring to fig. 1, a four-two line conversion circuit for baseband transmission includes PHY chips electrically connected with a transformer T1, further, two PHY chips, each of which is electrically connected with a transformer, and two groups of PHY chips and transformer connection combinations are mirror image arrangements. Fig. 1 shows a connection manner of two groups of PHY chips and a transformer connection combination, specifically, tr+ pins of a transformer T1 and a transformer T2 are connected by a wire and transmit podl+ signals, and TR-pins of the transformer T1 and the transformer T2 are respectively connected by corresponding connected first blocking capacitors C1 and C2 and transmit PODL-signals.
The present embodiment is explained by taking a connection combination of one group of PHY chips and a transformer as an example, specifically, the transformer includes a primary winding a and a secondary winding C, a primary winding E and a secondary winding F, a primary winding B and a secondary winding E, further, the primary winding a is divided into a primary winding A1 and a primary winding A2 by a middle tap, and the primary winding B is divided into a primary winding B1 and a primary winding B2 by a middle tap. The other end of the primary winding A2, i.e., the end other than the intermediate tap, is connected to one end of the primary winding E, and the other end of the primary winding B2, i.e., the end other than the intermediate tap, is connected to the end of the primary winding E remote from the primary winding A2. Further, the other end of the primary winding A1, i.e., the end other than the intermediate tap, is connected to the impedance resistor R1, and the other end of the primary winding B1, i.e., the end other than the intermediate tap, is connected to the second blocking capacitor C3. Further, both ends of the secondary winding C are connected through a resistor R3.
Two ends of the secondary winding F are respectively connected to a TR+ pin and a TR-pin of the transformer T1 so as to realize that one end of the secondary winding F outputs a PODL+ signal and the other end outputs a PODL-signal through the first blocking capacitor C1.
The tx+ pin of the PHY chip is connected to the corresponding primary winding a and the TX-pin is connected to the corresponding primary winding B, in particular the tx+ pin is connected to the intermediate tap of the primary winding a and the TX-pin is connected to the intermediate tap of the primary winding B.
The RX+ and RX-pins of the PHY chip are connected to the two ends of the secondary winding E, respectively.
Referring to fig. 1, in signal transmission, a tx+ signal of the PHY chip is transmitted to a center tap of the primary winding a through a td+ pin of the transformer T1, and is returned to the TD-pin of the PHY chip through the primary winding A2-primary winding E-primary winding B2-TD-pin. So as to realize that the signal is transmitted to the secondary winding F through the primary winding E and is further output to the lead through the first blocking capacitor C1.
Meanwhile, in this embodiment, the impedance between the impedance resistor R1 and the first blocking capacitor C1 is equal to the impedance of the primary winding E, so as to cancel TX signals received by the primary winding B1 and the primary winding B2 during signal transmission, thereby avoiding the RX end of the PHY chip from receiving the TX signals and effectively avoiding line loop-back.
During signal reception, the signal on the wire passes through the secondary winding F-primary winding E-primary winding A2-primary winding A1-impedance resistor R1-second blocking capacitor C3-primary winding B1-primary winding B2-secondary winding E, and at this time, the signal polarities on the primary winding B1 and the primary winding B2 are the same, so that the signal can return to the RX end of the PHY chip.
It should be appreciated that the above description is for a circuit design between one set of PHY chips and their connected transformers, and this embodiment illustrates that the two sets of PHY chips and their connected transformers are mirror image arrangements, so that the circuit arrangement of the other set of PHY chips and their connected transformers is a mirror image relationship to the above description.
In summary, the four-two-wire conversion circuit for baseband transmission disclosed by the application can realize baseband signal transmission through two core wires, and avoid circuit self-loop design on the surrounding circuits of the PHY chip, thereby ensuring smooth signal receiving and transmitting.
The specific manner in which the operations of the units in the above embodiments are performed has been described in detail in the embodiments related to the method, and will not be described in detail here.
The above is only a preferred embodiment of the present application, and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.