CN222050774U - Power domain controller hard-wired wake-up and delayed power-off timing logic circuit - Google Patents
Power domain controller hard-wired wake-up and delayed power-off timing logic circuit Download PDFInfo
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Abstract
The application relates to a hard-wire wake-up and time-delay power-down time sequence logic circuit of a power domain controller. The circuit comprises: the system comprises a power supply access module, a common mode filtering module, a hard wire awakening module and a filtering voltage stabilizing module; the power supply access module is respectively connected with the automobile low-voltage storage battery and the common mode filtering module and is used for receiving the current accessed by the automobile low-voltage storage battery and transmitting the current to the common mode filtering module; the common mode filter module is respectively connected with the power supply access module and the hard wire wake-up module and is used for preventing an external circuit from interfering with the circuit and isolating the circuit from interfering with the external circuit; the hard wire awakening module is respectively connected with the common mode filtering module and the filtering voltage stabilizing module and is used for receiving an awakening source signal so as to conduct the filtering voltage stabilizing module; the filtering voltage stabilizing module is respectively connected with the hard wire awakening module and the automobile internal circuit, and is used for stabilizing the voltage in the circuit to be a fixed voltage and conducting the circuit; the filtering voltage stabilizing module is used for supplying power to the internal circuit of the automobile.
Description
Technical Field
The application relates to the technical field of hard-wire awakening of new energy vehicles, in particular to a power domain controller hard-wire awakening and delayed power-down time sequence logic circuit.
Background
When the vehicle is in a state of not being awakened, the circuit is smaller and better under the condition of meeting standby (the current is generally called as static current), and when the vehicle is in an awakening state, the circuit works normally. The circuit for waking up the normal operation of the vehicle by the external signal input is called a wake-up circuit;
The key point of the wake-up circuit is that under the premise of meeting the function, the static current is as small as possible, and the magnitude of the static current directly influences the static parking time of the vehicle; when the key is closed to stop the vehicle, most parts need a reaction time, and the current work is completely finished and then completely powered down, namely delayed power down.
Along with the continuous development of new energy automobile industry, the requirements on static current are higher and higher, a plurality of forms of wake-up circuits and delay power-down circuits are generated in an accelerating way, but in most cases, schemes such as relays, transformers and the like are adopted to finish the process, and along with the requirements of carbon neutralization and carbon reaching standards, a controllable delay power-down time sequence circuit with high-efficiency wake-up is urgently needed.
Disclosure of utility model
Based on the above, it is necessary to provide a power domain controller hard-wire wake-up and time-delay power-down sequential logic circuit with simple and reliable wake-up, low power consumption, small quiescent current and controllable time-delay power-down.
A power domain controller hard-wired wake-up and time-delay power down sequential logic circuit, comprising: the system comprises a power supply access module, a common mode filtering module, a hard wire awakening module and a filtering voltage stabilizing module;
The system comprises a power supply access module, a common mode filtering module, a hard wire awakening module and a filtering voltage stabilizing module;
The input end of the power supply access module is connected with an automobile low-voltage storage battery, the output end of the power supply access module is connected with the common mode filtering module, the automobile low-voltage storage battery inputs current into the power supply access module, and the power supply access module transmits the current to the common mode filtering module;
The input end of the common mode filter module is connected with the power supply access module, the output end of the common mode filter module is connected with the hard wire awakening module, and the common mode filter module comprises a filter and isolates the circuit from other circuits through the filter;
The input end of the hard wire awakening module is connected with the common mode filtering module, the output end of the hard wire awakening module is connected with the filtering voltage stabilizing module, and when the hard wire awakening module receives an awakening source signal, the hard wire awakening module conducts the filtering voltage stabilizing module;
The input end of the filtering voltage stabilizing module is connected with the hard wire awakening module, the output end of the filtering voltage stabilizing module is connected with the internal circuit of the automobile, and the filtering voltage stabilizing module receives the current transmitted by the hard wire awakening module and limits the voltage value of the current input into the filtering voltage stabilizing module to be a fixed voltage value; the filtering voltage stabilizing module conducts the internal circuit of the automobile and transmits the current with the fixed voltage value to the internal circuit of the automobile.
In one embodiment, the power access module includes:
A transient suppression diode, a first PMOS transistor, and a first zener diode, wherein the transient suppression diode, the first PMOS transistor, and the first zener diode are connected in parallel;
The transient suppression diode clamps a voltage value corresponding to the current input into the power access module to a fixed voltage value;
When the input end of the low-voltage storage battery power supply is reversely connected, the first PMOS tube controls the power supply access module to be in a disconnected state;
Before the current is input into a first PMOS tube of the power supply access module, the first zener diode limits the voltage value corresponding to the current to a fixed voltage value.
In one embodiment, the common mode filtering module includes:
two capacitors and a filter, wherein each capacitor is connected in parallel with the filter.
In one embodiment, the hard-wired wake module includes:
The plurality of sub-hard wire wake-up modules comprise a second PMOS tube, an NMOS tube and a second voltage stabilizing diode;
the sub-hard wire wake-up module, the second PMOS tube, the NMOS tube and the second zener diode are connected in parallel;
when a wake-up source signal is received, the sub-hard-wire wake-up module conducts a connecting circuit between the hard-wire wake-up module and the filtering voltage stabilizing module;
when the input end of the filter voltage stabilizing module is connected in reverse, the second PMOS tube controls the connecting circuit to be in a disconnection state;
When the power supply access terminal connected to the sub-hard-wire wake-up module is in reverse, the NMOS tube controls the hard-wire wake-up module to be in a disconnected state;
And the second voltage stabilizing diode limits the voltage value corresponding to the current before the second PMOS tube of the hard wire wake-up module is input to a fixed voltage value.
In one embodiment, the sub-hardwired wake-up module includes:
a plurality of hard wire wake-up circuits connected in parallel, each hard wire wake-up circuit corresponding to a wake-up source signal;
The hard wire wake-up circuit comprises a wake-up source connected to a power supply and an anti-reflection diode;
When a wake-up source signal is received, the wake-up source is connected with a power supply to input current to the hard-wire wake-up circuit;
when the wake-up source signal of the hard wire wake-up circuit is inconsistent with the wake-up source signal corresponding to the hard wire wake-up circuit, the anti-reflection diode controls the hard wire wake-up circuit to be in an off state.
In one embodiment, the sub-hard-line wake module further includes:
The microcontroller is connected with any target hard-wire wake-up circuit;
When the hard-wire wake-up circuit is turned on, the microcontroller controls the target hard-wire wake-up circuit to be continuously turned on, and after all the awakened influence wake-up circuits are turned off, the microcontroller continuously controls the target hard-wire wake-up circuit to be continuously turned on.
In one embodiment, the microcontroller further comprises:
When the internal circuit of the automobile is disconnected, the microcontroller enters a delay power-down mode, and when the execution duration of the delay power-down mode meets the delay duration, the microcontroller controls the target hard-wire wake-up circuit to be powered down.
In one embodiment, the wake-up source signal comprises:
An access signal when a vehicle key is accessed to a vehicle lock hole, an access signal when a quick and slow charging pile is accessed to a vehicle charging port, a timing wake-up signal input by a timing wake-up line, a wake-up signal input by a transceiver wake-up line and the like.
In one embodiment, the power access module receives a current input by a low-voltage storage battery of an automobile, and transmits the current to the hard-wire wake-up module through the common mode filtering module;
When the hard wire awakening module receives an awakening source signal, the hard wire awakening module conducts a connecting circuit between the hard wire awakening module and the filtering voltage stabilizing module;
when the connecting circuit is conducted, the current is subjected to current voltage stabilization processing through the filtering voltage stabilization module to obtain target current, and the target current is transmitted to the automobile internal circuit, so that the automobile internal circuit is powered.
In one embodiment, the method is applied to the power domain controller hard-wire wake-up and time-delay power-down sequential logic device.
The power domain controller hard wire awakening and time-delay power-down sequential logic circuit is firstly implemented by adopting the MOS tube and resistor voltage dividing mode, has quite simple circuit structure, is realized by adopting the conventional MOS, has numerous component types, strong selectivity and low cost. And secondly, the control logic is simple, the control can be completed only by a passive element, and the MCU is controlled in a programmable manner in a time delay power-down time length. And the MOS is in a complete disconnection state, the quiescent current is extremely low, the uA level can be achieved, the low-power consumption requirement can be completely met, the electric quantity of the automobile storage battery is hardly lost, and the battery energy consumption is saved. Then, the PMOS tube has large conduction current, small internal resistance, low loss and small heating value, and has larger significance especially in large-current and high-power equipment. Can provide stable and reliable power supply for the later stage and is not easy to burn. Finally, the circuit supports various signal awakenings, and can also input awakenings at the same time. The level signal of the wake-up source supports a wide voltage input. No mutual interference is generated between the wake-up sources.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a diagram illustrating current transfer in power domain controller hard-wired wake-up and delayed power down sequential logic circuitry according to an embodiment.
FIG. 2 is a block diagram of a hard-wired wake-up module according to an embodiment;
FIG. 3 illustrates power domain controller hard-wired wake-up and delayed power down sequential logic circuitry according to an embodiment.
Reference numerals illustrate:
TD1 is a transient suppression diode, Q1 is a first PMOS tube, Q2 is a second PMOS tube, Q3 is an NMOS tube, ZD1 is a first zener diode, ZD2 is a second zener diode, D1, D2 … D5 are anti-reflection diodes of each hard wire wake-up circuit, D2, D4 … D6 are transient suppression diodes of each hard wire wake-up circuit, C1, C2 … C10 are capacitors, R1, R2 … R8 are resistors, and L1, L2 are filters.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
It is understood that "at least one" means one or more and "a plurality" means two or more. "at least part of an element" means part or all of the element.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
As shown in fig. 1, the power domain controller hard-line wake-up and time-delay power-down sequential logic circuit of an embodiment is characterized by comprising: the system comprises a power supply access module, a common mode filtering module, a hard wire awakening module and a filtering voltage stabilizing module; the input end of the power supply access module is connected with an automobile low-voltage storage battery, the output end of the power supply access module is connected with the common mode filtering module, the automobile low-voltage storage battery inputs current into the power supply access module, and the power supply access module transmits the current to the common mode filtering module; the input end of the common mode filter module is connected with the power supply access module, the output end of the common mode filter module is connected with the hard wire awakening module, and the common mode filter module comprises a filter and isolates the circuit from other circuits through the filter; the input end of the hard wire awakening module is connected with the common mode filtering module, the output end of the hard wire awakening module is connected with the filtering voltage stabilizing module, and when the hard wire awakening module receives an awakening source signal, the hard wire awakening module conducts the filtering voltage stabilizing module; the input end of the filtering voltage stabilizing module is connected with the hard wire awakening module, the output end of the filtering voltage stabilizing module is connected with the internal circuit of the automobile, and the filtering voltage stabilizing module receives the current transmitted by the hard wire awakening module and limits the voltage value of the current input into the filtering voltage stabilizing module to be a fixed voltage value; the filtering voltage stabilizing module conducts the internal circuit of the automobile and transmits the current with the fixed voltage value to the internal circuit of the automobile.
In one embodiment, the power access module includes: a transient suppression diode, a first PMOS transistor, and a first zener diode, wherein the transient suppression diode, the first PMOS transistor, and the first zener diode are connected in parallel; the transient suppression diode clamps a voltage value corresponding to the current input into the power access module to a fixed voltage value; when the input end of the low-voltage storage battery power supply is reversely connected, the first PMOS tube controls the power supply access module to be in a disconnected state; before the current is input into a first PMOS tube of the power supply access module, the first zener diode limits the voltage value corresponding to the current to a fixed voltage value.
In one embodiment, the common mode filtering module includes: two capacitors and a filter, wherein each capacitor is connected in parallel with the filter.
In one embodiment, as shown in FIG. 2, the hard-wired wake module includes: the plurality of sub-hard wire wake-up modules comprise a second PMOS tube, an NMOS tube and a second voltage stabilizing diode; the sub-hard wire wake-up module, the second PMOS tube, the NMOS tube and the second zener diode are connected in parallel; when a wake-up source signal is received, the sub-hard-wire wake-up module conducts a connecting circuit between the hard-wire wake-up module and the filtering voltage stabilizing module; when the input end of the filter voltage stabilizing module is connected in reverse, the second PMOS tube controls the connecting circuit to be in a disconnection state; when the power supply access terminal connected to the sub-hard-wire wake-up module is in reverse, the NMOS tube controls the hard-wire wake-up module to be in a disconnected state; and the second voltage stabilizing diode limits the voltage value corresponding to the current before the second PMOS tube of the hard wire wake-up module is input to a fixed voltage value.
In the above embodiment, as shown in fig. 3, power and Power are respectively the positive and negative poles of the low-voltage storage battery (namely, the commonly-called automobile storage battery) of the whole automobile, the upper half part of the lower diagram is an anti-reflection and filtering related circuit, and p+ and GND after filtering are the Power supplies for the internal circuit of the automobile component finally; TD1 is a transient suppression diode used for absorbing energy impact generated by inductive load and the like, so that stability of a later-stage power supply is ensured. Q1 is a PMOS tube for preventing the reverse connection of the power supply input terminal, when the potentials of the 1 pin and the 3 pin of the Q1 are equal after the reverse connection of the power supply, namely Vgs=0, the Q1 is in an off state (if the reverse applied voltage is not more than the maximum withstand voltage born by the VSD of the Q1, if the reverse spike pulse is the spike pulse, the TD1 can absorb the spike pulse, so that the voltage is embedded below the VSD), and a current loop cannot be formed, thereby ensuring that the rear-stage circuit is not burnt, namely the reverse connection preventing effect is achieved. When the power supply is positive and the pin 2D of the Q1 is positive, the power supply is conducted through the parasitic diode in the Q1, the voltage of the pin 3S is also positive, the voltage of the pin 1G is divided by the R1 and the R3 (the values of the R1 and the R3 are required to be selected by combining the conduction threshold value of the Q1 VGS), the voltage of the pin 1G is smaller than the voltage of the pin S, namely, the Vgs is smaller than the conduction threshold value of the Q1, and the Q1 is conducted.
ZD1 is a zener diode that protects VGS of Q1 from breakdown by overvoltage. C4, L2 and C5 together form a common mode filter circuit to prevent external interference from entering the internal circuit and isolate the internal interference from the external circuit. ZD2 is a voltage stabilizing tube and acts as ZD1.
In one embodiment, the sub-hard-line wake module includes: a plurality of hard wire wake-up circuits connected in parallel, each hard wire wake-up circuit corresponding to a wake-up source signal; the hard wire wake-up circuit comprises a wake-up source connected to a power supply and an anti-reflection diode; when a wake-up source signal is received, the wake-up source is connected with a power supply to input current to the hard-wire wake-up circuit; when the wake-up source signal of the hard wire wake-up circuit is inconsistent with the wake-up source signal corresponding to the hard wire wake-up circuit, the anti-reflection diode controls the hard wire wake-up circuit to be in an off state.
In the above embodiment, Q3 cannot be turned on when there is no hard-wire wake-up source, and R2 and R4 form a resistor voltage divider but cannot form a loop, so the 3-pin and 1-pin voltages of Q2 are equal, i.e. vgs=0, Q2 cannot be turned on, and thus p+ power cannot be provided to the subsequent stage.
When a hard-wire signal source exists, for example, a hard-wire wake-up signal 1 is in a high level, after D1 is in anti-reflection, R5 and R6 are divided (R5 and R6 are determined by combining a Q3 VGS conduction threshold value and an input voltage), VGS is greater than the conduction threshold value, so that Q3 is conducted, namely, a DS pin is conducted, and a 3 pin is in a low level. Through R2, R4 partial pressure, make Q2's Vgs < turn on threshold value, therefore Q2 switches on, and in pi type (C1, L1, C2) and large capacitance filter circuit lead to whole circuit to switch on, make ripple coefficient little, signal P+ output of voltage stabilization, provide stable voltage for the later stage circuit.
The hard-wire wake-up signals 1 to N can be in various modes, and the Q3 is a MOS tube and belongs to a voltage driving type, so that the wake-up signals can support power input wake-up signals (strong driving capability) of 3.3V, 5V, 12V and the like, and also can be high-level signals (weak driving capability) output by a singlechip or other chips.
When no wake-up signal is input, Q3 is in a closed state, the power supply input is closed and cut off at Q2, and only Q1 and R3 are connected in series to consume a little current (R1, R3 is M omega level resistance), so that the power consumption of the circuit is very weak, belongs to uA level, can be completely ignored, and saves energy consumption very.
In one embodiment, the sub-hard-line wake module further comprises: the microcontroller is connected with any target hard-wire wake-up circuit; when the hard-wire wake-up circuit is turned on, the microcontroller controls the target hard-wire wake-up circuit to be continuously turned on, and after all the awakened influence wake-up circuits are turned off, the microcontroller continuously controls the target hard-wire wake-up circuit to be continuously turned on.
In the above embodiment, the 1 st path of hard wire wake-up signal is connected to a certain GPIO port of the MCU microcontroller, when at least one path of external 2-N wake-up signal is input, the circuit is woken up to start working, and at this time, the GPIO port of the MCU microcontroller can output a high level, so that the circuit can be kept in its own state, and even if all external 2-N wake-up sources are powered down, the later stage circuit can still work normally, thereby realizing self-locking.
In one embodiment, the microcontroller further comprises: when the internal circuit of the automobile is disconnected, the microcontroller enters a delayed power-down mode, and when the execution duration of the delayed power-down mode meets the delay duration, the microcontroller controls the target hard-wire wake-up circuit to be powered down.
In the above embodiment, after the post-stage circuit completes the current actual operation, the GPIO self-locking release becomes low level, and the circuit is completely powered down to enter the shutdown mode. The time length of the power-down of the GPIO delay can be set through the MCU microcontroller according to the actual use condition of the circuit, the data of the later-stage circuit is stored before the power-down of the MCU microcontroller, and the later-stage relay or parts are released to enter a complete power-down power-off mode after the work such as disconnection is completed, so that the reliability and convenience of the circuit are ensured.
In one embodiment, waking up the source signal includes: an access signal when a vehicle key is accessed to a vehicle lock hole, an access signal when a quick and slow charging pile is accessed to a vehicle charging port, a timing wake-up signal input by a timing wake-up line, a wake-up signal input by a transceiver wake-up line and the like.
In the above embodiment, the hard-wire wake-up circuit supports multiple simultaneous input wake-ups, each wake-up source branch has an anti-reflection diode (D1, D3, D5..) and the circuits do not interfere with each other and have no effect. The wake-up source signal (i.e. hard-wire wake-up signal) CAN be a key KL15, a fast and slow charging pile, RTC timing, CAN wake-up and other wake-up modes.
In one embodiment, the power domain controller hard-wire wake-up and time-delay power-down sequential logic circuit receives current input by the low-voltage storage battery of the automobile through the power access module, and transmits the current to the hard-wire wake-up module through the common mode filter module. When the hard wire awakening module receives the awakening source signal, the hard wire awakening module conducts a connecting circuit between the hard wire awakening module and the filtering voltage stabilizing module. When the connecting circuit is conducted, the current is subjected to current voltage stabilization treatment through the filtering voltage stabilizing module, so that target current is obtained, and the target current is transmitted to the internal circuit of the automobile, so that the internal circuit of the automobile is powered.
In the description of the present specification, reference to the term "some embodiments," "other embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (10)
1. The utility model provides a power domain controller hard-wire wake-up and time delay power down sequential logic circuit which characterized in that includes:
The system comprises a power supply access module, a common mode filtering module, a hard wire awakening module and a filtering voltage stabilizing module;
The input end of the power supply access module is connected with an automobile low-voltage storage battery, the output end of the power supply access module is connected with the common mode filtering module, the automobile low-voltage storage battery inputs current into the power supply access module, and the power supply access module transmits the current to the common mode filtering module;
The input end of the common mode filter module is connected with the power supply access module, the output end of the common mode filter module is connected with the hard wire awakening module, and the common mode filter module comprises a filter and isolates the circuit from other circuits through the filter;
The input end of the hard wire awakening module is connected with the common mode filtering module, the output end of the hard wire awakening module is connected with the filtering voltage stabilizing module, and when the hard wire awakening module receives an awakening source signal, the hard wire awakening module conducts the filtering voltage stabilizing module;
The input end of the filtering voltage stabilizing module is connected with the hard wire awakening module, the output end of the filtering voltage stabilizing module is connected with an internal circuit of the automobile, and the filtering voltage stabilizing module receives the current transmitted by the hard wire awakening module and limits the voltage value of the current input into the filtering voltage stabilizing module to a fixed voltage value; the filtering voltage stabilizing module conducts the internal circuit of the automobile and transmits the current with the fixed voltage value to the internal circuit of the automobile.
2. The power domain controller hard-wired wake-up and delayed power down sequential logic circuit of claim 1, wherein the power access module comprises:
A transient suppression diode, a first PMOS transistor, and a first zener diode, wherein the transient suppression diode, the first PMOS transistor, and the first zener diode are connected in parallel;
The transient suppression diode clamps a voltage value corresponding to the current input into the power access module to a fixed voltage value;
When the input end of the low-voltage storage battery power supply is reversely connected, the first PMOS tube controls the power supply access module to be in a disconnected state;
Before the current is input into a first PMOS tube of the power supply access module, the first zener diode limits the voltage value corresponding to the current to a fixed voltage value.
3. The power domain controller hard-wired wake-up and delayed power down sequential logic circuit of claim 1, wherein the common mode filter module comprises:
two capacitors and a filter, wherein each capacitor is connected in parallel with the filter.
4. The power domain controller hard-wired wake-up and delayed power down sequential logic circuit of claim 1, wherein the hard-wired wake-up module comprises:
The plurality of sub-hard wire wake-up modules comprise a second PMOS tube, an NMOS tube and a second voltage stabilizing diode;
the sub-hard wire wake-up module, the second PMOS tube, the NMOS tube and the second zener diode are connected in parallel;
when a wake-up source signal is received, the sub-hard-wire wake-up module conducts a connecting circuit between the hard-wire wake-up module and the filtering voltage stabilizing module;
when the input end of the filter voltage stabilizing module is connected in reverse, the second PMOS tube controls the connecting circuit to be in a disconnection state;
When the power supply access terminal connected to the sub-hard-wire wake-up module is in reverse, the NMOS tube controls the hard-wire wake-up module to be in a disconnected state;
And the second voltage stabilizing diode limits the voltage value corresponding to the current before the second PMOS tube of the hard wire wake-up module is input to a fixed voltage value.
5. The power domain controller hard-wired wake-up and delayed power down sequential logic circuit of claim 4, wherein the sub-hard-wired wake-up module comprises:
a plurality of hard wire wake-up circuits connected in parallel, each hard wire wake-up circuit corresponding to a wake-up source signal;
The hard wire wake-up circuit comprises a wake-up source connected to a power supply and an anti-reflection diode;
When a wake-up source signal is received, the wake-up source is connected with a power supply to input current to the hard-wire wake-up circuit;
when the wake-up source signal of the hard wire wake-up circuit is inconsistent with the wake-up source signal corresponding to the hard wire wake-up circuit, the anti-reflection diode controls the hard wire wake-up circuit to be in an off state.
6. The power domain controller hard-wired wake-up and delayed power down sequential logic circuit of claim 5, wherein the sub-hard-wired wake-up module further comprises:
The microcontroller is connected with any target hard-wire wake-up circuit;
When the hard-wire wake-up circuit is turned on, the microcontroller controls the target hard-wire wake-up circuit to be continuously turned on, and after all the awakened influence wake-up circuits are turned off, the microcontroller continuously controls the target hard-wire wake-up circuit to be continuously turned on.
7. The power domain controller hard-wired wake-up and delayed power down sequential logic circuit of claim 6, wherein the microcontroller further comprises:
When the internal circuit of the automobile is disconnected, the microcontroller enters a delay power-down mode, and when the execution duration of the delay power-down mode meets the delay duration, the microcontroller controls the target hard-wire wake-up circuit to be powered down.
8. The power domain controller hard-wired wake-up and delayed power down sequential logic circuit of claim 7, wherein the wake-up source signal comprises:
The access signal when the vehicle key is accessed to the vehicle lock hole, the access signal when the quick and slow charging pile is accessed to the vehicle charging port, the timing wake-up signal input by the timing wake-up line, and the wake-up signal input by the transceiver wake-up line.
9. The power domain controller hard-wired wake-up and delayed power-down sequential logic circuit of any one of claims 1 to 8, wherein the power access module receives current input by a low-voltage battery of an automobile and transmits the current to the hard-wired wake-up module through the common-mode filter module;
When the hard wire awakening module receives an awakening source signal, the hard wire awakening module conducts a connecting circuit between the hard wire awakening module and the filtering voltage stabilizing module;
when the connecting circuit is conducted, the current is subjected to current voltage stabilization processing through the filtering voltage stabilization module to obtain target current, and the target current is transmitted to the automobile internal circuit, so that the automobile internal circuit is powered.
10. The power domain controller hard-wired wake-up and time-delay power-down sequential logic circuit according to any one of claims 1 to 8, wherein the power domain controller hard-wired wake-up and time-delay power-down sequential logic circuit is applied to power domain controller hard-wired wake-up and time-delay power-down sequential logic equipment.
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| CN202420235919.8U CN222050774U (en) | 2024-01-31 | 2024-01-31 | Power domain controller hard-wired wake-up and delayed power-off timing logic circuit |
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