CN221057790U

CN221057790U - Electronic equipment

Info

Publication number: CN221057790U
Application number: CN202322783082.9U
Authority: CN
Inventors: 马保军; 张治宇; 张龙; 张科; 陈金林
Original assignee: Emdoor Digital Technology Co ltd
Current assignee: Emdoor Digital Technology Co ltd
Priority date: 2023-10-16
Filing date: 2023-10-16
Publication date: 2024-05-31
Anticipated expiration: 2033-10-16

Abstract

The utility model provides electronic equipment, which is provided with a miniRJ female seat, wherein a first end of the miniRJ female seat is connected with an external RJ45 connector through an adapter wire, and a second end of the miniRJ female seat is connected with a CPU module; the patch cord includes: an RJ45 connecting seat and miniRJ45 male heads; the RJ45 connecting seat is connected with an external RJ45 connector, and the miniRJ male connector is connected with the miniRJ female connector; and the CPU module is used for carrying out network data signal transmission with the external RJ45 connector through the patch cord. Because the electronic equipment provided by the utility model is provided with the miniRJ female seat and is connected with the external RJ45 connector through the patch cord, compared with the existing RJ45 connector, the miniRJ female seat has smaller volume, so that the thickness of the electronic equipment can be reduced, the portability is improved, and the user experience is improved.

Description

Electronic equipment

Technical Field

The present utility model relates to the field of network interfaces, and in particular, to an electronic device.

Background

At present, in order to connect the network, the common electronic equipment is provided with an RJ45 interface, and the networking is realized by connecting the RJ45 interface with a network cable, but because the volume of the conventional RJ45 interface is larger, the electronic equipment which is light and thin becomes thick, portability is reduced, and user experience is poor.

The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present utility model and is not intended to represent an admission that the foregoing is prior art.

Disclosure of utility model

The utility model mainly aims to provide electronic equipment, and aims to solve the technical problem that in the prior art, the electronic equipment is heavy due to the fact that networking of the electronic equipment is realized through an RJ45 interface, and user experience is affected.

In order to achieve the above objective, the present utility model provides an electronic device, which is provided with a miniRJ female socket, wherein a first end of the miniRJ female socket is connected with an external RJ45 connector through an adapter cable, and a second end of the miniRJ female socket is connected with a CPU module;

the patch cord includes: an RJ45 connecting seat and miniRJ45 male heads;

The RJ45 connecting seat is connected with the external RJ45 connector, and the miniRJ male connector is connected with the miniRJ female connector;

and the CPU module is used for carrying out network data signal transmission with the external RJ45 connector through the patch cord.

Optionally, the electronic device further includes: the first resistor, the second resistor, the third resistor, the first capacitor and the second capacitor;

The pin A1 of the miniRJ ' 45 female seat is grounded, the pin G1 of the miniRJ ' 45 female seat is connected with the pin A1 of the miniRJ ' 45 female seat, the pin A4 of the miniRJ ' 45 female seat is connected with the second end of the first resistor, the first end of the first resistor is connected with a power supply, the first end of the first resistor is also connected with the first end of the first capacitor, the second end of the first capacitor is grounded, the pin A8 of the miniRJ ' 45 female seat is connected with the second end of the second resistor, the first end of the second resistor is grounded, the pin A9 of the miniRJ ' 45 female seat is connected with the second end of the third resistor, the first end of the third resistor is connected with the second end of the second capacitor, the first end of the second capacitor is grounded, the pin a12 of the miniRJ ' 45 female seat is grounded, and the pin G2 of the miniRJ ' 45's female seat is connected with the pin a12 of the miniRJ's 45's female seat.

Optionally, the electronic device further includes: a fourth resistor;

The B1 pin of the miniRJ45 female seat is grounded, the G3 pin of the miniRJ45 female seat is connected with the B1 pin of the miniRJ female seat, the B4 pin of the miniRJ45 female seat is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the first end of the third resistor, the B9 pin of the miniRJ45 female seat is connected with the A4 pin of the miniRJ45 female seat, the B12 pin of the miniRJ45 female seat is grounded, and the G4 pin of the miniRJ female seat is connected with the B12 pin of the miniRJ female seat.

Optionally, the electronic device further includes: an Ethernet module;

the Ethernet module is connected with the CPU module, and is also respectively connected with an A6 pin, an A7 pin, an A10 pin, an A11 pin, a B2 pin, a B3 pin, a B6 pin and a B7 pin of the miniRJ mother seat;

The Ethernet module is used for carrying out network data signal transmission with the external RJ45 connector through the patch cord.

Optionally, the ethernet module includes: a network chip;

The first pin of the network chip is connected with the A6 pin of the miniRJ '45 female seat, the second pin of the network chip is connected with the A7 pin of the miniRJ' 45 female seat, the fourth pin of the network chip is connected with the A10 pin of the miniRJ '45 female seat, the fifth pin of the network chip is connected with the A11 pin of the miniRJ' 45 female seat, the sixth pin of the network chip is connected with the B2 pin of the miniRJ '45 female seat, the seventh pin of the network chip is connected with the B3 pin of the miniRJ' 45 female seat, the ninth pin of the network chip is connected with the B6 pin of the miniRJ '45 female seat, and the tenth pin of the network chip is connected with the B7 pin of the miniRJ' 45 female seat.

Optionally, the electronic device further includes: the fifth resistor, the sixth resistor and the seventh resistor are connected;

The A5 pin of the miniRJ ' 45 female seat is connected with the second end of the fifth resistor, the first end of the fifth resistor is connected with the twenty-seventh pin of the network chip, the B5 pin of the miniRJ ' 45 female seat is connected with the first end of the sixth resistor, the second end of the sixth resistor is connected with the twenty-sixth pin of the network chip, the B8 pin of the miniRJ ' 45 female seat is connected with the first end of the seventh resistor, and the second end of the seventh resistor is connected with the twenty-fifth pin of the network chip.

Optionally, the pin definition of the miniRJ45 male head is consistent with the pin definition of the miniRJ female socket, the A6 th pin of the miniRJ45 male head is connected with the first pin of the RJ45 connecting socket, the A7 th pin of the miniRJ45 male head is connected with the second pin of the RJ45 connecting socket, the a10 th pin of the miniRJ45 male head is connected with the third pin of the RJ45 connecting socket, the a11 th pin of the miniRJ male head is connected with the fourth pin of the RJ45 connecting socket, the B2 nd pin of the miniRJ male head is connected with the fifth pin of the RJ45 connecting socket, the B3 rd pin of the miniRJ male head is connected with the sixth pin of the RJ45 connecting socket, the B6 th pin of the miniRJ male head is connected with the seventh pin of the RJ45 connecting socket, and the B7 th pin of the miniRJ male head is connected with the eighth pin of the RJ45 connecting socket.

Optionally, the miniRJ a 45 b female base includes: a terminal assembly and a female housing;

The terminal assembly is arranged in the female port shell, and a plurality of horizontally distributed conductive terminals are arranged on the terminal assembly;

The miniRJ male head comprises: a male port housing matched with the female port housing;

And a connecting terminal which is spliced with the conductive terminal is arranged in the male port shell.

Optionally, one of the inner wall of the female port shell and the outer wall of the male port shell is provided with a limiting projection, the other one of the inner wall of the female port shell and the outer wall of the male port shell is correspondingly provided with a avoiding groove, and the groove is used for being matched and positioned with the limiting projection.

Optionally, a plurality of limit bumps are provided, and the limit bumps are uniformly distributed on two sides of the terminal assembly;

the avoidance grooves are arranged in a plurality of corresponding to the limit protruding blocks.

The utility model provides electronic equipment, which is provided with a miniRJ female seat, wherein a first end of the miniRJ female seat is connected with an external RJ45 connector through an adapter wire, and a second end of the miniRJ female seat is connected with a CPU module; the patch cord includes: an RJ45 connecting seat and miniRJ45 male heads; the RJ45 connecting seat is connected with the external RJ45 connector, and the miniRJ male connector is connected with the miniRJ female connector; and the CPU module is used for carrying out network data signal transmission with the external RJ45 connector through the patch cord. Because the electronic equipment provided by the utility model is provided with the miniRJ female seat and is connected with the external RJ45 connector through the patch cord, compared with the existing RJ45 connector, the miniRJ female seat has smaller volume, so that the thickness of the electronic equipment can be reduced, the portability is improved, and the user experience is improved.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a block diagram of a first embodiment of an electronic device according to an embodiment of the present utility model;

fig. 2 is a schematic structural diagram of a first embodiment of an electronic device according to an embodiment of the present utility model;

Fig. 3 is a schematic structural diagram of a transfer wire in a first embodiment of an electronic device according to an embodiment of the present utility model;

Fig. 4 is a schematic structural diagram of a miniRJ a female socket in a first embodiment of an electronic device according to an embodiment of the present utility model;

fig. 5 is a schematic diagram illustrating dimensions of a miniRJ a female socket in a first embodiment of an electronic device according to an embodiment of the present utility model;

Fig. 6 is a schematic structural diagram of a miniRJ male head in a first embodiment of an electronic device according to an embodiment of the present utility model;

Fig. 7 is a schematic circuit diagram of a second embodiment of an electronic device according to an embodiment of the present utility model;

Fig. 8 is a schematic circuit diagram of an ethernet module in a second embodiment of an electronic device according to an embodiment of the present utility model;

Fig. 9 is a schematic circuit diagram of a transfer wire in a second embodiment of an electronic device according to an embodiment of the present utility model.

Reference numerals illustrate:

the achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the technical solutions should be considered that the combination does not exist and is not within the scope of protection claimed by the present utility model.

Referring to fig. 1, fig. 1 is a block diagram of a first embodiment of an electronic device according to an embodiment of the present utility model.

Based on fig. 1, a first embodiment of the electronic device of the present utility model is presented.

In this embodiment, the electronic device is provided with a miniRJ 45:45 female socket 1, a first end of the miniRJ 45:45 female socket 1 is connected with an external RJ45 connector through an adapter cable 2, and a second end of the miniRJ 45:45 female socket 1 is connected with a CPU module.

It should be noted that, the electronic device provided in the embodiment may be any device that needs to be networked, for example, a notebook computer, a tablet computer, etc., and the embodiment is not limited.

However, for easy understanding, referring to fig. 2, fig. 2 is a schematic structural diagram of a first embodiment of an electronic device according to an embodiment of the present utility model, as shown in fig. 2, and the notebook computer in fig. 2 may include: the base 3 and the display screen 4, the base 3 and the display screen 4 are connected, the miniRJ th mother seat 1 can be arranged at one end of the base 3, and of course, can be arranged at other positions on the notebook computer, and the example is not limited.

It can be understood that the size of the miniRJ female socket 1 can be similar to that of a standard TYPE-C interface, and the size of the standard TPYE-C interface is smaller than that of a standard RJ45 interface, so when the electronic device adopts the miniRJ female socket 1, the thickness of the electronic device can be reduced, the electronic device is lighter and thinner, the attractive appearance is improved, the electronic device is convenient to carry, and because the size of the miniRJ female socket 1 is smaller, raw materials required by the electronic device are reduced, and the yield is also improved.

It should be noted that, because the standard RJ45 interface is larger in size and is easy to deposit ash, the miniRJ female seat 1 of the embodiment is smaller in size and is not easy to deposit ash, and further the service life is further prolonged.

Further, the patch cord 2 includes: RJ45 connector blocks 21 and miniRJ45 male heads 22; the RJ45 connecting seat 21 is connected with the external RJ45 connector, and the miniRJ male connector 22 is connected with the miniRJ45 female seat 1;

The CPU module is configured to perform network data signal transmission with the external RJ45 connector through the patch cord 2.

It should be understood that the miniRJ male plug 22 may be mated with the miniRJ female plug 1, the external RJ45 connector may be a standard RJ45 interface, the external RJ45 connector may be connected to a standard cable, and the RJ45 connector 21 may be mated with the external RJ45 connector.

It should be understood that the cpu module may be any module for transmitting network data signals with an external network, which is not limited in this embodiment.

In order to facilitate understanding of the patch cord 2, referring to fig. 3, fig. 3 is a schematic structural diagram of the patch cord 2 in the first embodiment of the electronic device according to the embodiment of the present utility model, as shown in fig. 3, the RJ45 connection seat 21 and the miniRJ male connector 22 may be connected by a cable, and then the RJ45 connection seat 21 is connected with an external RJ45 connector, and the miniRJ male connector 22 is connected with the miniRJ female connector 1 on the electronic device, thereby realizing data signal transmission with an external network.

Further, referring to fig. 4, fig. 4 is a schematic structural diagram of a miniRJ a 45 female base 1 in a first embodiment of an electronic device according to an embodiment of the present utility model, as shown in fig. 4, the miniRJ a 45 female base 1 includes: a terminal assembly 111 and a female housing 112; the terminal assembly 111 is disposed inside the female housing 112, and a plurality of horizontally distributed conductive terminals 113 are disposed on the terminal assembly 111.

It should be noted that the female housing 112 may have a structure similar to a standard TYPE-C interface structure, and the conductive terminals 113 may be used for network data signal transmission.

Further, in order to facilitate explanation of the dimensions of the female socket 1 of miniRJ45, referring to fig. 5, fig. 5 is a schematic diagram of the dimensions of the female socket of miniRJ45 in the first embodiment of the electronic device according to the present utility model, as shown in fig. 5, the female socket 1 of miniRJ45 provided in the present embodiment shows 24 conductive terminals, A1 to a12 and B1 to B12 in sequence, wherein the horizontal distance from the A1 conductive terminal to the a12 conductive terminal is 5.55mm, the horizontal distance from the A1 conductive terminal to the B12 conductive terminal is 0.25mm, the horizontal distance from the a2 conductive terminal to the a11 conductive terminal is 4.50mm, the horizontal distance from the a3 conductive terminal to the perpendicular bisector of the interface is 0.50mm, the horizontal distance from the a11 conductive terminal to the perpendicular bisector is 2.375mm, the vertical distance from the conductive terminal to the B12 conductive terminal is 1.60mm, the vertical distance from the entire female socket housing 112 is 8.50mm, and the vertical distance from the female socket housing 112 of the non-overlapping portion with the conductive terminal 113 is 5.80±0.30 mm.

Further, referring to fig. 6, fig. 6 is a schematic structural diagram of a miniRJ male head in a first embodiment of an electronic device according to an embodiment of the present utility model, as shown in fig. 6, the miniRJ male head 22 includes: a male port housing 221 mated with the female port housing 112; a connection terminal 222 that is inserted into the conductive terminal 113 is provided in the male housing 221.

It is understood that the connection terminals 222 may be used for connection with cables of connection wires, the number of the connection terminals 222 corresponds to the number of the conductive terminals 113, and pin definitions of the connection terminals 222 are consistent with pin definitions of the conductive terminals 113.

It is appreciated that in some embodiments, since the conductive terminal 113 is floating, the portion corresponding to the floating conductive terminal 113 may not be provided with the connection terminal 222. For example, if the conductive terminals A2, A3, B10, and B11 of the miniRJ female socket 1 shown in fig. 7 are suspended, the connection terminal 222 may not be disposed at the position corresponding to the conductive terminals A2, A3, B10, and B11 on the miniRJ male head 22.

Still further, in order to limit the insertion of the standard TYPE-C interface in the market, as shown in fig. 4 and 6, one of the inner wall of the female housing 112 and the outer wall of the male housing 221 is provided with a limit bump 114, and the other one of the inner wall and the outer wall of the male housing is correspondingly provided with a recess 223, and the recess is used for being matched and positioned with the limit bump 114.

It should be understood that, in this embodiment, the inner wall of the female port housing 112 is provided with the limiting bump 114, and the outer wall of the male port housing 221 is provided with the avoiding groove 223, which can be reversed, and only when the miniRJ female seat 1 and the miniRJ male head 22 are plugged, the limiting bump 114 can smoothly slide in the limiting groove.

When the avoidance groove 223 is formed in the outer wall of the male port shell 221, the avoidance groove 223 is preferably formed in a position where the connection terminal 222 is not formed, so that the avoidance groove 223 avoids the connection terminal 222, space is reasonably utilized, and light and thin effects are achieved.

It should be emphasized that, in order to further increase the limiting effect, a plurality of the limiting protrusions 114 are provided, and the plurality of limiting protrusions 114 are uniformly distributed on two sides of the terminal assembly 111; the avoiding grooves 223 are disposed in plurality corresponding to the limit bump 114.

It should be noted that, in the embodiment described above, the two limiting protrusions 114 and the two avoiding grooves 223 are adopted for illustration, but the specific number is not limited, the limiting protrusions 114 in the embodiment are respectively disposed at two sides of the female port housing 112, the avoiding grooves 223 are respectively disposed at two sides of the male port housing 221, the specific positions correspond to the limiting protrusions 114, and the embodiment is not limited.

In a specific implementation, the present embodiment limits insertion of a standard TYPE-C interface on the market through the limiting bump 114 and the avoidance groove 223, so as to further increase safety.

Because the electronic equipment in this embodiment adopts the miniRJ45 female seat 1 and performs network data signal transmission with the external RJ45 connector through the patch cord 2, compared with the existing RJ45 connector through the standard, the miniRJ female seat 1 of this embodiment has smaller volume, thereby reducing the thickness of the electronic equipment, making the electronic equipment lighter and thinner, improving the appearance and being convenient to carry, and because the miniRJ female seat 1 has smaller volume, the raw materials required by the electronic equipment are reduced, the yield is improved along with the raw materials, dust is not easy to accumulate, and the service life is further prolonged; meanwhile, since the miniRJ female seat 1 and the miniRJ male head 22 in the embodiment respectively adopt the limit bump 114 and the avoidance groove 223, the safety is further increased.

Referring to fig. 7, fig. 7 is a schematic circuit diagram of a second embodiment of an electronic device according to an embodiment of the present utility model.

As shown in fig. 7, in this embodiment, the electronic device further includes: the first resistor R1, the second resistor R2, the third resistor R3, the first capacitor C1 and the second capacitor C2;

The pin A1 of the miniRJ45 female seat 1 is grounded, the pin G1 of the miniRJ45 female seat 1 is connected to the pin A1 of the miniRJ female seat 1, the pin A4 of the miniRJ45 female seat 1 is connected to the second end of the first resistor R1, the first end of the first resistor R1 is connected to the power supply (+v3p3a in fig. 7), the first end of the first resistor R1 is further connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is grounded, the pin A8 of the miniRJ45 female seat 1 is connected to the second end of the second resistor R2, the first end of the second resistor R2 is grounded, the pin A9 of the miniRJ45 female seat 1 is connected to the second end of the third resistor R3, the first end of the third resistor R3 is connected to the second end of the second capacitor C2, the first end of the second capacitor C2 is grounded, the pin a 24 of the first capacitor C2 is grounded, and the pin a 24 of the first resistor R45 is connected to the first end of the first resistor R2 is grounded, and the pin a12 of the 5245 female seat is connected to the 5212.

It should be noted that, the voltage value of the power supply can be set according to the actual situation, and the embodiment is not limited.

Further, the electronic device further includes: a fourth resistor R4;

The B1 pin of the miniRJ45 socket 1 is grounded, the G3 pin of the miniRJ socket 1 is connected with the B1 pin of the miniRJ socket 1, the B4 pin of the miniRJ socket 1 is connected with the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected with the first end of the third resistor R3 (RXCT in fig. 7), the B9 pin of the miniRJ socket 1 is connected with the A4 pin of the miniRJ socket 1, the B12 pin of the miniRJ socket 1 is grounded, and the G4 pin of the miniRJ socket 1 is connected with the B12 pin of the miniRJ socket 1.

Further, considering that the current modules for distributing the IP address are all disposed outside the electronic device, i.e. on the external patch cord 2, the IP address will also change when the patch cord 2 is replaced, so that the security is low, and therefore in this embodiment, the electronic device further includes: an Ethernet module;

the Ethernet module is connected with the CPU module, and is also respectively connected with an A6 pin, an A7 pin, an A10 pin, an A11 pin, a B2 pin, a B3 pin, a B6 pin and a B7 pin of the miniRJ45 female seat 1;

the ethernet module is configured to perform network data signal transmission with the external RJ45 connector through the patch cord 2.

It should be understood that the ethernet module may be a module for allocating an IP address, and further, since the ethernet module is disposed inside the electronic device, when the external patch cord 2 changes, the IP address is not changed, thereby improving security.

Further, the pin A2, pin A3, pin A5, pin B8, pin B10 and pin B11 of the miniRJ female socket 1 are suspended. Of course, in some embodiments, the A5 pin, the B5 pin, and the B8 pin can also be used as pins for connecting LEDs.

Note that, in miniRJ a 45 a female socket 1, pins are defined as follows: the pin A1 is GND_3, the pin A2 is SSTXp1, the pin A3 is SSTXn1, the pin A4 is VBUS_2, the pin A5 is CC1, the pin A6 is Dp1_2, the pin A7 is Dn1_2, the pin A8 is SBU1, the pin A9 is VBUS_4, the pin A10 is SSRXn2, the pin A11 is SSRXp2 and the pin A12 is GND_4; the B1 pin is GND_2, the B2 pin is SSTXp2, the B3 pin is SSTXn2, the B4 pin is VBUS_3, the B5 pin is CC2, the B6 pin is Dp1_1, the B7 pin is Dn1_1, the B8 pin is SBU2, the B9 pin is VBUS_1, the B10 pin is SSRXn1, the B11 pin is SSRXp1, and the B12 pin is GND_1. Wherein, the A4 pin and the B9 pin are power supply pins, and the G1 pin, the A12 pin, the G2 pin, the B1 pin, the G3 pin, the B12 pin and the G4 pin of the miniRJ45 busbar 1 are grounding pins.

Further, referring to fig. 8, fig. 8 is a schematic circuit diagram of an ethernet module in a second embodiment of an electronic device according to an embodiment of the present utility model; as shown in fig. 8, in this embodiment, the ethernet module includes: a network chip U1;

Wherein, the first pin of the network chip U1 is connected with the A6 pin of the miniRJ socket 1 (phy_ TRXP0 in fig. 8), the second pin of the network chip U1 is connected with the A7 pin of the miniRJ socket 1 (phy_trxn0 in fig. 8), the fourth pin of the network chip U1 is connected with the a10 pin of the miniRJ socket 1 (phy_ TRXP1 in fig. 8), the fifth pin of the network chip U1 is connected with the a11 pin of the miniRJ socket 1 (phy_trx1 in fig. 8), the sixth pin of the network chip U1 is connected with the B2 pin of the miniRJ socket 1 (phy_ TRXP2 in fig. 8), the seventh pin of the network chip U1 is connected with the B3 pin of the miniRJ socket 1 (phy_trx2 in fig. 8), the ninth pin of the network chip U1 is connected with the B6 pin of the 3245 socket 1 (phy_trx1 in fig. 8), and the sixth pin of the network chip U1 is connected with the B2 pin of the miniRJ socket 1 (phy_ TRXP in fig. 8).

It should be noted that, the model of the network chip U1 may be an RTL8111H-CG, and the chip adopts the most advanced DSP technology and the mixed mode model technology, and the RTL8111H-CG provides high-speed transmission through a CAT 5UTP cable or a CAT 3UTP (only 10 Mbps) cable, so as to implement functions of cross detection and automatic correction, polarity correction, adaptive equalization, crosstalk cancellation, echo cancellation, timing recovery, and error calibration, so as to provide powerful high-speed transmission and reception capability.

It can be understood that the first pin, the second pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the ninth pin, and the tenth pin of the network chip U1 are data transmission pins, which can be used for network data signal transmission with the miniRJ female socket 1.

Further, with continued reference to fig. 7 and 8, the electronic device further includes: the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are connected;

The pin A5 of the miniRJ female socket 1 is connected to the second end of the fifth resistor R5, the first end of the fifth resistor R5 is connected to the twenty-seventh pin of the network chip U1 (LED 0/ACT in fig. 7), the pin B5 of the miniRJ female socket 1 is connected to the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected to the twenty-sixth pin of the network chip U1 (LED 1/GP0 in fig. 7), the pin B8 of the miniRJ female socket 1 is connected to the first end of the seventh resistor R7, and the second end of the seventh resistor R7 is connected to the twenty-fifth pin of the network chip U1 (LED 2/LED1 in fig. 7).

It should be understood that the twenty-fifth pin, the twenty-sixth pin, and the twenty-seventh pin of the network chip U1 may be custom LED pins, and may be used for LED lamp display.

Further, the ethernet module further includes: third to thirteenth capacitances C3 to C13, eighth to thirteenth resistances R8 to R13, and first inductance L1;

The thirteenth pin of the network chip U1 is connected to the second end of the third capacitor C3, the first end of the third capacitor C3 is connected to the CPU module (db_peu0_x1_txp in fig. 8), the fourteenth pin of the network chip U1 is connected to the second end of the fourth capacitor C4, the first end of the fourth capacitor C4 is connected to the CPU module (db_peu0_x1_txn in fig. 8), the seventeenth pin of the network chip U1 is connected to the second end of the fifth capacitor C5, the first end of the fifth capacitor C5 is connected to the CPU module (db_peu0_x1_rxp in fig. 8), the eighteenth pin of the network chip U1 is connected to the second end of the sixth capacitor C6, and the first end of the sixth capacitor C6 is connected to the CPU module (db_peu0_x1_rxn in fig. 8).

Note that, the thirteenth pin and the fourteenth pin of the network chip U1 may be a differential pair for receiving PCI Express, and the seventeenth pin and the eighteenth pin of the network chip U1 may be a differential pair for transmitting PCI Express.

The fifteenth pin of the network chip U1 is connected to the CPU module (db_ PCIECLK _p in fig. 8), and the sixteenth pin of the network chip U1 is connected to the CPU module (db_ PCIECLK _n in fig. 8). The fifteenth pin and the sixteenth pin of the network chip U1 may be differential reference clock sources for PCI Express.

The twelfth pin of the network chip U1 is connected to the second end of the eighth resistor R8, and the first end of the eighth resistor R8 is connected to the power supply (+v3p3s in fig. 8). The twelfth pin of the network chip U1 may be used to receive a reference clock request signal, which may be used to request a reference clock for PCI Express to be initiated.

The nineteenth pin of the network chip U1 is connected to the second end of the seventh capacitor C7, the first end of the seventh capacitor C7 is grounded, the nineteenth pin of the network chip U1 is further connected to the second end of the ninth resistor R9, the first end of the ninth resistor R9 is connected to the CPU module (s3_pcie_rst# in fig. 8), the second end of the ninth resistor R9 is further connected to the second end of the tenth resistor R10, and the first end of the tenth resistor R10 is connected to the power supply (phy_dvdd33 in fig. 8). The nineteenth pin of the network chip U1 may be a reset signal for PCI Express.

The twentieth pin of the network chip U1 is connected with the CPU module. The twentieth pin of the network chip U1 may be an isolation pin.

The twenty-first pin of the network chip U1 is connected to the second end of the eleventh resistor R11, the first end of the eleventh resistor R11 is connected to the CPU module (phy_int_n in fig. 8), the second end of the eleventh resistor R11 is also connected to the second end of the twelfth resistor R12, and the first end of the twelfth resistor R12 is connected to the first end of the tenth resistor R10. The twenty-first pin of the network chip U1 described above may be used to activate the primary power supply and reference clock of the PCI Express slot.

The twenty eighth pin of the network chip U1 is connected to the CPU module (phy_xtl1 in fig. 8), and the twenty ninth pin of the network chip U1 is connected to the CPU module (phy_xtl2 in fig. 8). The twenty eighth pin and the twenty ninth pin of the network chip U1 described above may be used to input a reference clock.

The thirty-first pin of the network chip U1 is connected to the second end of the twelfth resistor R12, the first end of the twelfth resistor R12 is grounded, and the thirty-third pin of the network chip U1 is grounded. The thirty-first pin of the network chip U1 may be a reference pin.

The eleventh pin of the network chip U1 is connected to the CPU module (phy_avdd 33 in fig. 8), the thirty-second pin of the network chip U1 is connected to the eleventh pin of the network chip U1, and the twenty-third pin of the network chip U1 is connected to the CPU module (phy_dvdd 33 in fig. 8). The eleventh pin, the thirty-second pin, and the twenty-third pin of the network chip U1 may be power pins.

The twenty-fourth pin of the network chip U1 is connected to the first end of the eighth capacitor C8, the second end of the eighth capacitor C8 is grounded, the first end of the eighth capacitor C8 is further connected to the first end of the thirteenth resistor R13, the second end of the thirteenth resistor R13 is connected to the second end of the first inductor L1, the first end of the first inductor L1 is further connected to the first end of the eighth capacitor C8, the second end of the first inductor L1 is further connected to the eighth pin, the third pin, the twenty-second pin and the thirty-first pin of the network chip U1, the second end of the thirteenth resistor R13 is further connected to the first end of the ninth capacitor C9, the second end of the ninth capacitor C9 is further connected to the first end of the thirteenth capacitor C10, the second end of the tenth capacitor C10 is further connected to the second end of the ninth capacitor C9, the first end of the eleventh capacitor C11 is further connected to the first end of the eleventh capacitor C11, the second end of the eleventh capacitor C11 is further connected to the twelfth end of the twelfth capacitor C12, the twelfth end of the twelfth capacitor C13 is further connected to the twelfth end of the thirteenth capacitor C12.

In a specific implementation, since the network chip U1 is disposed inside the electronic device, but not on the patch cord 2, the IP address is not changed due to the change of the patch cord 2, thereby improving the security and reliability of the electronic device.

Further, referring to fig. 9, fig. 9 is a schematic circuit diagram of a transfer line 2 in a second embodiment of the electronic device according to the embodiment of the present utility model.

The pin definition of the miniRJ male head 22 is consistent with the pin definition of the miniRJ45 female seat 1, specifically, in the miniRJ male head 22, the pin A1 is gnd_3, the pin A2 is SSTXp1, the pin A3 is SSTXn, the pin A4 is vbus_2, the pin A5 is CC1, the pin A6 is Dp1_2, the pin A7 is Dn1_2, the pin A8 is SBU1, the pin A9 is vbus_4, the pin a10 is SSRXn2, the pin a11 is SSRXp2, and the pin a12 is gnd_4; the B1 pin is GND_2, the B2 pin is SSTXp2, the B3 pin is SSTXn2, the B4 pin is VBUS_3, the B5 pin is CC2, the B6 pin is Dp1_1, the B7 pin is Dn1_1, the B8 pin is SBU2, the B9 pin is VBUS_1, the B10 pin is SSRXn1, the B11 pin is SSRXp1, and the B12 pin is GND_1. Wherein, the A4 pin and the B9 pin are power supply pins, and the G1 pin, the A12 pin, the G2 pin, the B1 pin, the G3 pin, the B12 pin and the G4 pin of the miniRJ45 busbar 1 are grounding pins.

In some embodiments, if the A2 pin, A3 pin, B10 pin, and B11 pin of miniRJ/45 female holder 1 are floating, the A2 pin, A3 pin, B10 pin, and B11 pin of miniRJ male 22 are not set.

As shown in fig. 9, the A6 th pin of the miniRJ male head 22 is connected to the first pin of the RJ45 connection block 21 (phy_ TRXP0 in fig. 9), the A7 th pin of the miniRJ male head 22 is connected to the second pin of the RJ45 connection block 21 (phy_trxn0 in fig. 9), the a10 th pin of the miniRJ male head 22 is connected to the third pin of the RJ45 connection block 21 (phy_ TRXP1 in fig. 9), the a11 th pin of the miniRJ male head 22 is connected to the fourth pin of the RJ45 connection block 21 (phy_trx1 in fig. 9), the B2 nd pin of the miniRJ male head 22 is connected to the fifth pin of the RJ45 connection block 21 (phy_ TRXP2 in fig. 9), the B3 th pin of the miniRJ male head 22 is connected to the sixth pin of the RJ45 connection block 21 (phy_trx2 in fig. 9), the a11 th pin of the RJ45 male head 22 is connected to the fourth pin of the RJ45 connection block 21 (phy_trx1 in fig. 9), and the B6 th pin of the RJ45 male head 22 is connected to the eighth pin of the RJ45 connection block 21 (phy_trx25 2 in fig. 9).

The connection modes of the G1 pin, the A2 pin, the A3 pin, the A4 pin, the A5 pin, the A8 pin, the A9 pin, the a12 pin, the G2 pin, the G3 pin, the B1 pin, the B4 pin, the B5 pin, the B8 pin, the B9 pin, the B10 pin, the B11 pin, the B12 pin, and the G4 pin of the miniRJ male connector 22 refer to the connection modes of the corresponding pins of the miniRJ45 female connector 1, and are not described in detail herein.

In a specific implementation, the RJ45 connecting seat 21 is connected with an external RJ45 connector, and then the RJ45 connecting seat 21 is connected with the miniRJ male connector 22 through a cable, the miniRJ male connector 22 is connected with the miniRJ female connector 1 on the electronic device, so that network data signal transmission between the electronic device and an external network can be realized.

In the embodiment, the network chip U1 is arranged in the electronic equipment instead of on the patch cord 2, so that the IP address is not changed due to the change of the patch cord 2, and the safety and reliability of the electronic equipment are improved; meanwhile, the RJ45 connecting seat 21 is connected with an external RJ45 connector, the RJ45 connecting seat 21 is connected with the miniRJ public head 22 through a cable, the miniRJ public head 22 is connected with the miniRJ female seat 1 on the electronic equipment, and then network data signal transmission between the electronic equipment and an external network can be realized.

The foregoing description is only of the preferred embodiments of the present utility model, and is not intended to limit the scope of the utility model, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims

1. An electronic device is characterized in that the electronic device is provided with a miniRJ45 female seat, a first end of the miniRJ female seat is connected with an external RJ45 connector through an adapter wire, and a second end of the miniRJ female seat is connected with a CPU module;

the patch cord includes: an RJ45 connecting seat and miniRJ45 male heads;

2. The electronic device of claim 1, wherein the electronic device further comprises: the first resistor, the second resistor, the third resistor, the first capacitor and the second capacitor;

3. The electronic device of claim 2, wherein the electronic device further comprises: a fourth resistor;

4. The electronic device of claim 3, wherein the electronic device further comprises: an Ethernet module;

5. The electronic device of claim 4, wherein the ethernet module comprises: a network chip;

6. The electronic device of claim 5, wherein the electronic device further comprises: the fifth resistor, the sixth resistor and the seventh resistor are connected;

7. The electronic device of claim 4, wherein the pin definition of the miniRJ male head is consistent with the pin definition of the miniRJ female socket, the A6 th pin of the miniRJ male head is connected with the first pin of the RJ45 connection socket, the A7 th pin of the miniRJ male head is connected with the second pin of the RJ45 connection socket, the a10 th pin of the miniRJ male head is connected with the third pin of the RJ45 connection socket, the a11 th pin of the miniRJ male head is connected with the fourth pin of the RJ45 connection socket, the B2 nd pin of the miniRJ male head is connected with the fifth pin of the RJ45 connection socket, the B3 th pin of the miniRJ male head is connected with the sixth pin of the RJ45 connection socket, the B6 th pin of the miniRJ male head is connected with the seventh pin of the RJ45 connection socket, and the B7 th pin of the miniRJ male head is connected with the eighth pin of the RJ45 connection socket.

8. The electronic device of any of claims 1-7, wherein the miniRJ s 45 mount comprises: a terminal assembly and a female housing;

9. The electronic device of claim 8, wherein one of the inner wall of the female housing and the outer wall of the male housing is provided with a limit projection, and the other is correspondingly provided with a relief groove, and the groove is used for being matched and positioned with the limit projection.

10. The electronic device of claim 9, wherein a plurality of the limit bumps are provided, and the limit bumps are uniformly distributed on both sides of the terminal assembly;