CN220914221U - Semiconductor packaging structure - Google Patents

Abstract

A semiconductor package structure comprising a substrate including a chip region and a peripheral region surrounding the chip region, the substrate including opposed upper and lower surfaces, the upper surface of the chip region of the substrate having a plurality of first pads; the solder mask layer is positioned on the upper surface of the substrate, the solder mask layer on the chip area is provided with an opening, the opening exposes a plurality of first bonding pads, the solder mask layer on the peripheral area is provided with an exhaust port, the exhaust port is communicated with the opening, the exhaust port is used for exhausting air in the opening through the exhaust port when the semiconductor chip with the non-conductive film is attached on the surface of the chip area of the substrate, and the non-conductive film fills the opening. Air residue in the opening is prevented during mounting of the semiconductor chip, and generation of voids in the non-conductive film is prevented.

Description

Semiconductor packaging structure

Technical Field

The present disclosure relates to semiconductor packaging, and particularly to a semiconductor packaging structure.

Background

At present, the stacking welding of chips mainly adopts a hot-press bonding process (Thermal Compression Bonding, TCB), and the welding is carried out in situ under the synchronous action of pressure and temperature. Currently, the mainstream stacking process adopts a Thermal Compression Bonding (TCB) +non-conductive Film (NCF) method, wherein a non-conductive Film is pre-attached to the surface of a chip and covers the solder bumps on the surface of the chip, and in the soldering process, the non-conductive Film is filled between the chip and the substrate in a flowing manner, so that the influence of stress on the chip is buffered, and meanwhile, the solder bumps are protected.

Before soldering, a solder mask (Solder Mask, SR) is typically formed on the surface of the substrate, with openings therein exposing the pads on the substrate. When the chip with the non-conductive film is attached on the surface of the substrate and is contacted with the substrate under the action of pressure, air in the solder mask layer is wrapped in the chip, and the air is difficult to discharge. Although in the process, the non-conductive film in a molten state can flow through subsequent continuous pressurization, and air is extruded and discharged, the process requirement is high, pores caused by air residues are easy to occur, and the reliability of the chip is affected.

Disclosure of utility model

Some embodiments of the present utility model provide a semiconductor package structure, including:

A substrate including a chip region and a peripheral region surrounding the chip region, the substrate including opposite upper and lower surfaces, the upper surface of the chip region of the substrate having a plurality of first pads;

The solder mask layer is positioned on the upper surface of the substrate, the solder mask layer on the chip area is provided with an opening, the opening exposes a plurality of first bonding pads, the solder mask layer on the peripheral area is provided with an exhaust port, the exhaust port is communicated with the opening, the exhaust port is used for exhausting air in the opening through the exhaust port when the semiconductor chip with the non-conductive film is attached on the surface of the chip area of the substrate, and the non-conductive film fills the opening.

In some embodiments, the number of openings is at least one, the number of exhaust openings is at least one, and one or both ends of the openings are in communication with the respective exhaust openings.

In some embodiments, the opening includes a middle region and two end regions on opposite sides of the middle region, the middle region of the opening having a smaller size than the two end regions of the opening.

In some embodiments, the opening increases in size from the middle region to the two end regions in an arc.

In some embodiments, the opening increases in size stepwise from the middle region to the two end regions.

In some embodiments, the semiconductor chip has opposite functional sides and a backside, the functional sides of the semiconductor chip have bonding bumps thereon, and the non-conductive film is located on the functional sides of the semiconductor chip and covers the bonding bumps.

In some embodiments, the material of the non-conductive film is a thermally cured resin material.

In some embodiments, the lower surface of the substrate has a plurality of second pads, and the substrate has connection lines therein that electrically connect the respective first and second pads.

In some embodiments, the number of chip regions is at least one, and when the number of chip regions is greater than one, each of the chip region periphery has a peripheral region surrounding the chip region.

Other embodiments of the present utility model provide a semiconductor package structure, which includes:

A substrate including a chip region and a peripheral region surrounding the chip region, the substrate including opposite upper and lower surfaces, the upper surface of the chip region of the substrate having a plurality of first pads;

A solder mask layer positioned on the upper surface of the substrate, wherein the solder mask layer on the chip area is provided with an opening, the opening exposes a plurality of first bonding pads, the solder mask layer on the peripheral area is provided with an exhaust port, and the exhaust port is communicated with the opening;

And a semiconductor chip mounted on the chip area surface of the substrate and electrically connected to the first pad, the semiconductor chip and the substrate having a non-conductive film therebetween, the vent being configured to vent air in the opening through the vent when the semiconductor chip having the non-conductive film is mounted on the chip area surface of the substrate, the non-conductive film filling the opening.

The semiconductor structure provided by the embodiments of the utility model comprises a substrate, wherein the substrate comprises a chip area and a peripheral area surrounding the chip area, the substrate comprises an upper surface and a lower surface which are opposite, and the upper surface of the chip area of the substrate is provided with a plurality of first bonding pads; the solder mask layer is positioned on the upper surface of the substrate, the solder mask layer on the chip area is provided with an opening, the opening exposes a plurality of first bonding pads, the solder mask layer on the peripheral area is provided with an exhaust port, the exhaust port is communicated with the opening, the exhaust port is used for exhausting air in the opening through the exhaust port when the semiconductor chip with the non-conductive film is attached on the surface of the chip area of the substrate, and the non-conductive film fills the opening. When a semiconductor chip having a non-conductive film is mounted on the surface of a chip region of a substrate, since an exhaust port communicating with an opening in the solder resist layer on the chip region is also provided in the solder resist layer on the edge region, when the opening is filled with the non-conductive film in a molten state, air in the opening is exhausted from the exhaust port communicating with the opening when being pressed, thereby preventing air from remaining and preventing the generation of voids.

Drawings

FIGS. 1-2 are schematic diagrams illustrating a semiconductor package structure according to some embodiments of the utility model;

FIG. 3 is a schematic diagram illustrating a semiconductor package structure according to other embodiments of the present utility model;

FIG. 4 is a schematic diagram illustrating a semiconductor package structure according to other embodiments of the present utility model;

FIG. 5 is a schematic diagram illustrating a semiconductor package structure according to other embodiments of the present utility model;

Fig. 6 is a schematic structural diagram of a semiconductor package according to another embodiment of the utility model.

Detailed Description

The following describes the embodiments of the present utility model in detail with reference to the drawings. In describing embodiments of the present utility model in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the utility model. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

Some embodiments of the present utility model firstly provide a semiconductor package structure, referring to fig. 1 and 2, wherein fig. 1 is a schematic cross-sectional structure of fig. 2 along a cutting line AB, and the semiconductor package structure includes:

A substrate 100, the substrate 100 including a chip region 11 and a peripheral region 12 surrounding the chip region 11, the substrate 100 including opposite upper and lower surfaces, the upper surface of the chip region 11 of the substrate 100 having a plurality of first pads 101;

the solder mask 104 on the upper surface of the substrate 100 has an opening 105 in the solder mask 104 on the chip region 11, the opening 105 exposes the plurality of first pads 101, the solder mask 104 of the peripheral region 12 has an exhaust port 106 (refer to fig. 2), the exhaust port 106 communicates with the opening 105, and the exhaust port 106 is used for exhausting air in the opening 105 through the exhaust port 106 when a semiconductor chip having a non-conductive film is mounted on the surface of the chip region 11 of the substrate 100, and the non-conductive film fills the opening.

Specifically, the chip area 11 of the substrate 100 is used for mounting a semiconductor chip, and the periphery of the chip area 11 is a peripheral area 12 surrounding the chip area 11. In some embodiments, the number of the chip areas 11 on the substrate 100 is at least one, and may specifically be one or more (greater than or equal to 2). When the number of the chip regions 11 is 2 or more, the periphery of each of the chip regions 11 has one peripheral region 12 surrounding the chip region 11. The substrate 100 is illustrated in fig. 1 and 2 with only one chip area 11 and one peripheral area 12 as examples.

The upper surface of the chip region 11 of the substrate 100 has a plurality of first pads 101, and the first pads 101 are used for electrically connecting with the mounted semiconductor chip. In some embodiments, the lower surface of the substrate 100 may have a plurality of second pads 102, and the substrate 100 has a connection line 103 therein, where the connection line 103 electrically connects the respective first pads 101 and second pads 102, and the connection line 103 may include one or more of a metal line, a metal plug, a via connection structure, and a via connection structure. In some embodiments, the materials of the first pad 101, the second pad 102, and the connection line 103 are metals, and may specifically be one or several kinds of Al, cu, ag, au, pt, ni, ti, tiN, taN, ta, taC, taSiN, W, WN, WSi. In some embodiments, the substrate 100 may be one of a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate, a metal substrate, a Printed Circuit Board (PCB), or a flexible circuit board (FPC). In some embodiments, the substrate 100 may be a single layer board or a multi-layer board.

The upper surface of the substrate 100 also has a solder mask layer 104. The solder mask layer 104 is used for preventing circuit short circuit and non-soldering points from being stained caused by solder overflow during soldering, and can effectively prevent moisture and protect the circuit.

The solder mask 104 on the chip area 11 has an opening 105 therein, the opening 105 exposes the plurality of first pads 101, the solder bumps on the semiconductor chip are convenient to solder on the first pads 101 when the semiconductor chip is mounted, and the solder mask 104 of the peripheral area 12 has an exhaust port 106 (refer to fig. 2) therein, the exhaust port 106 being in communication with the opening 105. When the semiconductor chip is stacked on the upper surface of the substrate by means of a thermal compression bonding process (TCB) +a non-conductive Film (NCF), specifically, a semiconductor chip 200 (refer to fig. 6) is provided first, the semiconductor chip 200 having opposite functional surfaces and a back surface, the functional surface of the semiconductor chip 200 having a bonding bump 201 thereon, the functional surface of the semiconductor chip 200 further having a non-conductive Film 202 covering the bonding bump 201 thereon, the non-conductive Film 202 being attached to the functional surface of the semiconductor chip by a Film attaching process; next, the functional surface of the semiconductor chip 200 is directed to the upper surface of the substrate 100, and when the semiconductor chip 200 is mounted on the substrate 100, a pressure is applied to the back surface of the semiconductor chip 200 and the non-conductive film 202 is heated, the non-conductive film 202 becomes a molten state (becomes soft), the non-conductive film 202 flows and fills the opening 105 in the solder resist layer 104, and the bonding bump 201 on the semiconductor chip 200 is brought into contact with the first bonding pad 101 and bonded together; finally, curing is performed. When a semiconductor chip having a non-conductive film is mounted on the surface of the chip region 11 of the substrate 100, since the solder mask layer on the edge region 12 further has the vent port 106 communicating with the opening 105 in the solder mask layer on the chip region 11, when the opening 105 is filled with the non-conductive film 202 in a molten state, air in the opening 105 is discharged from the vent port 106 communicating with the opening when being pressed, thereby preventing air from remaining and preventing the generation of voids.

The material of the non-conductive film 202 is a resin material that becomes molten (flows) when heated, and is thermally cured. In some embodiments, the material of the non-conductive film 202 includes a thermally cured epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin.

In some embodiments, the functional surface of the semiconductor chip 200 further has pads thereon, which are connected to integrated circuits formed in the semiconductor chip 200, and bonding bumps are formed on the pads. In some embodiments, the solder bumps may be solder bumps or include metal bumps and solder bumps on the top surface of the metal bumps. In a specific embodiment, the material of the bonding pad is one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver, the material of the metal bump is one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver, and the material of the solder bump is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium or tin silver antimony.

With continued reference to fig. 1 and 2, the number of openings 105 is at least one, the number of exhaust ports 106 is at least one, and one or both ends of the openings 105 are in communication with the respective exhaust ports 106.

In a specific embodiment, the number of the openings 105 may be 2 or more, the number of the exhaust ports 106 may be also plural, the number of the exhaust ports 106 is greater than the number of the openings 105, and referring specifically to fig. 2, the number of the openings 105 is two, the number of the exhaust ports 106 is four, and two ends of each opening 105 are respectively communicated with one exhaust port 106.

In another specific embodiment, the number of the openings 105 is one, the number of the exhaust ports 106 is one or two, one end of one of the openings 105 is in communication with one of the exhaust ports 106, or both ends of one of the openings 105 are respectively in communication with one of the exhaust ports 106.

In another specific embodiment, the number of the openings 105 may be plural, and may be 2 or more, the number of the exhaust ports 106 may be plural, and the number of the exhaust ports 106 may be equal to or less than the number of the openings 105, and referring specifically to fig. 3, fig. 4, or fig. 5, the number of the openings 105 may be two, and the number of the exhaust ports 106 may be two, where two ends of each opening 105 are respectively connected to one exhaust port 106 located on the same side.

In some embodiments, the opening 105 includes a middle region and two end regions located at two sides of the middle region, and the size of the middle region of the opening 105 is smaller than the size of the two end regions of the opening, so that when the semiconductor chip 200 is mounted on the substrate 100 and soldered, the narrower middle region of the opening 105 can be filled with the non-conductive film 202, and the air in the opening 105 can be more easily extruded from the opening 105 to the exhaust port 106.

In some specific embodiments, referring to fig. 2 or 3, the opening 105 is gradually increased in size from the middle region to the two end regions.

In other specific embodiments, referring to fig. 4, the size of the opening 105 increases gradually from the middle area to the two end areas.

In other embodiments, referring to fig. 5, the size of the middle region of the opening 105 is equal to the size of the two end regions of the opening 105.

Still further embodiments of the present utility model provide a semiconductor package structure, referring to fig. 6, fig. 1 and fig. 2 in combination, including:

A substrate 100, the substrate 100 including a chip region 11 and a peripheral region 12 surrounding the chip region 11, the substrate 100 including opposite upper and lower surfaces, the upper surface of the chip region 11 of the substrate 100 having a plurality of first pads 101;

A solder mask 104 disposed on the upper surface of the substrate 100, wherein the solder mask 104 on the chip region 11 has an opening 105 therein, the opening 105 exposes a plurality of first pads 104, the solder mask 104 of the peripheral region 12 has an exhaust port 106 therein, and the exhaust port 106 communicates with the opening 105;

And a semiconductor chip 200 mounted on the surface of the chip region 11 of the substrate 100 and electrically connected to the first pad 101, wherein a non-conductive film 202 is provided between the semiconductor chip 200 and the substrate 100, and the vent 105 is configured to vent air in the opening 105 through the vent 106 when the semiconductor chip 200 having the non-conductive film 202 is mounted on the surface of the chip region 11 of the substrate 100, and the non-conductive film 202 fills the opening 105.

It should be noted that the terms "comprising" and "having" and variations thereof herein are intended to cover a non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, the embodiments of the present utility model and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present utility model. In the foregoing embodiments, each embodiment is mainly described for the differences from the other embodiments, and the same/similar parts between the embodiments need to be referred to (or referred to) each other.

Although the present utility model has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present utility model by using the methods and technical matters disclosed above without departing from the spirit and scope of the present utility model, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present utility model are within the scope of the technical matters of the present utility model.

Claims (10)

1. A semiconductor package structure, comprising:

A substrate including a chip region and a peripheral region surrounding the chip region, the substrate including opposite upper and lower surfaces, the upper surface of the chip region of the substrate having a plurality of first pads; the solder mask layer is positioned on the upper surface of the substrate, the solder mask layer on the chip area is provided with an opening, the opening exposes a plurality of first bonding pads, the solder mask layer on the peripheral area is provided with an exhaust port, the exhaust port is communicated with the opening, the exhaust port is used for exhausting air in the opening through the exhaust port when the semiconductor chip with the non-conductive film is attached on the surface of the chip area of the substrate, and the non-conductive film fills the opening.

2. The semiconductor package according to claim 1, wherein the number of the openings is at least one, the number of the exhaust ports is at least one, and one or both ends of the openings communicate with the corresponding exhaust ports.

3. The semiconductor package according to claim 1 or 2, wherein the opening includes a middle region and both end regions located on both sides of the middle region, and a size of the middle region of the opening is smaller than a size of the both end regions of the opening.

4. A semiconductor package according to claim 3, wherein the opening increases in size from the middle region to the end regions in an arc shape.

5. The semiconductor package according to claim 3, wherein the opening increases in size stepwise from the middle region to the end regions.

6. The semiconductor package according to claim 1, wherein the semiconductor chip has opposite functional surfaces and a back surface, the functional surfaces of the semiconductor chip have bonding bumps thereon, and the non-conductive film is located on the functional surfaces of the semiconductor chip and covers the bonding bumps.

7. The semiconductor package according to claim 1, wherein the material of the non-conductive film is a thermally cured resin material.

8. The semiconductor package according to claim 1, wherein the lower surface of the substrate has a plurality of second pads, and the substrate has connection lines therein electrically connecting the respective first and second pads.

9. The semiconductor package according to claim 1, wherein the number of the chip regions is at least one, and when the number of the chip regions is greater than one, each of the chip regions has a peripheral region surrounding the chip region.

10. A semiconductor package structure, comprising:

A substrate including a chip region and a peripheral region surrounding the chip region, the substrate including opposite upper and lower surfaces, the upper surface of the chip region of the substrate having a plurality of first pads; a solder mask layer positioned on the upper surface of the substrate, wherein the solder mask layer on the chip area is provided with an opening, the opening exposes a plurality of first bonding pads, the solder mask layer on the peripheral area is provided with an exhaust port, and the exhaust port is communicated with the opening;

And a semiconductor chip mounted on the chip area surface of the substrate and electrically connected to the first pad, the semiconductor chip and the substrate having a non-conductive film therebetween, the vent being configured to vent air in the opening through the vent when the semiconductor chip having the non-conductive film is mounted on the chip area surface of the substrate, the non-conductive film filling the opening.