CN220121820U

CN220121820U - Semiconductor packaging device

Info

Publication number: CN220121820U
Application number: CN202320143638.5U
Authority: CN
Inventors: 闵繁宇; 李铮鸿
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2023-01-16
Filing date: 2023-01-16
Publication date: 2023-12-01
Anticipated expiration: 2033-01-16

Abstract

The utility model provides a semiconductor packaging device, comprising: a first mold seal material and a second mold seal material; a first rewiring layer disposed between the first mold seal material and the second mold seal material; the first chip is buried in the first mold sealing material and is electrically connected with the first rewiring layer through a bonding wire. The semiconductor packaging device forms an ePo (embedded stacked package) structure, is an integral structure, has better rigidity and is beneficial to inhibiting warping. In addition, CTE matching can be performed during manufacturing by choice of materials, helping to reduce warpage. In addition, the ePO structure can realize better thinning effect. In addition, the utility model is connected by the bonding wire, and the IO (input output) density is higher.

Description

Semiconductor packaging device

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging device.

Background

The PoP (Package on Package) structure is a structure of stacking a plurality of packages, wherein each Package has one to a plurality of chips (Die) disposed on a Substrate (SBT), and the packages are connected by solder balls, so as to integrate into a high-density electronic component Package.

Referring to fig. 1, a current semiconductor package device with a PoP structure is shown, which includes a second package structure 12 and a first package structure 11 stacked thereon, wherein the first package structure 11 and the second package structure 12 are electrically and physically connected by solder balls 13, and an underfill 14 covering the solder balls 13 may be further filled in a gap between the first package structure 11 and the second package structure 12. In addition, the first package structure 11 and the second package structure 12 generally further include a solder resist layer (not shown in the drawings) disposed on the outer surface.

The packages in the PoP structure are from different manufacturers, and there is typically no particular consideration between the manufacturers as to whether the CTE (coefficient of thermal expansion ) of the materials are matched at the PoP. In the case that the CTE of the material is not considered in the previous stage, when stacking packages, the assembly factory may suffer from Warpage (warp) caused by CTE mismatch and soldering caused by the warp, for example, the first Package structure 11 and the second Package structure 12 may not be soldered to the second Package structure 12 well due to different distances between solder ball joints caused by Warpage.

Disclosure of Invention

The utility model provides a semiconductor packaging device which is used for solving the technical problems that a PoP structure is easy to warp after stacking due to the fact that CTE of each package cannot be considered in a front-end process.

In order to achieve the above purpose, the present utility model provides the following technical solutions: a semiconductor package apparatus comprising: a first mold seal material and a second mold seal material; a first rewiring layer disposed between the first mold seal material and the second mold seal material; the first chip is buried in the first mold sealing material and is electrically connected with the first rewiring layer through a first bonding wire.

In some alternative embodiments, the first chip is connected to the first rewiring layer by a first adhesive layer, the back side of the first chip facing the first rewiring layer.

In some alternative embodiments, the semiconductor package apparatus further includes a second chip stacked on the first chip, the second chip being buried in the first molding material.

In some alternative embodiments, the second chip is electrically connected to the first chip by a second bond wire.

In some alternative embodiments, the semiconductor packaging apparatus further includes: and the third chip is buried in the second mold sealing material and connected to the first rewiring layer through a second adhesive layer, and the back surface of the third chip faces the first rewiring layer.

In some alternative embodiments, the semiconductor packaging apparatus further includes: a fourth chip embedded in the second molding material and connected to the first rewiring layer through the second adhesive layer; the back of the fourth chip faces the first rewiring layer, the fourth chip and the third chip are arranged side by side, and the thickness of the fourth chip is different from that of the third chip.

In some alternative embodiments, the semiconductor packaging apparatus further includes: and a second redistribution layer provided on the other side of the second mold seal material with respect to the first redistribution layer.

In some alternative embodiments, the semiconductor packaging apparatus further includes: and the heat conduction layer is arranged on the other side of the first mold sealing material relative to the first rewiring layer.

In some alternative embodiments, the semiconductor packaging apparatus further includes: the hardness of the first mold seal material is greater than that of the second mold seal material.

In some alternative embodiments, the semiconductor packaging apparatus further includes: the size of the filler in the first mold seal material is larger than that of the filler in the second mold seal material.

In some alternative embodiments, the semiconductor packaging apparatus further includes: the active face of the first chip faces the first rewiring layer and is spaced apart from the first rewiring layer.

In some alternative embodiments, the semiconductor packaging apparatus further includes: the active surface of the third chip faces the first rewiring layer and is spaced apart from the first rewiring layer.

In order to solve the technical problems that the post-stacking warpage is easy to occur due to the fact that CTE of each package cannot be considered in a front-end process of a PoP structure, the utility model provides a semiconductor packaging device. According to the utility model, the first redistribution layer is arranged on the surface of a certain package (namely the second mold sealing material), and then another package (namely the first mold sealing material) is stacked on the first redistribution layer, and chips can be buried in the first mold sealing material and the second mold sealing material, so that an ePO (embedded Package on Package) structure is formed.

Compared with the PoP structure, the ePO structure of the utility model has no tin ball combined part, but is an integral structure, has better rigidity, contributes to inhibiting warping, and can not cause cracking problem even if the warping condition occurs because the structural strength of the first rewiring layer is much higher than that of the tin ball combined part.

In addition, the ePO structure of the utility model is a one-piece integral structure, and does not involve packaging from different factories, so CTE matching can be performed through material selection in the manufacturing process, material characteristic difference is reduced, warpage is reduced, and other problems such as welding and the like derived from CTE mismatch are solved.

In addition, the PoP structure comprises solder balls (thickness about 80 μm), and each package comprises a substrate (thickness about 200 μm-300 μm), which is large and difficult to thin, while the ePO structure of the present utility model uses a rewiring layer

The substrate and the tin balls are eliminated (the thickness is about 50 μm), the thickness is much smaller, and a better thinning effect can be realized.

In addition, the solder ball connection is adopted between the packages of the PoP structure, and poor welding or incapability of welding can be caused due to the warping condition, but in the ePo structure, the first die sealing material and the second die sealing material are connected through the first rewiring layer, and the first chip embedded in the first die sealing material is connected with the first rewiring layer through the bonding wire, so that the problem of welding, such as void problem, can be avoided, the electrical performance is better, and the IO (input output) density is higher.

In addition, the ePO structure reduces materials such as underfills, solder masks and the like, and reduces the types of materials, thereby being beneficial to reducing CTE mismatch and further inhibiting warpage and reducing the cost in terms of materials and manufacturing processes.

In addition, the ePO structure of the utility model is an integral structure, is light, thin, short and small, can realize more functions in one package, and has higher processing efficiency and higher productivity.

Drawings

Other features, objects and advantages of the present utility model will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

fig. 1 is a schematic view of a longitudinal sectional structure of a semiconductor package apparatus of the present utility model;

fig. 2 is a schematic longitudinal sectional structure of a semiconductor package apparatus 2a according to an embodiment of the present utility model;

FIG. 3A is an enlarged view of a portion of FIG. 2;

FIG. 3B is another enlarged partial view of FIG. 2;

fig. 4 is a schematic longitudinal sectional structure of a semiconductor package apparatus 4a according to an embodiment of the present utility model;

fig. 5 is a schematic longitudinal sectional structure of a semiconductor package apparatus 5a according to an embodiment of the present utility model;

fig. 6 is a schematic longitudinal sectional structure of a semiconductor package apparatus 6a according to an embodiment of the present utility model;

fig. 7 is a schematic longitudinal sectional structure of a semiconductor package apparatus 7a according to an embodiment of the present utility model;

fig. 8A-8J are schematic diagrams of steps in the manufacture of a semiconductor package apparatus according to one embodiment of the present utility model.

Reference numerals/symbol description:

11-a first package structure; 12-a second package structure; 13-tin balls; 14-underfill; 21-a first mold seal material; 22-a second molding material; 23-a first rewiring layer; 231-line pattern; 232-a dielectric layer; 233-connection pads; 24-a second redistribution layer; 25-an adhesive layer; 251-a first adhesive layer; 252-a second adhesive layer; 253-a third adhesive layer; 26-bonding wires; 261-a first bond wire; 262-a second bond wire; 27-conductive pillars; 28-bump; 29-solder balls; 30-packing; 31-a first chip; 32-a second chip; 33-a third chip; 34-fourth chip; 35-a heat conducting layer; 40-carrier plate.

Detailed Description

The following description of the embodiments of the present utility model will be given with reference to the accompanying drawings and examples, and it is easy for those skilled in the art to understand the technical problems and effects of the present utility model. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant utility model and are not limiting of the utility model. In addition, for convenience of description, only parts related to the relevant utility model are shown in the drawings.

It should be readily understood that the meanings of "on", "above" and "above" in the present utility model should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are only used for being matched with those described in the specification for understanding and reading, and are not intended to limit the applicable limitation of the present utility model, so that the present utility model has no technical significance, and any modification of structures, changes in proportions or adjustment of sizes, without affecting the efficacy and achievement of the present utility model, should still fall within the scope covered by the technical content disclosed in the present utility model. Also, the terms "upper", "first", "second", and "a" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the utility model for which the utility model may be practiced, but rather for relative changes or modifications without materially altering the technical context.

It should be further noted that, in the embodiment of the present utility model, the corresponding longitudinal section may be a section corresponding to a front view direction, the corresponding transverse section may be a section corresponding to a right view direction, and the corresponding horizontal section may be a section corresponding to an upper view direction.

In addition, the embodiments of the present utility model and the features in the embodiments may be combined with each other without collision. The utility model will be described in detail below with reference to the drawings in connection with embodiments.

Referring to fig. 2, fig. 2 is a schematic longitudinal sectional structure of a semiconductor package apparatus 2a according to an embodiment of the present utility model. As shown in fig. 2, a semiconductor package apparatus 2a of an embodiment of the present utility model includes:

a first molding material 21;

a second molding material 22 located below the first molding material 21;

a first rewiring layer 23 provided between the first mold seal material 21 and the second mold seal material 22; specifically, the first re-wiring layer 23 may be disposed on the second mold seal material 22, and the first mold seal material 21 may be disposed on the first re-wiring layer 23;

the first chip 31 is embedded in the first molding compound 21 and electrically connected to the first rewiring layer 23 through the bonding wire 26 (specifically, the first bonding wire 261).

In some alternative embodiments, the semiconductor package apparatus 2a further includes: the third chip 33 is buried in the second molding material 22.

Here, the first molding compound 21 and the first chip 31 embedded therein may constitute the first package structure 11, the second molding compound 22 and the third chip 33 embedded therein may constitute the second package structure 12, and the two may be electrically connected through the first redistribution layer 23 therebetween.

In some alternative embodiments, the first mold seal material 21 and the second mold seal material 22 may be made of the same or similar mold seal materials such that CTE (coefficient of thermal expansion) of the two are substantially equal, whereby CTE mismatch may be reduced, thereby suppressing warpage.

In some alternative embodiments, the first chip 31 may be connected to the first redistribution layer 23 through an adhesive layer 25 (specifically, the first adhesive layer 251), the back surface of the first chip 31 faces the first redistribution layer 23, and the active surface of the first chip 31 is far away from the first redistribution layer 23 and is electrically connected to the first redistribution layer 23 through the bonding wire 26.

In some alternative embodiments, the third chip 33 may be connected to the first redistribution layer 23 through an adhesive layer 25 (specifically, may be the second adhesive layer 252), where the back surface of the third chip 33 faces the first redistribution layer 23, and the active surface of the third chip 33 is far away from the first redistribution layer 23. Here, the first chip 31 and the third chip 33 are located on upper and lower sides of the first re-wiring layer 23, respectively.

In some alternative embodiments, the semiconductor package apparatus 2a further includes: the fourth chip 34 embedded in the second molding material 22, the fourth chip 34 may be disposed side by side with the third chip 33. Similar to the third chip 33, the fourth chip 34 may also be connected to the first redistribution layer 23 through an adhesive layer 25 (i.e. the second adhesive layer 252), and the back surface faces the first redistribution layer 23, and the active surface is far from the first redistribution layer 23. Here, the thicknesses of the fourth chip 34 and the third chip 33 may be the same or different.

In some alternative embodiments, the semiconductor package apparatus 2a further includes: the second redistribution layer 24 is provided on the other side of the second mold seal material 22 with respect to the first redistribution layer 23.

In some alternative embodiments, the active faces of the third chip 33 and the fourth chip 34 face the second redistribution layer 24 and may be electrically connected to the second redistribution layer 24 through the bumps 28.

In some alternative embodiments, the semiconductor package apparatus 2a further includes: and a conductive post 27 penetrating the second molding material 22, and electrically connecting the first redistribution layer 23 and the second redistribution layer 24 at both ends thereof. That is, the first and second redistribution layers 23 and 24 may be electrically connected through the conductive pillars 27. Here, the conductive pillars 27 include, but are not limited to, copper pillars (Cu pillars).

In some alternative embodiments, the semiconductor package apparatus 2a further includes: and solder balls 29 electrically connected to the other side of the second redistribution layer 24 with respect to the second molding material 22. The solder balls 29 are configured to connect to an external device, such as a PCB (Printed Circuit Board ). The solder balls 29 may be plural and distributed in an array, constituting a ball grid array.

In some alternative embodiments, the first chip 31 embedded in the first mold seal 21 may be a memory chip (memory die); the third chip 33 and the fourth chip 34 embedded in the second molding compound 22 may be logic chips (logic die), such as application processor (Application Processor) chips.

Referring to fig. 3A, fig. 3A is a partial enlarged view of fig. 2. As shown in fig. 3A, the first re-wiring layer 23 may include at least one layer of a line pattern 231 and a dielectric layer 232, and may further include a connection pad 233, and the connection pad 233 may be configured to connect the bonding wire 26. Here, the first re-wiring layer 23 is not required to be exposed to the outside for a long period of time in the process, and thus, the surface thereof is not required to be covered with a solder resist (e.g., green paint).

Referring to fig. 3B, fig. 3B is another enlarged partial view of fig. 2. As shown in fig. 3B, a filler (filler) 30 may be included in the second mold seal material 22. It is easily understood that the filler 30 may be included in the first molding material 21. In some alternative embodiments, the size of the filler 30 in the first mold seal material 21 is larger than the size of the filler 30 in the second mold seal material 22, so that the hardness of the first mold seal material 21 can be made larger than the hardness of the second mold seal material 22. Of course, in other embodiments, the hardness of the first mold seal material 21 may be made greater than the hardness of the second mold seal material 22 in other manners. Since the first mold seal material 21 is disposed above the second mold seal material 22 and the thickness of the first mold seal material 21 is generally thicker than the second mold seal material 22, warpage can be suppressed by making the hardness of the first mold seal material 21 larger than the second mold seal material 22.

With continued reference to fig. 3B, it can be seen that some of the filler 30 adjacent to the second redistribution layer 24 may have a ground surface that contacts the second redistribution layer 24 due to the grinding being shaved off a portion thereof, so that the bonding of the second mold seal 22 to the second redistribution layer 24 may be better.

For the convenience of understanding and implementation of the present utility model, the materials and dimensions of some elements in the semiconductor package apparatus 2a according to the embodiment of the present utility model are further described below:

in some alternative embodiments, the first mold seal material 21 and the second mold seal material 22 may be formed of various mold seal materials (Molding Compound). By way of example, the molding material may include Epoxy (Epoxy resin), filler (Filler), catalyst (Pigment), release Agent (Release Agent), flame Retardant (Flame Retardant), coupling Agent (Coupling Agent), hardener (Harden), low stress absorber (Low Stress Absorber), adhesion promoter (Adhesion Promoter), ion scavenger (Ion Trapping Agent), and the like. The molding material may be EMC (Epoxy molding compound, epoxy molding compound or epoxy molding compound), for example.

In some alternative embodiments, the adhesive layer 25 may be an organic substance (organic polymer material) in a liquid state or a film state, for example: non-Conductive Paste (NCP), non-Conductive Film (NCF), anisotropic Conductive Paste (ACP, anisotropic Conductive Paste), anisotropic Conductive Film (ACF, anisotropic Conductive Film), polyimide (PI), epoxy (Epoxy), resin (Resin), PP (pre reg, prePreg or semi-cured Resin, prePreg), ABF (Ajinomoto Build-up Film), glue, and the like.

In some alternative embodiments, dielectric layer 232 in first redistribution layer 23 and dielectric layer 24 include, but are not limited to, polyimide (PI).

In some alternative embodiments, the Bonding wires 26 are also referred to as Bonding wires, or Wire bonds, and include, but are not limited to, gold, silver, copper, aluminum, palladium, platinum, nickel, alloys thereof, and the like, for tightly Bonding with bond pads (bond pads) using heat, pressure, ultrasonic energy during a Wire Bonding process, and are typically used to make electrical connection between the chip and other components.

In some alternative embodiments, bump 28 is an electrical connection made of materials including, but not limited to, solder (holder), or Cu (copper), au (gold), ag (silver), al (aluminum), pd (palladium), pt (platinum), and Ni (nickel), and alloys thereof. The bump 28 may be, for example, a Gold bump (typically rectangular) or a solder bump (typically circular, copper-tin).

In some alternative embodiments, the solder ball (ball) 29 is a spherical electrical connector, the material of which includes but is not limited to solder (holder), and optionally, the surface may be provided with ACP/ACF (anisotropic conductive adhesive).

In some alternative embodiments, the thickness of both the first and second redistribution layers 23, 24 may be below 100 μm, for example around 50 μm. The thickness of each of the first mold seal material 21 and the second mold seal material 22 may be about several hundred micrometers (μm), and may be, for example, 300 μm to 500 μm or less than 300 μm or more than 500 μm, and for example, the thickness of the first mold seal material 21 is greater than the thickness of the second mold seal material 22.

As described above, the embodiment of the present utility model proposes a semiconductor package apparatus 2a. The first redistribution layer 23 is disposed on the surface of a certain package (for example, the second mold seal material 22), and another package (for example, the first mold seal material 21) is stacked on the first redistribution layer 23, and chips (for example, the first chip 31) can be embedded in the first mold seal material 21 and the second mold seal material 22, so that an ePoP (embedded Package on Package, embedded stacked package) structure can be formed.

Next, advantages of the semiconductor package apparatus 2a according to the embodiment of the present utility model are further described.

Compared with the PoP structure, the ePoP structure of the present utility model has no solder ball bonded portion, but is a unitary integral structure, has better rigidity, contributes to suppressing warpage, and does not cause cracking problems even if warpage occurs because the structural strength of the first rewiring layer 23 is much higher than that of the solder ball bonded portion.

In addition, the PoP structure includes solder balls having a thickness of about 80 μm, and each package includes a substrate having a thickness of about 200 μm to 300 μm, which is large in thickness and difficult to thin, whereas the ePoP structure of the present utility model, by using the first redistribution layer 23 (having a thickness of 100 μm or less, for example, about 50 μm), eliminates the substrate and solder balls, and has a much smaller thickness, thereby achieving a better thinning effect.

In addition, in the ePoP structure of the present utility model, the solder ball connection is adopted between the packages of the PoP structure, which may cause poor soldering or failure to solder due to the warpage condition, and the first mold seal material 21 and the second mold seal material 22 are connected through the first redistribution layer 23, and the first chip 31 embedded in the first mold seal material 21 is connected to the first redistribution layer 23 through the bonding wire 26, so that the problem in the soldering aspect, such as the void problem, may not occur, the electrical performance is better, and the IO (input output) density is higher.

In addition, the semiconductor package apparatus of the present utility model may employ a wafer level or panel level process, and for example, warpage may be controlled to be 1mm or less after a mold process (forming the first mold seal 21 and the second mold seal 22) and 200 μm or less after a reflow process.

In a further embodiment, the first mold seal material 21 and the second mold seal material 22 may be made of the same or similar mold seal materials, and the CTE thereof may be substantially equal, so that the CTE matching degree may be improved and warpage may be suppressed.

In a further embodiment, the second mold seal 22 may be further provided with a second redistribution layer 24 on the other side with respect to the first redistribution layer 23. Here, the first and second redistribution layers 23 and 24 can be made to oppose each other by design, further suppressing warpage.

In a further embodiment, the first redistribution layer 23 and the second redistribution layer 24 may be connected by the conductive pillars 27, so as to improve the IO density and connection reliability compared to the conventional PoP structure by solder ball connection.

In a further embodiment, the chips (including the first chip 31, the third chip 33 and the fourth chip 34) and the rewiring layer (including the first rewiring layer 23) may be connected by the adhesive layer 25, so that the connection firmness may be improved, and the chip offset may be avoided.

Referring to fig. 4, fig. 4 is a schematic longitudinal sectional structure of a semiconductor package apparatus 4a according to an embodiment of the present utility model. The semiconductor packaging apparatus 4a shown in fig. 4 is similar to the semiconductor packaging apparatus 2a shown in fig. 2, except that:

the semiconductor package apparatus 4a further includes a second chip 32 stacked on the first chip 31, the second chip 32 being buried in the first molding material 21.

Here, the second chip 32 may be a memory chip.

In some alternative embodiments, the second chip 32 may be connected to the first chip 31 by an adhesive layer 25 (specifically, the third adhesive layer 253 may be used), and the back surface of the second chip 32 faces the first chip 31, and the active surface is far away from the first chip 31.

In some alternative embodiments, the second chip 32 is electrically connected to the first chip 31 by bonding wires 26 (which may be specifically second bonding wires 262). Alternatively, the first chip 31 and the second chip 32 partially overlap in a top view, and a portion of the active surface of the first chip 31 is not covered by the second chip 32, and the active surface of the second chip 32 may be electrically connected to the active surface of the first chip 31 by using the bonding wires 26.

In still further embodiments, the second chip 32 stacked on the first chip 31 may be further stacked with other second chips 32, that is, the second chip 32 may have a plurality of layers and may be stacked, and from the top-most second chip 32, it is sequentially connected through the bonding wires 26.

Here, chips (including the first chip 31 and the second chip 32) embedded in the first molding compound 21 may be stacked, and the stacked chips may be connected by bonding wires 26, thereby contributing to a reduction in thickness and avoiding processing of TMV (through molding via, plastic molding through holes), thereby saving materials and time costs of the process.

Referring to fig. 5, fig. 5 is a schematic longitudinal sectional structure of a semiconductor package apparatus 5a according to an embodiment of the present utility model. The semiconductor packaging apparatus 5a shown in fig. 5 is similar to the semiconductor packaging apparatus 4a shown in fig. 4, except that:

the active surface of the first chip 31 of the semiconductor package apparatus 5a faces the first rewiring layer 23 and is spaced apart from the first rewiring layer 23.

Here, the active face of the first chip 31 may be electrically connected to the first rewiring layer 23 by the bonding wires 26. Alternatively, the bonding wires 26 electrically connected between the first chip 31 and the first re-wiring layer 23 may be disposed vertically, that is, may be perpendicular to the upper surface of the first re-wiring layer 23.

Referring to fig. 6, fig. 6 is a schematic longitudinal sectional structure of a semiconductor package apparatus 6a according to an embodiment of the present utility model. The semiconductor packaging apparatus 6a shown in fig. 6 is similar to the semiconductor packaging apparatus 2a shown in fig. 2, except that:

in the semiconductor package apparatus 6a, the active surface of the third chip 33 faces the first rewiring layer 23 and is spaced apart from the first rewiring layer 23.

Here, the third chip 33 may be electrically connected to the first redistribution layer 23 through the bump 28.

Here, the back surface of the third chip 33 may be connected to the second redistribution layer 24 through the adhesive layer 25.

In a further embodiment, the semiconductor package apparatus 6a may further include a fourth chip 34 disposed side by side with the third chip 33, the fourth chip 34 may be actively facing the first redistribution layer 23 and electrically connected to the first redistribution layer 23 through the bump 28, and the back surface is connected to the second redistribution layer 24 through the adhesive layer 25, and the thicknesses of the fourth chip 34 and the third chip 33 may be the same or different.

Referring to fig. 7, fig. 7 is a schematic longitudinal sectional structure of a semiconductor package apparatus 7a according to an embodiment of the present utility model. The semiconductor packaging apparatus 7a shown in fig. 7 is similar to the semiconductor packaging apparatus 2a shown in fig. 2, except that:

the semiconductor packaging apparatus 7a further includes: the heat conductive layer 35 is provided on the other side of the first molding material 21 with respect to the first redistribution layer 23.

In some alternative embodiments, the thermally conductive layer 35 may be a metal layer formed by Physical Vapor Deposition (PVD), plating, lamination, sputtering, tin spraying, and the like.

In some alternative embodiments, the heat conductive layer 35 may be thermally connected to the chips (including the first chip 31 and/or the second chip 32) embedded in the first molding compound 21 through some heat conductive structure/heat conductive material.

Here, by providing the heat conductive layer 35, the heat dissipation performance of the semiconductor package apparatus 7a can be increased.

Referring to fig. 8A-8J, fig. 8A-8J are schematic views of steps in the manufacture of a semiconductor package apparatus according to one embodiment of the present utility model. As shown in fig. 8A-8J, the manufacturing steps of the semiconductor package apparatus according to the embodiment of the present utility model may include:

as shown in fig. 8A, the first redistribution layer 23 is formed on a carrier 40. Here, the carrier plate 40 includes, but is not limited to, a glass carrier plate having a good surface flatness. Here, the step of forming the first re-wiring layer 23 may include: a dielectric layer is formed by coating or laminating, and a metal circuit pattern is formed on the dielectric layer by an additive method or a subtractive method. The addition method is to transfer the pattern by using photoresist through steps of photoetching, developing and the like, and then form a metal circuit pattern through electroplating. The subtractive method is to form a metal layer, then use photoresist to transfer the pattern through photolithography, development and other steps, and then etch to form the metal circuit pattern.

As shown in fig. 8B, the first chip 31 is bonded to the first re-wiring layer 23 through an adhesive layer 25, and the active surface (away from the first re-wiring layer) of the first chip 31 is electrically connected to the first re-wiring layer 23 by bonding wires 26. The first chip 31 may be, for example, a memory chip.

As shown in fig. 8C, a molding process is performed to form a first molding material 21 covering the first chip 31 and the bonding wires 26 on the first redistribution layer 23. The carrier 40 is then removed.

As shown in fig. 8D, the structure is shown after the carrier plate 40 is removed.

As shown in fig. 8E, at least one conductive pillar 27 is formed on the other side of the first redistribution layer 23 by a process such as placement or electroplating, and the third chip 33 and the fourth chip 34 with active surfaces facing upwards are bonded on the first redistribution layer 23 through the adhesive layer 25. The third chip 33 and the fourth chip 34 are lower than the conductive pillars 27, and bumps 28 may be disposed on the upward active surfaces of the third chip 33 and the fourth chip 34.

As shown in fig. 8F, a mold process is performed to form a second mold compound 22 covering the third chip 33, the fourth chip 34, and the conductive pillars 27 on the first redistribution layer 23.

As shown in fig. 8G, the upper surface of the second molding compound 22 is polished to expose the conductive posts 27 and the bumps 28 from the surface of the second molding compound 22.

As shown in fig. 8H, a second redistribution layer 24 is formed on the upper surface of the second molding material 22. Here, the step of forming the second re-wiring layer 24 may include: a dielectric layer is formed by coating or laminating, and a metal pattern is formed on the dielectric layer by an additive method or a subtractive method. Here, the second redistribution layer 24 is electrically connected to the first redistribution layer 23 through the conductive pillars 27, and is electrically connected to the third chip 33 and the fourth chip 34 through the bumps 28.

As shown in fig. 8I, the surface of the first molding material 21 is polished to be thinned.

As shown in fig. 8J, the solder balls 29 are provided on the second rewiring layer 24 by a ball mounting process, and the second rewiring layer 24 and the solder balls 29 are subjected to surface treatment. Here, the solder balls 29 are configured to connect to an external device. And cutting to obtain the independent semiconductor packaging device through a singulation process.

In the above, the process of the semiconductor package apparatus according to the embodiment of the present utility model is described.

It should be noted that, in the above-mentioned process steps, the first chip 31 to the fourth chip 34 can change the orientation of the active surface during the placement.

While the utility model has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to limit the utility model. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the utility model as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproduction and actual implementation in the present utility model due to variables in the manufacturing process, etc. Other embodiments of the utility model not specifically illustrated may exist. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present utility model. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Thus, the order and grouping of the operations is not a limitation of the present utility model unless specifically indicated herein.

Claims

1. A semiconductor package apparatus, comprising:

a first mold seal material and a second mold seal material;

a first rewiring layer disposed between the first mold seal material and the second mold seal material;

the first chip is buried in the first mold sealing material and is electrically connected with the first rewiring layer through a first bonding wire.

2. The semiconductor package apparatus according to claim 1, wherein the first chip is connected to the first rewiring layer through a first adhesive layer, and a back surface of the first chip faces the first rewiring layer.

3. The semiconductor package apparatus according to claim 1, further comprising a second chip stacked on the first chip, the second chip being buried in the first mold compound.

4. The semiconductor package apparatus according to claim 3, wherein the second chip is electrically connected to the first chip through a second bonding wire.

5. The semiconductor package apparatus according to claim 1, further comprising: and the third chip is buried in the second mold sealing material and connected to the first rewiring layer through a second adhesive layer, and the back surface of the third chip faces the first rewiring layer.

6. The semiconductor package apparatus according to claim 5, further comprising: a fourth chip embedded in the second molding material and connected to the first rewiring layer through the second adhesive layer; the back of the fourth chip faces the first rewiring layer, the fourth chip and the third chip are arranged side by side, and the thickness of the fourth chip is different from that of the third chip.

7. The semiconductor package apparatus according to claim 1, further comprising: and a second redistribution layer provided on the other side of the second mold seal material with respect to the first redistribution layer.

8. The semiconductor package apparatus according to claim 1, further comprising: and the heat conduction layer is arranged on the other side of the first mold sealing material relative to the first rewiring layer.

9. The semiconductor package apparatus according to claim 1, wherein the hardness of the first mold seal material is greater than the hardness of the second mold seal material.

10. The semiconductor package apparatus of claim 1, wherein an active face of the first chip faces the first redistribution layer and is spaced apart from the first redistribution layer.