CN219435243U - Dormancy wake-up circuit, motor controller and vehicle - Google Patents

Abstract

The utility model discloses a dormancy wakeup circuit, a motor controller and a vehicle. The sleep wake-up circuit comprises: the device comprises a first switch module, a second switch module, a hard wire dormancy wakeup module, a delay power-down module, a power-down detection module and a control module; the first switch module is connected in series between the controlled power line and the controlled load, and the second switch module is used for controlling the first switch module; the hard wire dormancy wakeup module is used for controlling the second switch module according to the hard wire dormancy wakeup signal; the power-down detection module is used for detecting whether the hard wire dormancy wakeup module is powered down or not; the control module is used for controlling the delay power-down module to delay power-down after detecting that the hard wire dormancy wakeup module is powered down. The embodiment of the utility model provides a power-down delay function for hard-wire dormancy, thereby perfecting the function of a dormancy awakening circuit.

Description

Dormancy wake-up circuit, motor controller and vehicle

Technical Field

The utility model relates to the technical field of automobile electronics, in particular to a dormancy wakeup circuit, a motor controller and a vehicle.

Background

With the development of automotive electronics, low power consumption of the automotive electronics is required, and therefore, a sleep wake-up circuit is generally adopted, and when the vehicle is stopped, the corresponding controller is in a sleep state to reduce power consumption. However, the existing sleep wake-up circuit has a defect that when hard wire sleep is adopted, the later stage load is powered down instantaneously, so that the later stage controller cannot store data.

Disclosure of Invention

The utility model provides a dormancy wakeup circuit, a motor controller and a vehicle, which are used for providing a power-down delay function for hard wire dormancy so as to perfect the function of the dormancy wakeup circuit.

According to an aspect of the present utility model, there is provided a sleep wakeup circuit including:

the first switch module is connected in series between the controlled power line and the controlled load;

the second switch module is electrically connected with the first switch module; the second switch module is used for controlling the first switch module;

the hard wire dormancy wakeup module and the delay power-down module are electrically connected with the second switch module; the hard wire dormancy wakeup module is used for controlling the second switch module according to a hard wire dormancy wakeup signal;

the power failure detection module is electrically connected with the hard wire dormancy wakeup module; the power-down detection module is used for detecting whether the hard wire dormancy wakeup module is powered down or not;

the control module is electrically connected with the power-down detection module and the delay power-down module; and the control module is used for controlling the power-down delay module to delay power down after detecting the power down of the hard wire dormancy wakeup module.

Optionally, the power failure detection module includes:

the control electrode of the first electronic switching tube is electrically connected with the hard wire dormancy awakening module, the first electrode of the first electronic switching tube is connected with a pull-up voltage, and the second electrode of the first electronic switching tube is connected with a pull-down voltage;

the first voltage dividing resistor unit is electrically connected with the control electrode and the second electrode of the first electronic switching tube; the first voltage dividing resistor unit is used for protecting the voltage of the first electronic switching tube;

the first current limiting unit is connected in series between the first pole of the first electronic switching tube and the pull-up voltage.

Optionally, the first electronic switch tube is a triode;

and/or, the first voltage dividing resistance unit includes: the first resistor is connected in series between the control electrode of the first electronic switch tube and the hard wire dormancy wakeup module; the second resistor is connected between the control electrode and the second electrode of the first electronic switching tube;

and/or the first current limiting unit comprises a third resistor, and the third resistor is connected in series between the first pole of the first electronic switching tube and the pull-up voltage.

Optionally, the hard-wire sleep wake module includes: a first unidirectional conduction unit; the first end of the first unidirectional conduction unit is connected with the hard wire dormancy wakeup signal, and the second end of the first unidirectional conduction unit is electrically connected with the second switch module;

and/or, the delay power down module comprises: the second current limiting unit and the second unidirectional conduction unit; the second current limiting unit and the second unidirectional conduction unit are connected in series between the control module and the second switch module.

Optionally, the sleep wake-up circuit further comprises:

the communication dormancy wakeup module is electrically connected with the second switch module; the communication dormancy wakeup module is used for controlling the second switch module according to the communication dormancy wakeup signal.

Optionally, the communication dormancy wakeup module includes: a communication chip and a third unidirectional conduction unit; the first pin of the communication chip is connected to the communication dormancy awakening signal, the second pin of the communication chip is electrically connected with the control module, the third pin of the communication chip is electrically connected with the first end of the third unidirectional conduction unit, and the second end of the third unidirectional conduction unit is electrically connected with the second switch module.

Optionally, the first switch module includes:

the control electrode of the second electronic switching tube is electrically connected with the second switching module, the first electrode of the second electronic switching tube is electrically connected with the controlled power line, and the second electrode of the second electronic switching tube is electrically connected with the controlled load;

the second voltage-dividing resistor unit is electrically connected with the second electronic switch tube; the second voltage-dividing resistor unit is used for protecting the voltage of the second electronic switching tube.

Optionally, the second switch module includes:

the control electrode of the third electronic switching tube is electrically connected to the hard wire dormancy awakening module, the second electrode of the third electronic switching tube is electrically connected with the first switching module, and the first electrode of the third electronic switching tube is grounded;

the third voltage dividing resistor unit is electrically connected with the third electronic switch tube; the third voltage dividing resistor unit is used for protecting the voltage of the third electronic switching tube.

According to another aspect of the present utility model, there is provided a motor controller comprising a sleep wakeup circuit according to any embodiment of the present utility model;

the controlled power line is an input power line of the motor controller, and the controlled load is a load of the motor controller.

According to another aspect of the present utility model there is provided a vehicle comprising an electric motor and a motor controller according to any embodiment of the present utility model for controlling the operation of the electric motor.

The embodiment of the utility model is provided with the power-down detection module and the power-down delay module in the dormancy wakeup circuit, and is matched with the hard wire dormancy wakeup module for use. The power-down detection module can transmit a power-down signal to the control module when the hard-wire dormancy wakeup signal is powered down; and the control module controls the high and low levels of the delay power-down module. The sleep time of the controlled device can be delayed by setting the sleep time, and data or other processing can be stored in the delay time. Therefore, the embodiment of the utility model provides a power-down delay function for hard-line dormancy, thereby perfecting the function of a dormancy wakeup circuit.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic circuit diagram of a sleep wake-up circuit according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of another sleep wake-up circuit according to an embodiment of the present utility model;

fig. 3 is a schematic circuit diagram of a sleep wake-up circuit according to another embodiment of the present utility model.

Detailed Description

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the utility model provides a dormancy wakeup circuit, which is suitable for a motor controller, in particular to a motor controller in a vehicle. Fig. 1 is a schematic circuit diagram of a sleep wake-up circuit according to an embodiment of the present utility model. Referring to fig. 1, the sleep wakeup circuit includes:

the first switch module 100, the first switch module 100 is connected in series between the controlled power line and the controlled load RL;

the second switch module 200 is electrically connected with the first switch module 100; the second switch module 200 is used for controlling the first switch module 100;

the hard wire dormancy wakeup module 300 and the delay power down module 400 are electrically connected with the second switch module 200; the hard-wire sleep wake-up module 300 is configured to control the second switch module 200 according to the hard-wire sleep wake-up signal KL 15;

the power-down detection module 500 is electrically connected with the hard-wire dormancy wakeup module 300; the power-down detection module 500 is configured to detect whether the hard-wired sleep wake-up module 300 is powered down;

the control module 600 is electrically connected with the power-down detection module 500 and is electrically connected with the delayed power-down module 400; the control module 600 is configured to control the delay power down module 400 to delay power down after detecting that the hard-wired sleep wakeup module 300 is powered down.

Specifically, taking a motor controller as an example, a controlled power line is an input power line of the motor controller, and for a passenger car, the voltage of the controlled power line is generally set to 9V to 36V. The controlled load RL is the load of the motor controller, i.e. all loads of the motor controller are equivalent to the controlled load RL. One end of the controlled load RL is connected to the positive pole KL30 of the controlled power line through the first switch module 100, and the other end of the controlled load is connected to the negative pole KL31 of the controlled power line.

The hard-wire sleep wakeup signal KL15 is a signal for performing sleep wakeup control through a hard wire pair, and still takes a motor controller of a vehicle as an example, the hard-wire sleep wakeup signal KL15 is a whole vehicle 'key' signal.

The principle of operation of the sleep wakeup circuit is, for example, as follows:

the hard-wire sleep wakeup signal KL15 is typically active high, i.e. enabled high. When the hard wire sleep wakeup signal KL15 is at a high level, the hard wire sleep wakeup module 300 transmits the high level to the second switch module 200, and the second switch module 200 is turned on and outputs a low level to control the first switch module 100 to be turned on. When the first switch module 100 is turned on, the motor controller is in an awake state, and the controlled load RL has a power input.

When the hard-wire sleep wake-up signal KL15 is at a low level, the hard-wire sleep wake-up module 300 cannot control the second switch module 200 to be turned on, and if the setting of the power-down module 400 is not delayed, the second switch module 200 outputs a high level to control the first switch module 100 to be turned off. When the first switch module 100 is turned off, the motor controller is in a dormant state, the controlled load RL has no power input, namely, the power of the motor controller is cut off, and when the motor controller is turned off, the dormant power consumption of the whole motor controller is all from the first switch module 100 and other control chips, so that the dormant power consumption can be extremely low.

However, in the embodiment of the present utility model, the power-down detection module 500 and the delay power-down module 400 are provided, when the hard-wire sleep wake-up signal KL15 is at a low level, the power-down detection module 500 outputs a low level to the pin GPIO2 of the control module 600, and the control module 600 receives the low level of the pin GPIO2, which indicates that the hard-wire sleep wake-up signal KL15 has been disconnected. At this time, the power-down delay control pin PowerON of the control module 600 outputs a high level, which is similar to the hard wire sleep wake-up signal KL15 outputting a high level, and the power-down delay control pin PowerON transmits the high level to the delay power-down module 400, and the delay power-down module 400 transmits the high level to the second switch module 200, and the second switch module 200 is turned on and outputs a low level to control the first switch module 100 to be turned on. When the first switch module 100 is turned on, the motor controller is in an awake state, and the controlled load RL has a power input. The power down delay control pin PowerEN remains high for a period of time (the period of time may be set by the control module 600, for example, 2 s), the motor controller saves and processes data, and after the data processing is finished, the control module 600 pulls down the power down delay control pin PowerEN to control the motor controller to sleep.

In the embodiment of the utility model, a power-down detection module 500 and a power-down delay module 400 are arranged in a dormancy wakeup circuit and are matched with a hard wire dormancy wakeup module 300 for use. The power-down detection module 500 can transmit a power-down signal to the control module 600 when the hard-wire sleep wake-up signal KL15 is powered down; and the control module 600 controls the high and low levels of the delay power down module 400. The sleep time of the controlled device can be delayed by setting the sleep time, and data or other processing can be stored in the delay time. Therefore, the embodiment of the utility model provides a power-down delay function for hard-line dormancy, thereby perfecting the function of a dormancy wakeup circuit.

On the basis of the above embodiments, the embodiments of the present utility model are also compatible with the communication dormancy wakeup function. With continued reference to fig. 1, in one embodiment of the utility model, the sleep wakeup circuit optionally further includes a communication sleep wakeup module 700. The communication dormancy wakeup module 700 is electrically connected with the second switch module 200; the communication dormancy wakeup module 700 is configured to control the second switch module 200 according to the communication dormancy wakeup signal. Optionally, the communication dormancy wakeup module 700 is further electrically connected to the control module 600, and the control module 600 is configured to perform software configuration on the communication dormancy wakeup module 700, so that the communication dormancy wakeup module 700 implements a power-down delay function. Illustratively, the pin GPIO1 of the control module 600 is in data communication with the communication sleep wakeup module 700.

Specifically, taking a motor controller as an example, the working principle of the sleep wake-up circuit is as follows:

the communication dormancy wakeup module 700 has a function of interacting with the whole vehicle data, and the communication dormancy wakeup signal is a CAN communication message. When the communication dormancy wakeup module 700 receives the whole vehicle CAN communication message, a high level CAN be output to the second switch module 200, the second switch module 200 is conducted and a low level is output, and the first switch module 100 is controlled to be conducted. When the first switch module 100 is turned on, the motor controller is in an awake state, and the controlled load RL has a power input. When the CAN communication message is powered down, the communication dormancy wakeup module 700 outputs a high level to maintain the motor controller in a wakeup state, and controls the motor controller to sleep after a period of time.

When the hard wire sleep wakeup signal KL15 is at a high level, the hard wire sleep wakeup module 300 transmits the high level to the second switch module 200, and the second switch module 200 is turned on and outputs a low level to control the first switch module 100 to be turned on. When the first switch module 100 is turned on, the motor controller is in an awake state, and the controlled load RL has a power input. When the hard wire sleep wake-up signal KL15 turns to a low level, the power-down detection module 500 outputs a low level to the pin GPIO2 of the control module 600, and the control module 600 receives the low level of the pin GPIO2, which indicates that the hard wire sleep wake-up signal KL15 has been disconnected. At this time, the delayed power down module 400 outputs a high level to maintain the motor controller in a wake-up state, and controls the motor controller to sleep after a period of time.

Therefore, the embodiment of the utility model CAN be compatible with two modes of the hard wire dormancy wakeup signal KL15 and the CAN communication signal dormancy wakeup, and CAN directly control the first switch module 100 to disconnect the power supply in the dormancy state, so that the dormancy wakeup circuit has extremely low dormancy power consumption. In addition, the embodiment of the utility model can delay the sleep time of the controlled equipment when the hard wire sleep wake-up signal KL15 is powered down, and can save data or other processing in the delay time.

With continued reference to fig. 1, the sleep wake-up circuit may further include an electrical control low-voltage connector 800, where the electrical control low-voltage connector 800 is used for signal switching, for example, a power supply of the whole vehicle (including a positive pole KL30 of a controlled power line and a negative pole KL31 of the controlled power line), a hard wire sleep wake-up signal KL15 and a CAN communication signal are all connected by the electrical control low-voltage connector 800.

With continued reference to FIG. 1, the control module 600 is optionally a micro control unit (Microcontroller Unit; MCU), such as a single chip microcomputer or the like.

Fig. 2 is a schematic circuit diagram of another sleep wake-up circuit according to an embodiment of the present utility model. Based on the above embodiments, the specific arrangement manner of the power failure detection module 500 is further described in the embodiments of the present utility model. Referring to fig. 2, in one embodiment of the present utility model, optionally, the power down detection module 500 includes:

the control electrode of the first electronic switch tube Q1 is electrically connected with the hard wire dormancy awakening module 300, the first electrode of the first electronic switch tube Q1 is connected with the pull-up voltage VCC, and the second electrode of the first electronic switch tube Q1 is connected with the pull-down voltage. The first electronic switching tube Q1 is an NPN transistor, a base electrode of the NPN transistor is electrically connected to the hard wire sleep wake-up module 300, a collector electrode of the NPN transistor is connected to the pull-up voltage VCC, and an emitter electrode of the first electronic switching tube Q1 is grounded.

The first voltage dividing resistor unit 510 is electrically connected with the control electrode and the second electrode of the first electronic switching tube Q1; the first voltage dividing resistor unit 510 is used for protecting the first electronic switching tube Q1 from voltage. Illustratively, the first voltage dividing resistor unit 510 includes a first resistor R1 and a second resistor R2, the first resistor R1 is connected in series between the base of the triode and the hard-wire sleep wakeup module 300; the second resistor R2 is connected between the base and emitter of the transistor. The first resistor R1 is a current limiting resistor of the triode, and the second resistor R2 is a lower bias resistor of the triode.

The first current limiting unit 520 is connected in series between the first pole of the first electronic switching tube Q1 and the pull-up voltage. The first current limiting unit 520 includes a third resistor R3, the third resistor R3 is connected in series between the collector and the pull-up voltage VCC of the triode, and the third resistor R3 is a current limiting resistor between the collector and the emitter of the triode.

The power-down detection module 500 is exemplified by the principle that when the hard-wire sleep wake-up signal KL15 is at a low level, the triode is turned on, the collector of the triode outputs a low level to the pin GPIO2 of the control module 600, and the control module 600 receives the low level of the pin GPIO2, which indicates that the hard-wire sleep wake-up signal KL15 has been turned off.

When the hard-wire sleep wake-up signal KL15 is at a high level, the triode is turned off, the collector of the triode outputs a high level to the pin GPIO2 of the control module 600, and the control module 600 receives the high level of the pin GPIO2, which indicates that the hard-wire sleep wake-up signal KL15 is in a wake-up state.

The power failure detection module 500 provided by the embodiment of the utility model realizes the function of power failure detection of the hard wire dormancy wakeup signal KL15 by a simple circuit, and has lower cost and easy realization.

Fig. 3 is a schematic circuit diagram of a sleep wake-up circuit according to another embodiment of the present utility model. Based on the above embodiments, the embodiments of the present utility model further describe a specific arrangement manner of other modules of the sleep wakeup circuit.

With continued reference to fig. 3, in one embodiment of the present utility model, optionally, the hard-wired sleep wakeup module 300 includes a first unidirectional conductive element; the first end of the first unidirectional conduction unit is connected to the hard wire dormancy wakeup signal KL15, and the second end of the first unidirectional conduction unit is electrically connected with the second switch module 200. Illustratively, the first unidirectional conducting unit includes a diode D1, an anode of the diode D1 is connected to the hard-wire sleep wake-up signal KL15, and a cathode of the diode D1 is electrically connected to the second switch module 200. The diode D1 has a unidirectional conduction function, and only allows the high level of the hard wire sleep wakeup signal KL15 to be conducted, so that the communication sleep wakeup module 700 and the delay power-down module 400 can be prevented from affecting the hard wire sleep wakeup signal KL15.

With continued reference to fig. 3, in one embodiment of the present utility model, optionally, the delayed power down module 400 includes a second current limiting unit 410 and a second unidirectional conductive unit 420; the second current limiting unit 410 and the second unidirectional current conducting unit 420 are connected in series between the control module 600 and the second switching module 200. Illustratively, the second current limiting unit 410 includes a resistor R4 and the second unidirectional current conducting unit 420 includes a diode D2. The diode D2 has a unidirectional conduction function, and only allows the high level output by the power-down delay control pin PowerON to be conducted, so that the communication dormancy wakeup module 700 and the hard wire dormancy wakeup module 300 can be prevented from influencing the power-down delay control pin PowerON signal.

With continued reference to fig. 3, in one embodiment of the utility model, optionally the communication sleep wakeup module 700 includes: a communication chip 710 and a third unidirectional conductive unit; a first pin of the communication chip 710 is connected to a communication sleep wake-up signal (e.g., CAN communication), a second pin of the communication chip 710 is electrically connected to the control module 600 (e.g., pin GPIO 1), a third pin of the communication chip 710 is electrically connected to a first end of a third unidirectional conduction unit, and a second end of the third unidirectional conduction unit is electrically connected to the second switch module 200. Illustratively, the communication chip 710 is a CAN chip, and the type of the CAN chip is not limited in the embodiments of the present utility model. When the CAN communication message is received, the third pin (INH pin) corresponding to the communication chip 710 outputs a high level, and when the CAN communication message is not sent by the whole car, the third pin (INH pin) corresponding to the CAN communication message delays outputting a low level. The third unidirectional conduction unit includes a diode D3, where the diode D3 has a unidirectional conduction function, and only allows the high level conduction of the third pin (INH pin), so as to prevent the hard wire sleep wakeup module 300 and the delay power-down module 400 from affecting the communication sleep wakeup module 700.

Therefore, the diode D1, the diode D2 and the diode D3 act as an or gate, the diode D1 only allows the high level conduction of the hard-wire sleep wakeup signal KL15, the diode D2 only allows the high level conduction of the power on output by the power off delay control pin PowerON, and the diode D3 only allows the high level conduction of the third pin (INH pin), thereby avoiding the mutual interference between the sleep wakeup signals.

With continued reference to fig. 3, in one embodiment of the utility model, optionally the first switch module 100 comprises:

the control electrode of the second electronic switching tube Q2 is electrically connected with the second switching module 200, the first electrode of the second electronic switching tube Q2 is electrically connected with the controlled power line, and the second electrode of the second electronic switching tube Q2 is electrically connected with the controlled load RL. Illustratively, the second electronic switching tube Q2 includes a PMOS tube, a gate of the PMOS tube is electrically connected to the second switching module 200, a source of the PMOS tube is electrically connected to the controlled power line, and a drain of the PMOS tube is electrically connected to the controlled load RL.

The second voltage-dividing resistor unit 110, the second voltage-dividing resistor unit 110 is connected with the second electronic switching tube Q2 electrically; the second voltage-dividing resistor unit 110 is used for voltage protection of the second electronic switching tube Q2. The second voltage-dividing resistor unit 110 includes a resistor R5 and a resistor R6, the resistor R1 is connected between the gate and the source of the PMOS transistor, and the second resistor R2 is connected in series between the gate of the PMOS transistor and the second switch module 200. The resistors R5 and R6 form resistor voltage division, and when the PMOS tube is conducted, the voltage at the two ends of the grid electrode and the source electrode of the PMOS tube is ensured to be smaller than the Vgs maximum voltage of the PMOS tube.

The working principle of the first switch module 100 is that when the second switch module 200 outputs a low level, the PMOS tube is conducted, and the motor controller wakes up; when the second switch module 200 outputs a high level, the PMOS tube is closed and the motor controller is dormant. The embodiment of the utility model is arranged in such a way that the circuit structure of the first switch module 100 is simple, the work is stable, and the implementation is easy.

With continued reference to fig. 3, in one embodiment of the utility model, optionally, the second switch module 200 includes:

the control electrode of the third electronic switch tube Q3 is electrically connected to the connection point of the hard wire dormancy wakeup module 300 and the communication dormancy wakeup module 700, the second electrode of the third electronic switch tube Q3 is electrically connected to the first switch module 100, and the first electrode of the third electronic switch tube Q3 is grounded. The third electronic switch Q3 is an NMOS transistor, a gate of the NMOS transistor is electrically connected to a connection point of the hard-wire sleep wake-up module 300, the power-down delay module 400 and the communication sleep wake-up module 700, a source of the NMOS transistor is grounded, and a drain of the NMOS transistor is electrically connected to the first switch module 100.

The third voltage dividing resistor unit 210, the third voltage dividing resistor unit 210 is electrically connected with the third electronic switching tube Q3; the third voltage dividing resistor unit 210 is used for protecting the third electronic switch Q3 from voltage. The third voltage dividing resistor unit 210 includes a resistor R7 and a resistor R8, the resistor R7 is connected in series between the gate and the connection point of the NMOS transistor, the resistor R8 is connected between the gate and the source of the NMOS transistor, that is, the resistor R8 is connected between the gate and the ground of the NMOS transistor. The power-down delay module 400 is directly electrically connected to the gate of the NMOS transistor. This is because the voltage of the CAN communication signal and the hard wire sleep wakeup signal KL15 is relatively large, and the third voltage dividing resistance unit 210 (including the resistor R7 and the resistor R8) is provided to divide the large voltage when transmitting to the rear stage circuit, and then transmitted to the rear stage third electronic switching tube Q3 (including the NMOS tube), thereby preventing damage to the rear stage electronic switch.

The working principle of the second switch module 200 is that when the connection point of the hard wire dormancy wakeup module 300, the delay power-down module 400 and the communication dormancy wakeup module 700 is at a high level, the NMOS tube is conducted, and a low level is output to the PMOS tube; when the connection point of the hard wire sleep wakeup module 300, the delay power down module 400 and the communication sleep wakeup module 700 is at a low level, the NMOS tube is closed, and a high level is output to the PMOS tube. The embodiment of the utility model is arranged in such a way that the circuit structure of the second switch module 200 is simple, the work is stable, and the implementation is easy.

With continued reference to fig. 3, on the basis of the above embodiments, the working principle of the sleep wakeup circuit is as follows:

when the hard wire sleep wake-up signal KL15 is at a high level, the diode D1 transmits the high level to the gate of the third electronic switching tube Q3 (NMOS tube), and the third electronic switching tube Q2 (NMOS tube) is turned on and outputs a low level to control the second electronic switching tube Q2 (PMOS tube) to be turned on. When the second electronic switching tube Q2 (PMOS tube) is conducted, the motor controller is in an awakening state, and the controlled load RL has power input. Meanwhile, the high level of the hard-wire dormancy wakeup signal KL15 controls the first electronic switch tube Q1 (triode) to be turned off, the collector electrode of the first electronic switch tube Q1 (triode) outputs the high level to the pin GPIO2 of the control module 600, and the control module 600 receives the high level of the pin GPIO2 to indicate that the hard-wire dormancy wakeup signal KL15 is in a wakeup state, and does not start the power-down delay control pin PowerON.

When the hard-wire sleep wake-up signal KL15 is at a low level, the diode D1 no longer outputs a high level, and the third electronic switching tube Q3 (NMOS tube) cannot be controlled to be continuously turned on. Meanwhile, the low-level first electronic switch tube Q1 (triode) of the hard-wire sleep wake-up signal KL15 is turned on, the collector of the first electronic switch tube Q1 (triode) outputs a low level to the pin GPIO2 of the control module 600, the control module 600 receives the low level of the pin GPIO2, which indicates that the hard-wire sleep wake-up signal KL15 is already turned off, and then the power-down delay control pin PowerON is started to output a high level. The diode D2 transmits the high level to the gate of the third electronic switching tube Q3 (NMOS tube), the third electronic switching tube Q2 (NMOS tube) is turned on and outputs the low level, and the second electronic switching tube Q2 (PMOS tube) is controlled to continue to be turned on, so that the motor controller continues to be in the awake state and is maintained for a period of time (the period of time can be set by the control module 600, for example, 2 s), and the motor controller stores and processes data. After the data processing is finished, the control module 600 pulls down the power-down delay control pin PowerEN to control the motor controller to sleep.

When the communication sleep wake-up module 700 receives the CAN communication message, the third pin (INH pin) corresponding to the communication chip 710 outputs a high level, the diode D3 transmits the high level to the gate of the third electronic switching tube Q3 (NMOS tube), and the third electronic switching tube Q2 (NMOS tube) is turned on and outputs a low level to control the second electronic switching tube Q2 (PMOS tube) to be turned on. When the second electronic switching tube Q2 (PMOS tube) is conducted, the motor controller is in an awakening state, and the controlled load RL has power input. When the CAN communication message is powered down, the third pin (INH pin) corresponding to the communication chip 710 keeps the high level output for a period of time and then turns to the low level output, so as to control the motor controller to delay dormancy.

In the above process, when the second electronic switching tube Q2 (PMOS tube) is turned off, the motor controller is in a sleep state, and the controlled load RL has no power input, i.e. the power of the motor controller is cut off, and when the motor controller is turned off, the sleep power consumption of the whole motor controller is all from the second electronic switching tube Q2 (PMOS tube) and the communication chip 710, so that the sleep power consumption can be extremely low.

In summary, the power-down detection module 500 performs level detection on the hard-wire sleep wakeup signal KL15, and is compatible with two modes of CAN sleep wakeup and hard-wire sleep wakeup signal KL15 wakeup, when a user uses the hard-wire sleep wakeup signal KL15 to perform sleep wakeup, only KL15 wakeup is used, after the power-down detection module 500 detects that the hard-wire sleep wakeup signal KL15 is powered down, a low level is output through the pin PowerON delay 2S of the control module 600, so that the motor controller delays to sleep for data storage. When the user wakes up using CAN sleep, pin PowerON of control module 600 does not respond and sleep is delayed by configuring communication chip 710. The voltages of the CAN communication signal and the hard wire sleep wakeup signal KL15 are relatively large, and a third voltage dividing resistance unit 210 (including a resistor R7 and a resistor R8) is provided to divide the large voltage when transmitting to the rear stage circuit, and then to a rear stage third electronic switching tube Q3 (including an NMOS tube), thereby preventing damage to the rear stage electronic switch. Meanwhile, the pin PowerON of the control module 600 is arranged to directly drive the third electronic switching tube Q3 (comprising an NMOS tube) at the rear stage, and a voltage dividing resistor is not needed.

Therefore, the embodiment of the utility model CAN be compatible with two modes of CAN dormancy wakeup and hard wire dormancy wakeup signal KL15, is beneficial to flexible configuration of users, and CAN be matched with CAN dormancy wakeup or hard wire dormancy wakeup signal KL15 according to requirements. And when the hard wire dormancy wakeup signal KL15 is adopted, the power-down delay function is matched, so that the data can be stored before the power-down of the motor controller. In addition, when the embodiment of the utility model is in dormancy, the dormancy is realized through the positive input of the cut-off power supply, and the dormancy power consumption is very low.

The embodiment of the utility model also provides a motor controller, which comprises the dormancy wakeup circuit provided by any embodiment of the utility model, and the technical principle and the effect are similar, and are not repeated. The controlled power line is an input power line of the motor controller, and the controlled load is a load of the motor controller.

The embodiment of the utility model also provides a vehicle which comprises a motor and the motor controller provided by any embodiment of the utility model, wherein the motor controller is used for controlling the operation of the motor. Because the vehicle provided by the utility model comprises the motor controller provided by any embodiment of the utility model, the technical principle and the produced effect are similar, and the description is omitted.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present utility model may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present utility model are achieved, and the present utility model is not limited herein.

The above embodiments do not limit the scope of the present utility model. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the scope of the present utility model.

Claims (10)

1. A sleep wake-up circuit, comprising:

the first switch module is connected in series between the controlled power line and the controlled load;

the second switch module is electrically connected with the first switch module; the second switch module is used for controlling the first switch module;

the hard wire dormancy wakeup module and the delay power-down module are electrically connected with the second switch module; the hard wire dormancy wakeup module is used for controlling the second switch module according to a hard wire dormancy wakeup signal;

the power failure detection module is electrically connected with the hard wire dormancy wakeup module; the power-down detection module is used for detecting whether the hard wire dormancy wakeup module is powered down or not;

the control module is electrically connected with the power-down detection module and the delay power-down module; and the control module is used for controlling the power-down delay module to delay power down after detecting the power down of the hard wire dormancy wakeup module.

2. The sleep wake-up circuit of claim 1, wherein the power down detection module comprises:

the control electrode of the first electronic switching tube is electrically connected with the hard wire dormancy awakening module, the first electrode of the first electronic switching tube is connected with a pull-up voltage, and the second electrode of the first electronic switching tube is connected with a pull-down voltage;

the first voltage dividing resistor unit is electrically connected with the control electrode and the second electrode of the first electronic switching tube; the first voltage dividing resistor unit is used for protecting the voltage of the first electronic switching tube;

the first current limiting unit is connected in series between the first pole of the first electronic switching tube and the pull-up voltage.

3. The sleep wake-up circuit of claim 2, wherein the first electronic switching tube is a triode;

and/or, the first voltage dividing resistance unit includes: the first resistor is connected in series between the control electrode of the first electronic switch tube and the hard wire dormancy wakeup module; the second resistor is connected between the control electrode and the second electrode of the first electronic switching tube;

and/or the first current limiting unit comprises a third resistor, and the third resistor is connected in series between the first pole of the first electronic switching tube and the pull-up voltage.

4. The sleep wake-up circuit of claim 1, wherein the hardwired sleep wake-up module comprises: a first unidirectional conduction unit; the first end of the first unidirectional conduction unit is connected with the hard wire dormancy wakeup signal, and the second end of the first unidirectional conduction unit is electrically connected with the second switch module;

and/or, the delay power down module comprises: the second current limiting unit and the second unidirectional conduction unit; the second current limiting unit and the second unidirectional conduction unit are connected in series between the control module and the second switch module.

5. The sleep wake-up circuit as claimed in claim 1, characterized in that, further comprises:

the communication dormancy wakeup module is electrically connected with the second switch module; the communication dormancy wakeup module is used for controlling the second switch module according to the communication dormancy wakeup signal.

6. The sleep wake-up circuit of claim 5, wherein the communication sleep wake-up module comprises: a communication chip and a third unidirectional conduction unit; the first pin of the communication chip is connected to the communication dormancy awakening signal, the second pin of the communication chip is electrically connected with the control module, the third pin of the communication chip is electrically connected with the first end of the third unidirectional conduction unit, and the second end of the third unidirectional conduction unit is electrically connected with the second switch module.

7. The sleep wake-up circuit of claim 1, wherein the first switch module comprises:

the control electrode of the second electronic switching tube is electrically connected with the second switching module, the first electrode of the second electronic switching tube is electrically connected with the controlled power line, and the second electrode of the second electronic switching tube is electrically connected with the controlled load;

the second voltage-dividing resistor unit is electrically connected with the second electronic switch tube; the second voltage-dividing resistor unit is used for protecting the voltage of the second electronic switching tube.

8. The sleep wake-up circuit of claim 1, wherein the second switch module comprises:

the control electrode of the third electronic switching tube is electrically connected to the hard wire dormancy awakening module, the second electrode of the third electronic switching tube is electrically connected with the first switching module, and the first electrode of the third electronic switching tube is grounded;

the third voltage dividing resistor unit is electrically connected with the third electronic switch tube; the third voltage dividing resistor unit is used for protecting the voltage of the third electronic switching tube.

9. A motor controller comprising a sleep wake-up circuit as claimed in any one of claims 1-8;

the controlled power line is an input power line of the motor controller, and the controlled load is a load of the motor controller.

10. A vehicle comprising an electric machine and the electric machine controller of claim 9 for controlling operation of the electric machine.