CN219392653U - Video memory expansion device interconnected with GPU chip - Google Patents

Abstract

The utility model relates to the field of computers, in particular to a video memory expansion device interconnected with a GPU chip, wherein the GPU chip C _j Comprises N1 (j) first chip-crossing interconnection devices, and the video memory expansion device E _i Comprises a second video memory controller MC2 _i Second video memory H2 _i And a second chip-crossing interconnection means SAC _i The MC2 _i For controlling the H2 _i Is accessed by a user; q first chip-crossing interconnection device FAC ^j _q With SAC _i Interconnect using non-QPI busA bus interconnect; the C is _j Other processors than the one cannot access MC2 _i Or by the FAC ^j _q With SAC _i Accessing MC2 _i The video memory expansion device can increase the independent video memory special for the GPU with higher compatibility and lower cost on the premise of not changing the hardware structure of the first video memory controller of the GPU and the whole hardware architecture of the GPU.

Description

Video memory expansion device interconnected with GPU chip

Technical Field

The utility model relates to the field of computers, in particular to a video memory expansion device interconnected with a GPU chip.

Background

In the computer field, typical processors include a central processing unit (CPU, central Processing Unit) and a graphics processing unit (GPU, graphics Processing Unit). In general, the memory accessed by the CPU is referred to as "memory", the memory accessed by the GPU is referred to as "video memory", and the memory and the video memory may be memories having the same structure and/or parameters, or memories having different structures and/or parameters. Devices that control memory are commonly referred to as memory controllers, and devices that control video memory are commonly referred to as video memory controllers.

The CPU accesses the memory through the memory controller, in particular in two cases. In one case, the memory controller is separate from the CPU, for example, the memory controller is included in a North Bridge (North Bridge) chip, in which case the CPU accesses the memory controller in the North Bridge chip via a Front Side Bus (FSB) to access the memory. In another case, the memory controller is integrated in the CPU, in which case the CPU may access the memory controller and thus the memory without using a front-side bus. Further, the memory is typically removably mounted in a memory slot of a Motherboard (moltherboard), which may be, for example, a slot supporting a dual in-line memory module (DIMM, dual Inline Memory Modules).

When the memory capacity required by the CPU is insufficient, the memory can be conveniently expanded by increasing the number of the memories or replacing the memories with larger capacity because the memories are pluggable. Further, when the number of memory slots is insufficient, the memory may be further extended by an external memory slot, for example, by using a QPI bus and/or SMI (Scalable Memory Interconnect) to link an external memory extension chip, a specific technology of using the QPI bus to extend the memory by using the external memory extension chip may refer to CN103488436B, and a technology of using the QPI bus and SMI to link the extended memory may refer to CN205091735U. Obviously, the above method for expanding the memory capacity only changes the physical position of the expansion memory and the connection mode between the memory and the CPU, but does not change the architecture among the CPU, the memory controller and the memory, namely, the CPU accesses the expansion memory through the memory controller.

Further, the system memory may be shared in a symmetric multiprocessor (SMP, symmetrical Multi Processing) manner, or the memory of different CPUs may be shared in a non-uniform memory access (NUMA, non Uniform Memory Access) manner.

The GPU comprises an integrated display card and an independent display card.

The graphics card-integrated GPU is integrated onto the motherboard or within other chips of the motherboard. The GPU of the integrated graphics card usually has no independent video memory, and needs to share the memory with the CPU, i.e. the configurable part of the memory is used by the CPU, and the configurable part of the memory is used by the GPU. In this case, the GPU needs to access the memory through the memory controller of the CPU, i.e. the access path includes the GPU, the memory controller of the CPU and the memory. When the memory capacity required by the GPU is insufficient, the memory for the GPU can be increased by configuration.

The GPU integrated in the independent display card is an independent chip and is fixed on the display card in a non-detachable mode, and the display card is connected to the main board through an interface bus. The interface bus may include, for example, an accelerated graphics port (AGP, accelerate Graphical Port) bus or PCIe (Peripheral Component Interconnect express) bus. The fixing means is, for example, welding. The GPU in the independent graphics card typically has a memory controller integrated therein and accesses the independent memory through the memory controller.

When the GPU in the early independent video card is in face of insufficient video memory capacity, a processing mode similar to a CPU is adopted, namely, the video memory is increased or the video memory with larger capacity is replaced through the video memory slot, and the position of the video memory slot can be on a main board or on the video card where the GPU is located; and the video memory can be increased by connecting an independent video memory expansion card to the interface. For example, the technology of the video memory slot on the motherboard may refer to chinese patent CN203966018U, CN203720713U, the technology of the video memory slot on the video card may refer to shadow GeForce 6200A video card (https:// tech.sina.com/2005-04-8/1027596611. Shtmlfrom=wap), the technology of the independent video memory expansion card may refer to hua AV264+ video card (https:// www.163.com/mobile/big i ih0d0011309 k.html), and so on. Obviously, the above method for expanding the display capacity only changes the physical position of the display memory and/or the expanded display memory and the connection mode between the display memory and the GPU, and does not change the framework among the GPU, the display memory controller and the display memory, namely, the GPU accesses the expanded display memory through the display memory controller.

The method for expanding the video memory by the GPU in the early independent video card has the following technical problems: the first slot or the interface for detachably mounting the video memory occupies more physical space of the video card and/or the main board, and the placement of other elements on the video card and/or the main board where the GPU is located is affected under the condition that the function and/or the performance of the GPU are greatly improved; second, with a large increase in memory function and/or performance, the number of pin interfaces in the socket has also increased significantly, thereby presenting a challenge to wiring between the GPU and the memory.

In order to solve the technical problems, unlike the CPU and the GPU in the early independent graphics card, the video memory of the GPU of the high-performance independent graphics card is packaged in the GPU or is fixed on the graphics card where the GPU is located in a non-detachable manner, so as to reduce the occupation of physical space and alleviate the challenges caused by wiring. Because the memory is not alterable, the memory controller of the GPU of the high performance stand-alone graphics card is not typically specifically designed to have the functionality to support additional extended memory. The memory of the GPU of the high performance stand-alone graphics card is illustratively a high bandwidth memory (HBM, high Bandwidth Memory) or GDDR (Graphics Double Data Rate).

In a GPU of a high performance stand alone graphics card, the video memory accessible by the video memory controller is typically packaged in the GPU or is non-detachably secured to the graphics card on which the GPU resides. When faced with insufficient memory capacity, there are mainly two solutions. The solution is to use the mode of accessing the memory by the integrated display card to share the memory of the CPU, namely the GPU accesses the memory of the CPU through the interface between the display card and the main board and the memory controller of the CPU; the interface between the graphics card and the motherboard is, for example, an AGP bus or a PCIe bus. Another is to share the memory of other GPUs, i.e., GPUs access the memory of other GPUs interconnected to the GPU through a cross-chip interconnect interface, including, for example, NVlink and/or NVSwitch.

The method for expanding the video memory by the GPU of the high-performance independent video card has the following technical problems: because the GPU and the CPU share memory, or the GPU and other GPUs share video memory, the memory and/or the upper limit of the video memory of the GPU and the CPU, or the upper limit of the video memory of the GPU and the other GPUs cannot be increased on the premise of not changing the video memory controller of the GPU. When the CPU or other GPU also needs to use more memory or video memory, there is more memory or video memory contention.

Disclosure of Invention

In order to solve the technical problems, the utility model aims to provide a video memory expansion device interconnected with a GPU chip, which adopts the following technical scheme:

in a first aspect, an embodiment of the present utility model provides a memory expansion device interconnected with a GPU chip C _j Comprises N1 (j) first chip-crossing interconnection devices { FAC ^j ₁ ,FAC ^j ₂ ,…,FAC ^j _q ,…,FAC ^j _N1(j) }, wherein FAC ^j _q Is C _j Q is in the range of 1 to N1 (j), and the function value of N1 (j) is a positive integer; the video memory expanding device E _i Comprises a second video memory controller MC2 _i Second video memory H2 _i And a second chip-crossing interconnection means SAC _i The MC2 _i For controlling the H2 _i Is accessed by a user; the FAC ^j _q With SAC _i Interconnection bus interconnection using non-QPI buses; the C is _j Other processors than the one cannot access MC2 _i Or by the FAC ^j _q With SAC _i Accessing MC2 _i 。

The utility model has the following beneficial effects:

the video memory expansion device which is interconnected with the GPU chip is interconnected with the first cross-chip interconnection device of the GPU chip through the second cross-chip interconnection device, the second video memory controller is not accessed by other processors, the second video memory is used as a special video memory of the GPU, the first video memory controller in the high-performance GPU does not need to be changed, the first video memory which is not detachably connected with the first video memory controller does not need to be replaced, namely, the special independent video memory of the GPU can be increased with higher compatibility and lower cost on the premise that the hardware structure of the first video memory controller of the GPU and the whole hardware architecture of the GPU are not changed.

Drawings

In order to more clearly illustrate the embodiments of the utility model or the technical solutions and advantages of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the utility model, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a system block diagram of a GPU processor system according to an embodiment of the present utility model.

Detailed Description

In order to further describe the technical means and effects of the present utility model for achieving the predetermined objects, the following detailed description refers to the specific embodiments, structures, features and effects of a GPU processor system according to the present utility model with reference to the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" means that the embodiments are not necessarily the same. Furthermore, the particular features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs.

The following specifically describes a specific scheme of the video memory expansion device interconnected with the GPU chip provided by the utility model with reference to the accompanying drawings.

Referring to FIG. 1, the GPU processor system includes N GPU chips { C ₁ ,C ₂ ,…,C _j ,…,C _N And non-detachably fixed at C _j First video memory H1 on the display card _j Wherein C _j Is the j thGPU chips, wherein the value range of j is 1 to N, N is the number of GPU chips, and N is a positive integer; the C is _j Comprises a first video memory controller MC1 which is not changeable _j And N1 (j) first chip-crossing interconnections { FAC ^j ₁ ,FAC ^j ₂ ,…,FAC ^j _q ,…,FAC ^j _N1(j) }，FAC ^j _q Is C _j Q is in the range of 1 to N1 (j), and the function value of N1 (j) is a positive integer; the MC _j For controlling the H1 _j Is used for the access of (a).

Alternatively, C _j Is a high performance GPU chip. The high performance GPU chip has an interface therein to a first cross-chip interconnect device connected to a first bus.

Preferably, the GPU chip is a graphics processor, a general purpose graphics processor, or an AI processor.

Preferably, H1 _j Is a video memory conforming to the HBM or GDDR standard.

It should be noted that, the first video memory controller is integrated inside the GPU and is an important component unit inside the GPU. The first video memory controller is connected with the first video memory, and when the first video memory is HBM, the first video memory and the GPU chip are packaged together; when the first video memory is GDDR, the first video memory is welded on the display card to which the GPU chip belongs.

Further, the system also comprises M independent video memory expansion devices { E ₁ ,E ₂ ,…,E _i ,…,E _M }，E _i The method comprises the steps that i is an ith video memory expansion device, the value range of i is 1 to M, M is the number of the video memory expansion devices, and M is a positive integer; e (E) _i Comprises a second video memory controller MC2 _i Second video memory H2 _i And a second chip-crossing interconnection means SAC _i The method comprises the steps of carrying out a first treatment on the surface of the The MC2 _i For controlling the H2 _j Is used for the access of (a).

Wherein E is _i No GPU and/or CPU chips are included.

Preferably, H2 _i Is greater than H1 _j And H2 _i Is smaller than H1 _j Is not limited to the bandwidth of the (c).

Preferably, the second displayStoring H2 _i Is a memory conforming to DDR standard or LPDDR standard.

Optionally, a second video memory H2 _i Detachably fixed at E _i The detachable fixing mode is as follows: second video memory controller MC2 _i Through DIMM interface and second video memory H2 _j And the DIMM interface is connected with each other, so that the plugging and unplugging are convenient, and the second video memory is convenient to replace.

Alternatively, E _i Comprises M (i) second video memory controllers MC2 _i And M (i) second video memories H2 _j Wherein M (i) second video memories H2 _j The memory can be all the memory meeting DDR standard; or the memory can be all the memory meeting the LPDDR standard; alternatively, a part of the second video memory may be compliant with the DDR standard, and the remaining second video memory may be compliant with the LPDDR standard.

Further, FAC ^j _q With SAC _i Interconnect bus interconnect using non-QPI bus.

Wherein FAC ^j _q And SAC _i Conforming to the same interconnect bus protocol. FAC (Fabry-Perot) ^j _q With SAC _i Comprises a physical layer, an adaptation layer and a protocol layer.

Alternatively, FAC ^j _q And SAC _i The interconnect protocol bandwidth of (a) is higher than the bandwidth of the PCIe bus.

Preferably, FAC ^j _q And SAC _i Bus interconnect compliant with MetaX Link, NVLink, informance Fabric, or UCIe standards are used. It is understood that the bandwidth of NVLink 1.0 can reach 160GB/s at maximum, the bandwidth of NVLink 2.0 can reach 300GB/s at maximum, and the bandwidth of MetaX Link can reach 128GB/s at maximum; the maximum bidirectional bandwidth of the communication of the GPU connected with the PCIe device can reach 32GB/s; therefore, the bandwidth of the video memory expansion device with NVLink 1.0 is about 5 times that of PCIe, the bandwidth of the video memory expansion device with NVLink 2.0 is about 9 times that of PCIe, and the bandwidth of the video memory expansion device with MetaX Link is 4 times that of PCIe.

Preferably, FAC ^j _q And SAC _i Interconnect devices conforming to the UCIe standard are compared to interconnect devices conforming to the NVLink standard and the information Fabric standardThe power consumption of the interconnect device is lower.

Wherein FAC ^j _q And SAC _i In order to make point-to-point connection, point-to-point connection is simpler in physical design and can make control logic simpler. FAC (Fabry-Perot) ^j _q And SAC _i The method is used for realizing interconnection between the chip and the video memory expansion device, has short physical transmission distance relative to a mode of sharing the memory by PCIe, and can greatly reduce the delay problem of data transmission. Wherein FAC ^j _q And SAC _i The conditions that need to be met for making a point-to-point connection are: when FAC ^j _q And SAC _i Upon interconnection, FAC ^j _p And SAC _i Are not interconnected and FAC ^j _q And SAC _k Not interconnected, where FAC ^j _p Is C _j The p-th first chip-crossing interconnection means, SAC _k Expansion device E for kth video memory _k In (2) p noteq, i notek).

Preferably, when FAC ^j _q And the kth GPU chip C _k P-th first chip-on-chip interconnect device FAC ^k _p Cannot be connected with the SAC when interconnected _i And (5) interconnection. Or when FAC ^j _q Is not capable of interconnecting with the SAC when interconnecting with the first chip-crossing interconnection device of the CPU chip _i And (5) interconnection.

Optionally, when n=1 and m=1, the GPU processor system includes a GPU chip and a video memory expansion device connected to the GPU chip, which is a one-to-one expansion structure.

Optionally, when n=1 and M >1, the GPU processor system includes one GPU chip and M video memory expansion devices connected to the GPU chip, which is a one-to-many expansion structure.

Alternatively, when N >1 and M >1, a one-to-one expansion structure or a one-to-many expansion structure may be included in the GPU processor system; further, a one-to-one expansion structure and a one-to-many expansion structure may be included in a processor system.

Further, MC1 _j Not controlling H2 _i Is accessed by (a) theMC2 _i Not controlling H1 _j Is used for the access of (a).

It will be appreciated that C _j By MC1 _j Access H1 _j And pass through MC2 _i Accessing H2 _i ，H1 _j And H2 _i Are all C _j Is a special video memory of MC2 _i Is only C _j The method can solve the problem of resource competition caused by shared memory or video memory, and the expanded special video memory breaks through the upper limit of capacity.

Wherein H1 _j And H2 _i A unified addressing mode is adopted. Specifically, C _j Comprises an address translation unit, and H1 is translated by the address translation unit _j And H2 _i And performing unified address conversion.

Alternatively, C _j The first interface bus is used for sharing the memory with the CPU. Optionally, the first interface bus is an AGP bus or a PCIe bus. It should be noted that the shared memory refers to a part of the memory as C _j And the other part is used as a memory special for the CPU. I.e. C _j Accessing the memory controller of the CPU through the first interface bus, and further accessing the memory as C through the memory controller of the CPU _j And a memory space of the special video memory.

Alternatively, H2 _i The bandwidth of which is greater than the memory shared by the CPU.

Further, the C _j Other processors than the one cannot access MC2 _i Or by FAC ^j _q With SAC _i Accessing the MC2 _i 。

Preferably, E _i Further comprises a data read-write controller RWC _i ，RWC _i With MC2 _i Connecting; SAC (SAC) _i With RWC _i Connecting; when RWC _i Receive C _j By FAC ^j _q And SAC _i RWC at the time of the first access command sent _i Converting the first access command into a second access command and sending the second access command to a second video memory controller; the first access command is not recognizable by the second video memory controller, and the second access command is recognizable by the second video memory controller.

Wherein RWC _i For conversion of command formats, when RWCs _i The received first access command cannot be received by MC2 _i RWC upon identification _i Converting the first access command into a second access command and transmitting the second access command to the MC2 through the second bus _i From MC2 _i To H2 _i Issuing a read-write task. When the first access command is a read data command, H2 _i Passing the return data through MC2 in turn _i Second bus, RWC _i 、SAC _i 、FAC ^j _q Return to C _j Wherein the returned procedure is a reciprocal procedure to the accessed procedure, requiring the conversion of the second access command into the first access command. Wherein the command formats of the first access command and the second access command are different, specifically, C _j And E is connected with _i The data packet of the first access command transmitted between the two is larger than that in E _i The data packet of the second access command transmitted internally, for example, the data packet of the first access command includes a read-write command of 128 bytes, and the data packet of the second access command includes a read-write command of 32 bytes. Before converting the first access command into the second access command, the method comprises: SAC (SAC) _i Analyzing the received first access command to obtain a plurality of read-write commands, and sending the read-write commands of 32Byte-256Byte to the data read-write controller RWC by taking the virtual page of 4KB as a unit _i Make RWC _i Repackaging the read-write command into a second access command.

Optionally, the protocol of the second bus is AXI bus protocol.

Preferably, the memory expansion device is realized by an FPGA or ASIC design.

In summary, the video memory expansion device interconnected with the GPU chip provided by the utility model includes the second inter-chip interconnection device connected with the first inter-chip interconnection device of the GPU, the GPU accesses the second video memory controller through the first inter-chip interconnection device and the second inter-chip interconnection device, and then accesses the second video memory, and the second video memory controller is not accessed by other processors, so that the second video memory is used as a dedicated video memory of the GPU, the first video memory controller in the GPU with high performance is not required to be changed, and the GDDR or HBM which is not detachably connected with the first video memory controller is not required to be replaced, namely, the dedicated independent video memory of the GPU can be increased with higher compatibility and lower cost on the premise that the hardware structure of the video memory controller of the GPU and the overall hardware architecture of the GPU are not changed.

It should be noted that: the sequence of the embodiments of the present utility model is only for description, and does not represent the advantages and disadvantages of the embodiments. And the foregoing description has been directed to specific embodiments of this specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.

The foregoing description of the preferred embodiments of the utility model is not intended to limit the utility model to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the utility model are intended to be included within the scope of the utility model.

Claims (8)

1. Video memory expansion device interconnected with GPU chip, wherein GPU chip C _j Comprises N1 (j) first chip-crossing interconnection devices { FAC ^j ₁ ,FAC ^j ₂ ,…,FAC ^j _q ,…,FAC ^j _N1(j) }, wherein FAC ^j _q Is C _j Q is in the range of 1 to N1 (j), and the function value of N1 (j) is a positive integer; the display memory expanding device is characterized in that _i Comprises a second video memory controller MC2 _i Second video memory H2 _i And a second chip-crossing interconnection means SAC _i The MC2 _i For controlling the H2 _i Is accessed by a user; the FAC ^j _q With SAC _i Interconnection bus interconnection using non-QPI buses; the C is _j Other processors than the one cannot access MC2 _i Or by the FAC ^j _q With SAC _i Accessing MC2 _i 。

2. The apparatus of claim 1, wherein the C _j Also comprises a first video memory controller MC1 _j The MC1 _j For controlling the first video memory H1 _j Is accessed by the H1 _j Non-detachably fixed on the C _j On the graphics card where it is located.

3. The apparatus of claim 2, wherein the MC1 is _j Not controlling the H2 _i Is accessed by the MC2 _i Not controlling the H1 _j Is used for the access of (a).

4. The apparatus of claim 1, wherein the SAC _i Buses conforming to the MetaX Link, NVLink, infinity Fabric, or UCIe standards are used.

5. The apparatus of claim 1, wherein the H2 _i Is a memory conforming to DDR standard or LPDDR standard.

6. The apparatus of claim 1, wherein the E _i Further comprises a data read-write controller RWC _i ，RWC _i With MC2 _i Connecting; SAC (SAC) _i With RWC _i Connecting;

when RWC _i Receive C _j By FAC ^j _q And SAC _i RWC at the time of the first access command sent _i Converting the first access command into a second access command and sending the second access command to a second video memory controller; the first access command is not recognized by the second video memory controller, and the second access commandEnabling identification by the second video memory controller.

7. The apparatus of claim 1, wherein the H2 _i Interfacing with MC2 through DIMM _i And (5) connection.

8. The apparatus of claim 1, wherein the video memory expansion means is implemented by FGPA or ASIC design.