CN217720774U - Charging and discharging fast discharging circuit and rechargeable battery - Google Patents

Charging and discharging fast discharging circuit and rechargeable battery Download PDF

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Publication number
CN217720774U
CN217720774U CN202221412460.1U CN202221412460U CN217720774U CN 217720774 U CN217720774 U CN 217720774U CN 202221412460 U CN202221412460 U CN 202221412460U CN 217720774 U CN217720774 U CN 217720774U
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discharge
charge
fast
transistor
field effect
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梁志锋
吴翔龙
吴伟
陈志军
叶国华
张志平
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Guangdong Greenway Technology Co Ltd
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Guangdong Greenway Technology Co Ltd
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Abstract

The application provides a charge-discharge fast discharge circuit and a rechargeable battery. The charge-discharge fast discharge circuit comprises a charge-discharge field effect transistor and a parasitic fast discharge circuit; parasitic fast discharge circuit includes fast putting and reaches woods dun pipe and first resistance, and the second end of fast putting and reaching woods dun pipe is connected with charge and discharge controller's control end, and the second end of fast putting and reaching woods dun pipe still is connected with charge and discharge field effect transistor's grid, and the first end of fast putting and reaching woods dun pipe is connected with the first end of first resistance, and the second end of first resistance is connected with charge and discharge field effect transistor's source electrode, and the level that switches on of fast putting and reaching woods dun pipe and charge and discharge field effect transistor is different. When the control end of the charge-discharge controller outputs the turn-off level, the charge-discharge field effect tube is cut off, the parasitic capacitor between the grid electrode and the source electrode of the charge-discharge field effect tube discharges, and the charge released by the parasitic capacitor passes through the fast-release Darlington tube, so that the turn-off rate of the charge-discharge fast-release circuit is effectively improved.

Description

Charging and discharging fast discharging circuit and rechargeable battery
Technical Field
The utility model relates to a battery technology field especially relates to a charge-discharge fast discharge way and rechargeable battery.
Background
The MOS tube is adopted for switch control in a plurality of electronic systems at present, and aiming at the current circuits with high power for switch control, the conduction resistance of the MOS tube is small, compared with a triode, the conduction voltage drop is much smaller, the heating power is correspondingly reduced, and the condition of blow-out is not easy to occur. When the MOS tube is used as a switching circuit, the MOS tube can be normally closed as long as two ends of the GS are higher than a driving threshold value. In a battery management system, a MOS transistor is often used to control a charge/discharge circuit.
However, as can be seen from the composition structure of the MOS transistor, parasitic capacitors exist between every two gate levels G, source S, and drain D of the MOS transistor, the driving of the MOS transistor is actually charging and discharging these capacitors, and applying a voltage to the GS terminal is charging the parasitic capacitors of the GS terminal.
SUMMERY OF THE UTILITY MODEL
The utility model aims at overcoming the weak point among the prior art, providing a fast way and rechargeable battery of discharging of charge-discharge that effectively improves the turn-off rate of the fast way of discharging of charge-discharge.
The purpose of the utility model is realized through the following technical scheme:
a charge-discharge fast discharge circuit comprising: a charge-discharge field effect transistor and a parasitic fast discharge circuit; the drain electrode of the charge-discharge field effect tube is grounded, and the source electrode of the charge-discharge field effect tube is used for being connected with the charging cathode; parasitic fast discharge circuit is including putting fast the woodton pipe and first resistance, the control end of putting fast the woodton pipe is used for being connected with charge and discharge controller's control end, the second end of putting fast the woodton pipe with charge and discharge controller's control end is connected, the second end of putting fast the woodton pipe still with charge and discharge field effect transistor's grid is connected, the first end of putting fast the woodton pipe with the first end of first resistance is connected, the second end of first resistance with charge and discharge field effect transistor's source electrode is connected, wherein, put fast the woodton pipe and charge and discharge field effect transistor's the level that switches on is different.
In one embodiment, the parasitic fast-discharge circuit further comprises a non-flowing diode, an anode of the non-flowing diode is connected with the control end of the charge-discharge controller, and a cathode of the non-flowing diode is connected with the second end of the fast-discharge darlington tube.
In one embodiment, the parasitic fast discharge circuit further includes a second resistor, a control end of the fast discharge darlington transistor is connected to a first end of the second resistor, and a second end of the second resistor is connected to a source electrode of the charge-discharge field effect transistor.
In one embodiment, the resistance value of the first resistor is smaller than the resistance value of the second resistor.
In one embodiment, the parasitic fast-discharge circuit further comprises a voltage stabilizing diode, the second end of the fast-discharge darlington tube is connected with the anode of the voltage stabilizing diode, and the cathode of the voltage stabilizing diode is connected with the source of the charge-discharge field effect tube.
In one embodiment, the charge and discharge fet is an N-type MOS transistor, the fast release darlington transistor includes a first PNP triode and a first NPN triode, a base and an emitter of the first PNP triode are respectively connected to the control end of the charge and discharge controller, a collector of the first PNP triode is connected to the base of the first NPN triode, a collector of the first NPN triode is connected to the emitter of the first PNP triode, and an emitter of the first NPN triode is connected to the first end of the first resistor.
In one embodiment, the charge and discharge field effect transistor is an N-type MOS transistor, the fast release darlington transistor includes a second PNP triode and a third PNP triode, an emitter of the second PNP triode is connected with the control end of the charge and discharge controller, a base of the second PNP triode is connected with an emitter of the third PNP triode, a collector of the second PNP triode is connected with the first end of the first resistor, a base of the third PNP triode is connected with the control end of the charge and discharge controller, and a collector of the third PNP triode is connected with a collector of the second PNP triode.
In one embodiment, the charge and discharge fet is a P-type MOS transistor, the fast release darlington transistor includes a second NPN transistor and a third NPN transistor, a collector and a base of the second NPN transistor are respectively connected to the control end of the charge and discharge controller, an emitter of the second NPN transistor is connected to a base of the third NPN transistor, a collector of the third NPN transistor is connected to the control end of the charge and discharge controller, and an emitter of the third NPN transistor is connected to the first end of the first resistor.
In one embodiment, the charge and discharge fet is a P-type MOS transistor, the fast playing darlington transistor includes a fourth PNP transistor and a fourth NPN transistor, an emitter of the fourth PNP transistor is connected to the control end of the charge and discharge controller, a base of the fourth PNP transistor is connected to a collector of the fourth NPN transistor, a collector of the fourth PNP transistor is connected to the first end of the first resistor, a base of the fourth NPN transistor is connected to the control end of the charge and discharge controller, and an emitter of the fourth NPN transistor is connected to the collector of the fourth PNP transistor.
A rechargeable battery comprising the charge and discharge fast discharge circuit according to any of the above embodiments.
Compared with the prior art, the utility model discloses at least, following advantage has:
when the control end of the charge-discharge controller outputs the turn-off level, the charge-discharge field effect tube is cut off, the parasitic capacitor between the grid electrode and the source electrode of the charge-discharge field effect tube discharges, the fast-release Darlington tube is turned on at the moment, the charges released by the parasitic capacitor are consumed through the fast-release Darlington tube and the first resistor, the voltage on the parasitic capacitor is conveniently and fast released, and the turn-off rate of the charge-discharge fast-discharge circuit is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a circuit diagram of a charge and discharge fast discharge circuit according to an embodiment;
FIG. 2 is a circuit diagram of a charge and discharge fast discharge circuit in another embodiment;
FIG. 3 is a circuit diagram of a charge-discharge fast-discharge circuit in yet another embodiment;
fig. 4 is a circuit diagram of a charge and discharge fast discharge circuit in another embodiment.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a single embodiment.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The utility model relates to a charge-discharge fast discharge circuit. In one embodiment, the charge and discharge fast discharge circuit comprises a charge and discharge field effect transistor and a parasitic fast discharge circuit. The drain electrode of the charge-discharge field effect tube is grounded, and the source electrode of the charge-discharge field effect tube is used for being connected with the charging cathode. The parasitic fast discharge circuit comprises a fast discharge Darlington tube and a first resistor. The control end of fast putting darlington pipe is used for being connected with the control end of charge and discharge controller, the second end of fast putting darlington pipe with the control end of charge and discharge controller is connected, the second end of fast putting darlington pipe still with the grid of charge and discharge field effect transistor is connected. The first end of the fast-release Darlington tube is connected with the first end of the first resistor, and the second end of the first resistor is connected with the source electrode of the charge-discharge field effect tube. And the conduction levels of the fast-release Darlington tube and the charge and discharge field effect tube are different. When the control end of the charge-discharge controller outputs the turn-off level, the charge-discharge field effect tube is cut off, the parasitic capacitor between the grid electrode and the source electrode of the charge-discharge field effect tube discharges, the fast-release Darlington tube is turned on at the moment, the charges released by the parasitic capacitor are consumed through the fast-release Darlington tube and the first resistor, the voltage on the parasitic capacitor is conveniently and fast released, and the turn-off rate of the charge-discharge fast-discharge circuit is effectively improved.
Please refer to fig. 1, which is a circuit diagram of a charge/discharge fast discharging circuit according to an embodiment of the present invention.
The charge/discharge fast discharging circuit 10 of an embodiment includes a charge/discharge fet QC1 and a parasitic fast discharging circuit 100. The drain electrode of the charge-discharge field-effect tube QC1 is grounded, and the source electrode of the charge-discharge field-effect tube QC1 is used for being connected with a charge cathode C-. The parasitic fast discharge circuit 100 includes a fast discharge darlington tube and a first resistor RK2. The control end of the fast-release Darlington tube is used for being connected with the control end CHG of the charge-discharge controller, the second end of the fast-release Darlington tube is connected with the control end CHG of the charge-discharge controller, and the second end of the fast-release Darlington tube is further connected with the grid electrode of the charge-discharge field effect tube QC1. The first end of the fast-release Darlington tube is connected with the first end of the first resistor RK2, and the second end of the first resistor RK2 is connected with the source electrode of the charge-discharge field-effect tube QC1. And the conduction levels of the fast-release Darlington tube and the charge-discharge field effect tube QC1 are different.
In this embodiment, when the control terminal CHG of the charge and discharge controller outputs the off-state power, the charge and discharge fet QC1 is turned off, the parasitic capacitance between the gate and the source of the charge and discharge fet QC1 is discharged, and the fast release darlington transistor is turned on at this time, and the charge released by the parasitic capacitance is consumed through the fast release darlington transistor and through the first resistor RK2, so that the voltage on the parasitic capacitance is quickly released, and the turn-off rate of the charge and discharge fast release circuit is effectively improved. The specific size of the turn-off level can be determined according to the types and polarities of the charge-discharge field-effect tube QC1 and the fast-release Darlington tube.
In one embodiment, referring to fig. 1, the parasitic fast discharge circuit 100 further includes a flood prevention diode DK1, an anode of the flood prevention diode DK1 is connected to the control terminal CHG of the charge and discharge controller, and a cathode of the flood prevention diode DK1 is connected to the second terminal of the fast discharge darlington tube. In this embodiment, the anti-sinking diode DK1 is located between the charge and discharge controller and the fast-release darlington transistor, and specifically, the anti-sinking diode DK1 is located between the control end CHG of the charge and discharge controller and the second end of the fast-release darlington transistor, and the second end of the fast-release darlington transistor is further connected to the gate of the charge and discharge field-effect transistor QC1, so that the current output by the control end CHG of the charge and discharge controller has a unidirectional characteristic, that is, the current output by the control end CHG of the charge and discharge controller flows into the gate of the charge and discharge field-effect transistor QC1 in a unidirectional manner, thereby preventing the gate of the charge and discharge field-effect transistor QC1 from sinking current into the charge and discharge controller. Therefore, when the charge-discharge field-effect tube QC1 is in a cut-off state, namely the charge-discharge field-effect tube QC1 is turned off, even if the voltage of the charge cathode C-is lower than the voltage of the ground end, the charge-discharge field-effect tube QC1 can be ensured to be kept turned off, the situation that the charge-discharge field-effect tube QC1 is turned on at the moment is avoided, and therefore accurate turn-off control of the charge-discharge controller on the charge-discharge field-effect tube QC1 is ensured.
In one embodiment, referring to fig. 1, the parasitic fast discharge circuit 100 further includes a second resistor RK1, a control terminal CHG of the fast discharge darlington transistor is connected to a first terminal of the second resistor RK1, and a second terminal of the second resistor RK1 is connected to a source of the charge and discharge fet QC1. In this embodiment, the second resistor RK1 is located between the fast-release darlington tube and the charge and discharge field-effect tube QC1, and specifically, the second resistor RK1 is connected in series between a control end CHG of the fast-release darlington tube and a source of the charge and discharge field-effect tube QC1, and the control end CHG of the fast-release darlington tube is further connected to the control end CHG of the charge and discharge controller, so that a control voltage output by the control end CHG of the charge and discharge controller is loaded on the second resistor RK1 and the charge and discharge field-effect tube QC1, and thus a certain voltage is continuously maintained on the second resistor RK1, thereby ensuring a voltage on a gate of the charge and discharge field-effect tube QC1, and effectively avoiding a situation in which the gate of the charge and discharge field-effect tube QC1 is damaged due to suspension of the control voltage, thereby ensuring stable control of an on-off state of the charge and discharge field-effect tube QC1.
In another embodiment, the resistance value of the first resistor RK2 is smaller than the resistance value of the second resistor RK 1. When a control end CHG of the charge and discharge controller outputs a turn-off signal, the charge and discharge field effect tube QC1 is turned off, the fast Darlington tube is turned on, the second resistor RK1 and the fast Darlington tube form a parasitic capacitance discharge loop of the charge and discharge field effect tube QC1, namely the second resistor RK1 and the fast Darlington tube provide a capacitance charge circulation loop for a parasitic capacitance between a grid electrode and a source electrode of the charge and discharge field effect tube QC1, so that charges on the parasitic capacitance between the grid electrode and the source electrode of the charge and discharge field effect tube QC1 can be discharged quickly, and the turn-off speed of the charge and discharge field effect tube QC1 is effectively improved. The first resistor RK2 and the second resistor RK1 can form a loop, the resistance value of the first resistor RK2 is smaller than that of the second resistor RK1, so that the currents of the two loops are adjusted, namely the discharge current of the discharge loop is increased, and the turn-off rate of the charge-discharge field-effect transistor QC1 is further improved. In another embodiment, at least one of the resistance value of the first resistor RK2 and the resistance value of the second resistor RK1 is adjustable, that is, at least one of the first resistor RK2 and the second resistor RK1 is a rheostat, so as to adjust the turn-off rate of the charge and discharge fet QC1.
In one embodiment, referring to fig. 1, the parasitic fast discharge circuit 100 further includes a voltage regulator diode ZK1, a second end of the fast discharge darlington transistor is connected to an anode of the voltage regulator diode ZK1, and a cathode of the voltage regulator diode ZK1 is connected to a source of the charge and discharge fet QC1. In this embodiment, the zener diode ZK1 is located between the charge and discharge controller and the charge and discharge fet QC1, and specifically, the zener diode ZK1 is located between the control terminal CHG of the charge and discharge controller and the source of the charge and discharge fet QC1. The control end CHG of the charge and discharge controller supplies power to the grid electrode of the charge and discharge field effect tube QC1, so that the voltage stabilizing diode ZK1 is connected between the grid electrode and the source electrode of the charge and discharge field effect tube QC1 in parallel, the voltage output by the control end CHG of the charge and discharge controller is kept stable through the voltage stabilizing diode ZK1, stable driving voltage is conveniently provided between the grid electrode and the source electrode of the charge and discharge field effect tube QC1, the situation that the grid electrode of the charge and discharge field effect tube QC1 is damaged due to suspension of control voltage is also avoided, and stable control over the opening and closing state of the charge and discharge field effect tube QC1 is further ensured.
In one embodiment, please refer to fig. 1, the charge-discharge fet QC1 is an N-type MOS transistor, the fast-release darlington transistor includes a first PNP transistor QKP1 and a first NPN transistor QKN1, a base and an emitter of the first PNP transistor QKP1 are respectively connected to the control terminal CHG of the charge-discharge controller, a collector of the first PNP transistor QKP1 is connected to the base of the first NPN transistor QKN1, a collector of the first NPN transistor QKN1 is connected to the emitter of the first PNP transistor QKP1, and an emitter of the first NPN transistor QKN1 is connected to the first end of the first resistor RK2. In this embodiment, the charge and discharge fet QC1 is turned on at a high level, the first PNP triode QKP1 is turned on at a low level, and the first NPN triode QKN1 is turned on at a high level. When the control end CHG of the charge and discharge controller outputs a low level, the charge and discharge field effect tube QC1 is cut off, the first PNP triode QKP1 and the first NPN triode QKN1 are simultaneously conducted, the charge of the parasitic capacitance between the grid electrode and the source electrode of the charge and discharge field effect tube QC1 passes through the first NPN triode QKN1 and is consumed at the first resistor RK2, the discharge is not required to be carried out through the charge and discharge controller, and the discharge current of the first NPN triode QKN1 and the first resistor RK2 is increased, so that the discharge rate of the parasitic capacitance between the grid electrode and the source electrode of the charge and discharge field effect tube QC1 is increased, the turn-off rate of the charge and discharge field effect tube QC1 is effectively improved, and the charge and discharge field effect tube QC1 is convenient to be quickly turned off.
In one embodiment, please refer to fig. 2, the charge and discharge fet QC1 is an N-type MOS transistor, the fast playing darlington transistor includes a second PNP transistor QKP2 and a third PNP transistor QKP3, an emitter of the second PNP transistor QKP2 is connected to the control terminal CHG of the charge and discharge controller, a base of the second PNP transistor QKP2 is connected to an emitter of the third PNP transistor QKP3, a collector of the second PNP transistor QKP2 is connected to the first terminal RK2, a base of the third PNP transistor QKP3 is connected to the control terminal CHG of the charge and discharge controller, and a collector of the third PNP transistor QKP3 is connected to a collector of the second PNP transistor QKP 2. In this embodiment, the charge and discharge fet QC1 is turned on at a high level, and the second PNP transistor QKP2 and the third PNP transistor QKP3 are both turned on at a low level. When the control end CHG of the charge-discharge controller outputs a low level, the charge-discharge field-effect tube QC1 is cut off, the second PNP triode QKP2 and the third PNP triode QKP3 are simultaneously conducted, the charge of the parasitic capacitance between the grid electrode and the source electrode of the charge-discharge field-effect tube QC1 passes through the second PNP triode QKP2 and is consumed at the first resistor RK2, the discharge is not required to be carried out through the charge-discharge controller, and the discharge current of the second PNP triode QKP2 and the first resistor RK2 is increased, so that the discharge rate of the parasitic capacitance between the grid electrode and the source electrode of the charge-discharge field-effect tube QC1 is increased, the turn-off rate of the charge-discharge field-effect tube QC1 is effectively improved, and the charge-discharge field-effect tube QC1 is convenient to be quickly turned off.
In one embodiment, referring to fig. 3, the charge and discharge fet QC1 is a P-type MOS transistor, the fast release darlington transistor includes a second NPN transistor QKN2 and a third NPN transistor QKN3, a collector and a base of the second NPN transistor QKN2 are respectively connected to the control terminal CHG of the charge and discharge controller, an emitter of the second NPN transistor QKN2 is connected to a base of the third NPN transistor QKN3, a collector of the third NPN transistor QKN3 is connected to the control terminal CHG of the charge and discharge controller, and an emitter of the third NPN transistor QKN3 is connected to the first end of the first resistor RK2. In this embodiment, the charge/discharge fet QC1 is turned on at a low level, and the second NPN transistor QKN2 and the third NPN transistor QKN3 are turned on at a high level. When the control end CHG of the charge and discharge controller outputs a high level, the charge and discharge field-effect tube QC1 is turned off, the second NPN triode QKN2 and the third NPN triode QKN3 are turned on simultaneously, charges of a parasitic capacitance between the gate and the source of the charge and discharge field-effect tube QC1 pass through the third NPN triode QKN3 and are consumed at the first resistor RK2, and discharge is not required to be performed through the charge and discharge controller, and the discharge current passing through the third NPN triode QKN3 and the first resistor RK2 is increased, so that the discharge rate of the parasitic capacitance between the gate and the source of the charge and discharge field-effect tube QC1 is increased, thereby effectively increasing the turn-off rate of the charge and discharge field-effect tube QC1 and facilitating rapid turn-off of the charge and discharge field-effect tube QC1.
In one embodiment, referring to fig. 4, the charge and discharge fet QC1 is a P-type MOS transistor, the fast setdown fet includes a fourth PNP transistor QKP4 and a fourth NPN transistor QKN4, an emitter of the fourth PNP transistor QKP4 is connected to the control terminal CHG of the charge and discharge controller, a base of the fourth PNP transistor QKP4 is connected to a collector of the fourth NPN transistor QKN4, a collector of the fourth PNP transistor QKP4 is connected to the first end of the first resistor RK2, a base of the fourth PNP transistor qnpn transistor QKN4 is connected to the control terminal CHG of the charge and discharge controller, and an emitter of the fourth PNP transistor QKN4 is connected to the collector of the fourth PNP transistor QKP 4. In this embodiment, the charge and discharge fet QC1 is turned on at a low level, the fourth PNP triode QKP4 is turned on at a low level, and the fourth NPN triode QKN4 is turned on at a high level. When the control end CHG of the charge and discharge controller outputs a high level, the charge and discharge field-effect tube QC1 is turned off, the fourth PNP triode QKP4 and the fourth NPN triode QKN4 are turned on simultaneously, the charge of the parasitic capacitance between the gate and the source of the charge and discharge field-effect tube QC1 passes through the fourth PNP triode QKP4 and is consumed at the first resistor RK2, and the discharge is not required to be performed by the charge and discharge controller, and the discharge current passing through the fourth PNP triode QKP4 and the first resistor RK2 is increased, so that the discharge rate of the parasitic capacitance between the gate and the source of the charge and discharge field-effect tube QC1 is increased, thereby effectively increasing the turn-off rate of the charge and discharge field-effect tube QC1 and facilitating the rapid turn-off of the charge and discharge field-effect tube QC1.
In the above embodiments, the on-state voltage of the charge and discharge fet and the on-state voltage of each transistor may be adjusted according to different models, that is, the forward bias voltage of the PN junction may be adjusted, so as to control the on-state and the off-state of each thyristor, that is, under the same control voltage, the on-state and the off-state of the fast-release darlington transistor and the charge and discharge fet may be opposite.
In one embodiment, the present application further provides a rechargeable battery, including the charge and discharge fast discharge circuit according to any of the above embodiments. In this embodiment, the charge and discharge fast discharge circuit includes a charge and discharge fet and a parasitic fast discharge circuit. The drain electrode of the charge-discharge field effect tube is grounded, and the source electrode of the charge-discharge field effect tube is used for being connected with the charging cathode. The parasitic fast discharge circuit comprises a fast release Darlington tube and a first resistor. The control end of fast putting darlington pipe is used for being connected with the control end of charge and discharge controller, the second end of fast putting darlington pipe with the control end of charge and discharge controller is connected, the second end of fast putting darlington pipe still with the grid of charge and discharge field effect transistor is connected. The first end of the fast-release Darlington tube is connected with the first end of the first resistor, and the second end of the first resistor is connected with the source electrode of the charge-discharge field effect tube. And the conduction levels of the fast-release Darlington tube and the charge and discharge field effect tube are different. When the control end of the charge-discharge controller outputs the turn-off level, the charge-discharge field effect tube is cut off, the parasitic capacitor between the grid electrode and the source electrode of the charge-discharge field effect tube discharges, the fast-release Darlington tube is turned on at the moment, the charges released by the parasitic capacitor are consumed through the fast-release Darlington tube and the first resistor, the voltage on the parasitic capacitor is conveniently and fast released, and the turn-off rate of the charge-discharge fast-discharge circuit is effectively improved.
The above-mentioned embodiments only represent several embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims (10)

1. A charge-discharge fast discharge circuit, comprising:
the drain electrode of the charge-discharge field effect tube is grounded, and the source electrode of the charge-discharge field effect tube is used for being connected with the charging cathode;
parasitic fast discharge circuit, parasitic fast discharge circuit is including putting fast the woodton pipe and first resistance that reaches, the control end that puts fast the woodton pipe is used for being connected with charge and discharge controller's control end, the second end that puts fast the woodton pipe with charge and discharge controller's control end is connected, the second end that puts fast the woodton pipe still with charge and discharge field effect transistor's grid is connected, the first end that puts fast the woodton pipe with the first end of first resistance is connected, the second end of first resistance with charge and discharge field effect transistor's source electrode is connected, wherein, put fast the woodton pipe and charge and discharge field effect transistor's the level that switches on is different.
2. The charge-discharge fast-discharge circuit according to claim 1, wherein said parasitic fast-discharge circuit further comprises a anti-sinking diode, an anode of said anti-sinking diode is connected to a control terminal of said charge-discharge controller, and a cathode of said anti-sinking diode is connected to a second terminal of said fast-discharge darlington tube.
3. The charge-discharge fast-discharge circuit according to claim 1, wherein said parasitic fast-discharge circuit further comprises a second resistor, a control terminal of said fast-discharge darlington transistor is connected to a first terminal of said second resistor, and a second terminal of said second resistor is connected to a source of said charge-discharge fet.
4. The charge-discharge fast discharge circuit according to claim 3, wherein the resistance of said first resistor is smaller than the resistance of said second resistor.
5. The charge-discharge fast-discharge circuit according to claim 1, wherein said fast-discharge circuit further comprises a zener diode, a second terminal of said fast-discharge darlington transistor is connected to an anode of said zener diode, and a cathode of said zener diode is connected to a source of said charge-discharge fet.
6. The charge-discharge fast-amplifying circuit according to claim 1, wherein the charge-discharge field effect transistor is an N-type MOS transistor, the fast-release darlington transistor includes a first PNP transistor and a first NPN transistor, a base and an emitter of the first PNP transistor are respectively connected to the control terminal of the charge-discharge controller, a collector of the first PNP transistor is connected to the base of the first NPN transistor, a collector of the first NPN transistor is connected to the emitter of the first PNP transistor, and an emitter of the first NPN transistor is connected to the first terminal of the first resistor.
7. The charge-discharge fast discharging circuit according to claim 1, wherein the charge-discharge field effect transistor is an N-type MOS transistor, the fast discharging darlington transistor comprises a second PNP triode and a third PNP triode, an emitter of the second PNP triode is connected to the control end of the charge-discharge controller, a base of the second PNP triode is connected to an emitter of the third PNP triode, a collector of the second PNP triode is connected to the first end of the first resistor, a base of the third PNP triode is connected to the control end of the charge-discharge controller, and a collector of the third PNP triode is connected to a collector of the second PNP triode.
8. The charge-discharge fast-discharging circuit according to claim 1, wherein the charge-discharge field effect transistor is a P-type MOS transistor, the fast-discharging darlington transistor includes a second NPN transistor and a third NPN transistor, a collector and a base of the second NPN transistor are respectively connected to the control terminal of the charge-discharge controller, an emitter of the second NPN transistor is connected to a base of the third NPN transistor, a collector of the third NPN transistor is connected to the control terminal of the charge-discharge controller, and an emitter of the third NPN transistor is connected to the first terminal of the first resistor.
9. The charge-discharge fast-discharging circuit according to claim 1, wherein the charge-discharge field effect transistor is a P-type MOS transistor, the fast-discharging darlington transistor includes a fourth PNP transistor and a fourth NPN transistor, an emitter of the fourth PNP transistor is connected to the control terminal of the charge-discharge controller, a base of the fourth PNP transistor is connected to a collector of the fourth NPN transistor, a collector of the fourth PNP transistor is connected to the first terminal of the first resistor, a base of the fourth NPN transistor is connected to the control terminal of the charge-discharge controller, and an emitter of the fourth NPN transistor is connected to a collector of the fourth PNP transistor.
10. A rechargeable battery comprising the charge-discharge fast-discharge circuit according to any one of claims 1 to 9.
CN202221412460.1U 2022-06-07 2022-06-07 Charging and discharging fast discharging circuit and rechargeable battery Active CN217720774U (en)

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CN202221412460.1U CN217720774U (en) 2022-06-07 2022-06-07 Charging and discharging fast discharging circuit and rechargeable battery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202221412460.1U CN217720774U (en) 2022-06-07 2022-06-07 Charging and discharging fast discharging circuit and rechargeable battery

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CN217720774U true CN217720774U (en) 2022-11-01

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