CN217306116U

CN217306116U - Testing device

Info

Publication number: CN217306116U
Application number: CN202220844030.0U
Authority: CN
Inventors: 朱玉龙
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2022-04-12
Filing date: 2022-04-12
Publication date: 2022-08-26
Anticipated expiration: 2032-04-12

Abstract

The application discloses testing arrangement includes that at least one tests the board main part, it includes to test the board main part to test testing arrangement: the first connection interface is used for receiving a test instruction and performing test data interaction with the test host; the second connection interface is used for carrying out test data interaction and test instruction interaction with the second connection interface in any other test board main body; the processor module is used for transmitting the test data acquired by the first connection interface or the second connection interface to the corresponding test seat after acquiring the test instruction from the first connection interface or the second connection interface; and the test sockets are used for transmitting the test data from the first connection interface or the second connection interface to the corresponding memories to be tested and testing the memories to be tested. The method and the device can test the plurality of memories simultaneously, so that the test efficiency is improved, and the production cost is reduced.

Description

Testing device

Technical Field

The application relates to the technical field of electronic product testing, in particular to a testing device.

Background

In daily life, a common memory includes a Solid State Disk (SSD). The production process of the memory comprises surface mounting, testing, shell mounting and quality inspection. In the testing process, a plurality of testers and a plurality of testing instruments are generally required to perform operations such as firmware burning, repeated data reading and writing, and the like, so that the production cost is inevitably increased when the memory is produced in a large scale.

Disclosure of Invention

To the technical problem, the application provides a testing device, can test a plurality of storages simultaneously, reduces manual operation, reduction in production cost.

The embodiment of the application provides a testing device, which comprises at least one testing board main body, wherein the testing board main body comprises a first connecting interface, a second connecting interface, a processor module and a plurality of testing seats;

the first connection interface is used for receiving a test instruction and performing test data interaction with a test host, wherein the test instruction and the test data are both generated by the test host;

the second connection interface is used for carrying out test data interaction and test instruction interaction with the second connection interface in any other test board main body;

the processor module is electrically connected with the first connection interface and the second connection interface respectively, and is used for transmitting test data acquired by the first connection interface or the second connection interface to a corresponding test socket after acquiring a test instruction from the first connection interface or the second connection interface;

the plurality of test sockets are electrically connected with the processor module and used for transmitting the test data from the first connecting interface or the second connecting interface to the corresponding memory to be tested and testing the memory to be tested.

Optionally, the second connection interface includes:

the output end is used for sending a test instruction and test data to the input end of the second connecting interface in any of the rest test board main bodies;

and the input end is used for receiving the test instruction and the test data output by the output end of the second connecting interface in any other test board main body.

Optionally, the test plate body further comprises:

and the connecting assembly is used for connecting the test board main bodies.

Optionally, the test board body is a polygonal circuit board;

the output end and the input end are respectively arranged on the edges of different sides of the circuit board.

Optionally, the output terminal and the input terminal are respectively arranged on the edges of the opposite sides of the circuit board;

setting the edge of the circuit board where the output end is located as a first edge and setting the edge of the circuit board where the input end is located as a second edge;

the first connecting interface is arranged at the edge of the circuit board, and the edge of the circuit board where the first connecting interface is arranged is a third side edge;

the third side edge is adjacent to the first side edge, and the third side edge is adjacent to the second side edge.

Optionally, the output end disposed at the first side edge is opposite the input end portion disposed at the second side edge.

Optionally, the first connection interface includes a first plug-in projecting outwards from a third side edge, for being inserted into the test host to realize electrical connection with the test host;

the difference between the distance from the center point of the output end to the third side edge and the distance from the center point of the input end to the third side edge is greater than or equal to the depth of the first plug-in unit inserted into the test host; or,

the difference between the distance from the center point of the input end to the third side edge and the distance from the center point of the output end to the third side edge is greater than or equal to the depth of the first plug-in unit inserted into the test host.

Optionally, the connecting assembly includes a plurality of connecting members, a portion of the connecting members are disposed on an edge of the circuit board on the same side as the output terminal, and another portion of the connecting members are disposed on an edge of the circuit board on the same side as the input terminal.

Optionally, at least one of the connecting members is adjacent to one end of the output or the input, and at least one of the connecting members is adjacent to the other end of the output or the input.

Optionally, the connecting assembly further comprises a plurality of sub-connectors, each sub-connector cooperating with a corresponding connecting member.

Optionally, the output terminal is a second plug-in projecting outwards from the edge of the circuit board; the input end is a slot matched with the second plug-in.

Optionally, the connecting component on the same side as the output end is a protruding part protruding outwards from the edge of the circuit board, and the protruding part is provided with a first positioning hole;

the connecting part which is positioned on the same side with the input end is a second positioning hole which is the same as the first positioning hole;

the sub-connecting piece is a positioning bolt which is used for penetrating through the first positioning hole and the second positioning hole.

Compared with the prior art, the embodiment of the application has the following beneficial effects:

the test device provided by the embodiment of the application comprises at least one test board main body, wherein the test board main body comprises a first connecting interface, a second connecting interface, a processor module and a plurality of test seats; the first connection interface is used for receiving a test instruction and performing test data interaction with a test host, wherein the test instruction and the test data are both generated by the test host; the second connection interface is used for carrying out test data interaction and test instruction interaction with the second connection interface in any other test board main body; the processor module is respectively electrically connected with the first connecting interface and the second connecting interface and is used for transmitting the test data acquired by the first connecting interface or the second connecting interface to the corresponding test seat after acquiring the test instruction from the first connecting interface or the second connecting interface; and the plurality of test sockets are electrically connected with the processor module and are used for transmitting the test data from the first connecting interface or the second connecting interface to the corresponding memory to be tested and testing the memory to be tested. Therefore, in this embodiment, after the processor module obtains the test instruction through the first connection interface or the second connection interface, the test data obtained by the first connection interface or the second connection interface is correspondingly transmitted to the corresponding test socket, and the test socket transmits the test data to the corresponding to-be-tested memory, so as to test the to-be-tested memory. Because testing arrangement includes a plurality of test seats, can test a plurality of memories that await measuring simultaneously through a plurality of test seats of this testing arrangement, can realize the test to a plurality of memories that await measuring promptly through a testing arrangement, and need not a plurality of test instrument, it is corresponding, also need not a plurality of testers to improve efficiency of software testing, reduction in production cost. Furthermore, when a plurality of test board main parts transmit test instructions and test data through the second connecting interface, technicians can install more memories to be tested on a plurality of test sockets of the plurality of test board main parts respectively, so that more test sockets can be utilized to complete the test of the memories to be tested, and therefore more memories to be tested can be tested simultaneously, and the test efficiency is further improved.

Drawings

FIG. 1 is a first structural diagram of a testing device provided in an embodiment of the present application;

FIG. 2 is a second structural diagram of a testing device provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a third structure of a testing device provided in the embodiments of the present application;

FIG. 4 is a fourth structural diagram of a testing device according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a fifth structure of a testing device provided in the embodiments of the present application;

FIG. 6 is a schematic diagram of a sixth structure of a testing device provided in the embodiments of the present application;

10, testing the plate body; 11. a communication module; 12. a processor module; 13. a test seat; 14. a connecting assembly; 111. a first connection interface; 112. a second connection interface; 1121. an output end; 1122. an input end; 141. a connecting member; 142. a sub-connector.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The application provides a testing arrangement, this testing arrangement includes that at least one tests the board main part, tests the board main part and includes communication module, processor module and a plurality of test seat.

Referring to fig. 1, fig. 1 is a schematic view illustrating a first structure of a testing apparatus according to an embodiment of the present disclosure. In FIG. 1, a test apparatus including a test board main body 10 is illustrated. In practice, there may be a plurality of test board bodies. The test board main body 10 comprises a communication module 11, a processor module 12 and a plurality of test seats 13, wherein the communication module 11 is used for acquiring a test instruction; the processor module 12 is electrically connected to the communication module 11, and is configured to respectively establish a test data transmission channel between the communication module 11 and the corresponding test socket 13 after obtaining the test instruction from the communication module 11. The communication module 11 is further configured to obtain test data and transmit the test data to the corresponding test socket 13 through the test data transmission channel. The plurality of test sockets 13 are electrically connected with the processor module 12, and are used for transmitting the test data from the communication module 11 to the corresponding memory to be tested, and testing the memory to be tested.

It is understood that in order to test the memory under test, a technician needs to mount the memory under test on the test socket 13. The test socket 13 automatically transmits test data to the memory to be tested, i.e. the memory to be tested is burned with the test data, or the test data is frequently and repeatedly read and written, so as to complete the test of the memory to be tested.

In the present embodiment, the test instruction is first obtained through the communication module 11, and then transmitted to the processor module 12; after receiving the test instruction, the processor module 12 establishes a test data transmission channel between the communication module 11 and the corresponding test socket 13 according to the test instruction. It should be noted that, according to the test instruction, the processor module 12 may establish the test data transmission channel for one or more of the plurality of test sockets 13, and the test sockets 13 that have not established the test data transmission channel are suspended for use, and the test data transmission channel is re-established when they need to be used. In some embodiments, the test data transmission channel established corresponding to each test socket 13 may transmit different test data corresponding to each test socket 13. After obtaining the test data through the corresponding test data transmission channel, each test socket 13 transmits the test data to the memory to be tested installed on the test socket 13, so as to test the memory to be tested.

It can be understood that, after the processor module 12 obtains the test instruction through the communication module 11 and establishes the test data transmission channels between the communication module 11 and the corresponding test sockets 13, each test socket 13 transmits the test data to the corresponding memory to be tested through the data transmission channels, so as to test the memory to be tested. Because testing arrangement includes a plurality of test seats 13, can test a plurality of memories that await measuring simultaneously through a plurality of test seats 13 of this testing arrangement, can realize the test to a plurality of memories that await measuring promptly through a testing arrangement, and need not a plurality of test instrument, it is corresponding, also need not a plurality of testers to improve efficiency of software testing, reduction in production cost.

Although the test board main body 10 is provided with a plurality of test sockets 13, the test board main body 10 is oversized by the plurality of test sockets 13, so that the entire test apparatus cannot be used in a small instrument (e.g., a burn-in box). In order to solve the problem, the embodiment of the application provides a testing device.

Referring to fig. 2, fig. 2 is a second structural diagram of the testing apparatus according to the embodiment of the present disclosure. In FIG. 2, the test apparatus including a test board main body 10 is illustrated. In practice, there may be a plurality of test board bodies.

In one embodiment, the communication module 11 includes a first connection interface 111 and a second connection interface 112, wherein the first connection interface 111 is configured to receive a test command and perform test data interaction with a test host, and both the test command and the test data are generated by the test host. The second connection interface 112 is used for performing test data interaction and test instruction interaction with the second connection interface 112 in any of the remaining test board bodies 10.

It is understood that the present embodiment can realize the electrical connection of the second connection interfaces 112 of two or three test board bodies 10 to adapt the test bit of 8/16/24 of the test software. It should be noted that the number of the test board main bodies 10 connected through the second connection interface 112 may be two or more, and depends on the transmission rate between the test host and the first connection interface 111. In the case of high transmission rate operation, the number of test board body 10 combinations can be expanded to the maximum. Preferably, the first connection interface 111 uses a PCI-e type interface to reach a higher transmission rate.

In this embodiment, the first connection interface 111 is mainly used for connecting with a test host, and the test host may be a computer or a test instrument such as an aging test box. Generally, the test host is the main source of test commands and test data, so the first connection interface has a faster transmission speed than the second connection interface 112.

When the first connection interface 111 performs test data interaction with the test host, a test instruction is received through the first connection interface 111, and then the test instruction is transmitted to the processor module 12; after receiving the test instruction, the processor module 12 respectively establishes a test data transmission channel between the communication module 11 and the corresponding test socket 13 according to the test instruction; after obtaining the test data through the corresponding test data transmission channel, each test socket 13 transmits the test data to the memory to be tested installed on the test socket 13, so as to test the memory to be tested. If the second connection interface 112 is connected to the second connection interface 112 of another test board main body 10, the test data and the test command from the first connection interface 111 can also be transmitted to the test board main body 10 other than the test board main body 10 through the second connection interface 112.

When the first connection interface 111 does not perform test data interaction with the test host, the test board main body 10 of the embodiment can obtain the test command and the interactive test data from the second connection interface 112 of another test board main body 10 through the second connection interface 112 (another test board main body 10 obtains the test command from the test host and performs test data interaction with the test host through the first connection interface 111). Receiving the test instruction through the second connection interface 112 and then transmitting the test instruction to the processor module 12; after receiving the test instruction, the processor module 12 respectively establishes a test data transmission channel between the communication module 11 and the corresponding test socket 13 according to the test instruction; after obtaining the test data through the corresponding test data transmission channel, each test socket 13 transmits the test data to the memory to be tested installed on the test socket 13, so as to test the memory to be tested.

It can be understood that, in this embodiment, the test command and the interactive test data can be obtained through the first connection interface 111, and the test command and the interactive test data can be obtained through the second connection interface 112, so that the ways of obtaining the test command and the interactive test data are various, and the failure of the whole test apparatus caused by that any interface cannot be used is avoided. Moreover, when the plurality of test board main bodies 10 transmit the test instruction and the test data through the second connection interface 112, a technician can install more memories to be tested on the plurality of test sockets 13 of the plurality of test board main bodies 10, so that the test on the memories to be tested can be completed by using more test sockets 13, thereby realizing the test on more memories to be tested simultaneously and improving the test efficiency.

In order to connect more test board bodies 10, the present embodiment provides a test apparatus.

Referring to fig. 3, fig. 3 is a schematic diagram of a third structure of a testing apparatus according to an embodiment of the present disclosure. In FIG. 3, the test apparatus including a test board main body 10 is illustrated. In practice, there may be a plurality of test board bodies.

In one embodiment, the second connection interface 112 includes an output 1121 and an input 1122; the output end 1121 is used for sending a test command and test data to the input end 1122 of the second connection interface 112 of any other test board main body 10. The input terminal 1122 is used for receiving the test command and the test data output from the output terminal 1121 of the second connection interface 112 of any other test board main body 10.

It can be understood that, in an embodiment of connecting more test board bodies 10, 3 test board bodies are taken as an example for description, for convenience of description, the 3 test board bodies are respectively referred to as a first test board body, a second test board body, and a third test board body, an input end of a second connection interface in the first test board body receives a test instruction and test data transmitted by an output end of the second connection interface in the second test board body, and the first test board body receives the test instruction through an input end thereof and then transmits the test instruction to a processor module of the first test board body; after the processor module receives the test instruction, respectively establishing a test data transmission channel between the communication module of the first test board main body and the test seat corresponding to the first test board main body according to the test instruction; after the test seat of each first test board main body acquires the test data through the corresponding test data transmission channel, the test data are transmitted to the to-be-tested memory installed on the test seat of the first test board main body, so that the to-be-tested memory is tested.

Then, the first test board body sends the test instruction and the test data to the input end of the second connection interface in the third test board body through the output end of the second connection interface, and similarly, the third test board body tests the plurality of memories by using the plurality of test sockets after obtaining the test instruction and the test data, and the second test board body can obtain the test instruction and the test data from the test host or other test board bodies to test the plurality of memories, so that the plurality of test sockets of the plurality of test board bodies can be used for testing more memories as much as possible, and the test efficiency is further improved.

In one embodiment, the test board body 10 is a polygonal circuit board.

In some embodiments, the circuit board may be triangular, quadrilateral, pentagonal, hexagonal, not to name a few.

In the present embodiment, the output end 1121 and the input end 1122 are respectively disposed on the edges of different sides of the circuit board.

In some embodiments, the output end 1121 and the input end 1122 are respectively disposed at the edges of the adjacent sides of the circuit board.

It is understood that the first connection interface 111 may be disposed on the edge of the circuit board on the same side as the output end 1121 or the input end 1122, or disposed on the edge of the circuit board on a different side from the output end 1121 or the input end 1122.

In one embodiment, output 1121 and input 1122 are respectively disposed on opposite side edges of the circuit board. The edge of the circuit board where the output end 1121 is located is taken as a first side edge, and the edge of the circuit board where the input end 1122 is located is taken as a second side edge. The first connection interface 111 is disposed at an edge of the circuit board, and an edge of the circuit board where the first connection interface 111 is located is taken as a third side edge. The third side edge is adjacent to the first side edge and the third side edge is adjacent to the second side edge.

In one embodiment, output end 1121 disposed at the first side edge is partially opposite input end 1122 disposed at the second side edge.

It is understood that the output end 1121 and the input end 1122 which are located at opposite sides of each other may be a portion of the output end 1121 which is opposite to a portion of the input end 1122, or may be a portion of the output end 1121 which is completely opposite to the input end 1122, or even may be a portion of the output end 1121 which is not opposite to the input end 1122.

Although a plurality of test sockets 13 on a plurality of test board main bodies 10 can be used to test more memories to be tested by transmitting test instructions and test data among a plurality of test board main bodies 10, however, a plurality of test board main bodies 10 are easily separated due to the influence of external force when connected, and therefore, the embodiment of the present application provides a test device to solve the problem that a plurality of test board main bodies 10 are easily separated due to the influence of external force when connected.

In one embodiment, the test plate main body 10 further includes a connection assembly 14, wherein the connection assembly 14 is used to perform connection between the test plate main bodies 10.

It will be appreciated that in some embodiments the test plate body 10 may be connected to another test plate body 10 by means of the connecting members 14, or the test plate body 10 may be connected to more than two other test plate bodies 10 by means of the connecting members 14.

In one embodiment, the connection component 14 includes a plurality of connection components 141, a portion of the connection components 141 are located on the same side of the circuit board edge as the output end 1121, and another portion of the connection components 141 are located on the same side of the circuit board edge as the input end 1122.

In some embodiments, the number of connecting members 141 on the same side of output 1121 is different from the number of connecting members 141 on the same side of input 1122, e.g., n connecting members 141 on the same side of output 1121, m connecting members 141 on the same side of input 1122, n being greater than m, or n being less than m.

Preferably, the number of connecting members 141 on the same side as output end 1121 is equal to the number of connecting members 141 on the same side as input end 1122.

In some embodiments, the plurality of connecting components 141 are adjacent to one end of the output end 1121 at the same edge of the circuit board, or the plurality of connecting components 141 are adjacent to one end of the input end 1122 at the same edge of the circuit board.

Referring to fig. 4, fig. 4 is a fourth structural schematic diagram of a testing apparatus according to an embodiment of the present disclosure. In FIG. 4, the test apparatus including a test board main body 10 is illustrated. In practice, there may be a plurality of test board bodies. The testing board body 10 of the testing apparatus is a quadrilateral circuit board, the output end 1121 and the input end 1122 are respectively disposed at the edges of the opposite sides of the circuit board, and one edge of the first connection interface 111 is adjacent to both the edge of the output end 1121 and the edge of the input end 1122.

In another embodiment, at least one connection member 141 is adjacent to one end of the output end 1121 or the input end 1122, and at least one connection member 141 is adjacent to the other end of the output end 1121 or the input end 1122.

It is understood that the input end 1122 or the output end 1121 is provided with the connecting members 141 at both ends, the same number of connecting members 141 may be provided at both ends of the input end 1122 or the output end 1121, or different numbers of connecting members 141 may be provided at both ends of the input end 1122 or the output end 1121. When the input terminal 1122 of the test board main body 10 is electrically connected to the output terminal 1121 of another test board main body 10 (or the output terminal 1121 of the test board main body 10 is electrically connected to the input terminal 1122 of another test board main body 10), the connecting members 141 respectively located at the two ends of the input terminal 1122 or the output terminal 1121 can perform a better, more stable and more firm fixing function.

In some embodiments, the connection assembly 14 only contains the connection member 141, wherein the connection member 141 is a positioning clip for clamping the circuit board. The connecting member 141 may also be other members for realizing the fixing function, which are not listed here.

In another embodiment, the connection assembly 14 further includes a plurality of sub-connectors 142, each sub-connector 142 for mating with a corresponding connection member 141.

Referring to fig. 5, fig. 5 is a fifth structural schematic diagram of a testing apparatus according to an embodiment of the present disclosure. In FIG. 5, the test apparatus including a test board main body 10 is illustrated. In practice, there may be a plurality of test board bodies. The testing board body 10 of the testing device is a rectangular circuit board, the output end 1121 and the input end 1122 are respectively disposed on opposite side edges of the circuit board, and an edge of the first connecting interface 111 is adjacent to both the output end 1121 and the input end 1122.

In a preferred embodiment, the connection part 141 on the same side as the output end 1121 is a protrusion protruding outward from an edge of the circuit board, and the protrusion is provided with a first positioning hole. The connecting member 141 on the same side as the input end 1122 is a second positioning hole identical to the first positioning hole. The sub-connecting member 142 is a positioning pin for passing through the first positioning hole and the second positioning hole.

In one embodiment, the coupling part 141 is a screw hole, and the sub-coupling member 142 is a screw, and the screw is inserted into the screw hole to couple the sub-coupling member 142 and the coupling part 141.

The screw hole as the connecting member 141 and the corresponding screw as the sub-connecting member 142 are matched in one way, and there are other types of matching ways, which are not listed here.

Referring to fig. 6, fig. 6 is a sixth structural schematic diagram of a testing device according to an embodiment of the present disclosure. In FIG. 6, the test apparatus is illustrated as including two identical test board bodies 10 connected to each other. In practice, more than two identical test board bodies may be connected. The testing board body 10 of the testing apparatus is a quadrilateral circuit board, the output end 1121 and the input end 1122 are respectively disposed on the opposite side edges of the circuit board, and the edge of the first connection interface 111 is adjacent to both the edge of the output end 1121 and the edge of the input end 1122.

In one embodiment, the first connection interface 111 includes a first plug-in unit protruding outward from the third side edge, wherein the first plug-in unit is used for being inserted into the test host to realize electrical connection with the test host. The output end 1121 is a second plug-in projecting outward from the edge of the circuit board; input 1122 is a slot that mates with a second card.

Preferably, the difference between the distance from the center point of the output end 1121 to the third side edge and the distance from the center point of the input end 1122 to the third side edge is greater than or equal to the depth of the first plug-in inserted into the test host; alternatively, the difference between the distance from the center point of the input end 1122 to the third side edge and the distance from the center point of the output end 1121 to the third side edge is greater than or equal to the depth of the first plug-in inserted into the test host.

It can be understood that, since there are multiple application scenarios, only one of the application scenarios is taken as an example here to explain the present embodiment: the test board main bodies 10 of the two test apparatuses are electrically connected through the second connection interface 112, wherein the input end 1122 of one of the test board main bodies 10 is electrically connected to the output end 1121 of the other test board main body 10, or the output end 1121 of one of the test board main bodies 10 is electrically connected to the input end 1122 of the other test board main body 10, the test board main body 10 of one of the test apparatuses is inserted into the test host through the first plug-in of the first connection interface 111 to be electrically connected to the test host, and in order to avoid collision between the test board main body 10 of the other test apparatus and the test host, an installation space (e.g., a dotted area in fig. 6) needs to be left for the first plug-in of the first connection interface 111 to be inserted into the test host. The second plug-in units and the slots of the embodiment are arranged in a staggered manner, so that when the test board main bodies 10 of the two test devices are connected, the first plug-in units of the first connection interfaces 111 of the two test board main bodies 10 are not arranged in parallel, and therefore, when one of the test board main bodies 10 is inserted into the test host through the first plug-in unit of the first connection interface 111, the first plug-in unit of the first connection interface 111 of the other test board main body 10 is prevented from colliding with the test host.

That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.

In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In this application, the word "for example" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make and use the present application. In the foregoing description, various details have been set forth for the purpose of explanation.

It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. A testing device is characterized by comprising at least one testing board main body, wherein the testing board main body comprises a first connecting interface, a second connecting interface, a processor module and a plurality of testing seats;

and the test sockets are electrically connected with the processor module and used for transmitting the test data from the first connecting interface or the second connecting interface to the corresponding to-be-tested memory and testing the to-be-tested memory.

2. The testing device of claim 1, wherein the second connection interface comprises:

and the input end is used for receiving the test instruction and the test data output by the output end of the second connecting interface in any rest of the test board main bodies.

3. The test device of claim 2, wherein the test plate body further comprises:

and the connecting component is used for connecting the test board main bodies.

4. The test device of claim 3, wherein the test board body is a polygonal circuit board;

5. The test device of claim 4, wherein the output terminal and the input terminal are respectively disposed at edges of opposite sides of the circuit board;

6. The test device of claim 5, wherein the output end disposed at the first side edge is opposite the input end portion disposed at the second side edge.

7. The test device as claimed in claim 6, wherein the first connection interface comprises a first plug-in protruding outwards from a third side edge for being inserted into the test host to realize electrical connection with the test host;

the difference between the distance from the center point of the input end to the edge of the third side and the distance from the center point of the output end to the edge of the third side is greater than or equal to the depth of the first plug-in unit inserted into the test host.

8. The testing device of claim 4, wherein the connection assembly comprises a plurality of connection members, and a portion of the connection members are disposed on an edge of the circuit board on a same side as the output terminal, and another portion of the connection members are disposed on an edge of the circuit board on a same side as the input terminal.

9. The test device of claim 8, wherein at least one of the connection members is adjacent one end of the output or input and at least one of the connection members is adjacent the other end of the output or input.

10. The testing device of claim 9, wherein the connection assembly further comprises a plurality of sub-connectors, each sub-connector mating with a corresponding connection member.

11. The test apparatus defined in claim 10, wherein the output is a second insert projecting outwardly from an edge of the circuit board; the input end is a slot matched with the second plug-in.

12. The testing device of claim 11, wherein the connecting component on the same side as the output end is a protrusion protruding outward from an edge of the circuit board, and the protrusion is provided with a first positioning hole;