CN217085743U

CN217085743U - FPGA interface circuit of self-adaptation level standard

Info

Publication number: CN217085743U
Application number: CN202220864193.5U
Authority: CN
Inventors: 魏朝飞; 赵鑫鑫; 姜凯
Original assignee: Shandong Inspur Science Research Institute Co Ltd
Current assignee: Shandong Inspur Science Research Institute Co Ltd
Priority date: 2022-04-14
Filing date: 2022-04-14
Publication date: 2022-07-29
Anticipated expiration: 2032-04-14

Abstract

The utility model relates to the field of electronic technology, specifically provide a FPGA interface circuit of self-adaptation level standard, including FPGA integrated circuit board and external integrated circuit board, set up main control unit, programmable power and FPGA circuit on the FPGA integrated circuit board, main control unit, programmable power and FPGA circuit connect gradually, and the main control unit on the FPGA integrated circuit board is connected with external integrated circuit board and is carried out the detection of inserting of external integrated circuit board for read external integrated circuit board level standard, programmable power acquires the configuration of level standard through the main control unit. Compared with the prior art, the utility model discloses a FPGA interface level self-adaptation for the external integrated circuit board of FPGA integrated circuit board can compatible different level standards has improved the interface flexibility of FPGA integrated circuit board, has reduced product development cycle and cost, has extensive application prospect.

Description

FPGA interface circuit of self-adaptation level standard

Technical Field

The utility model relates to the field of electronic technology, specifically provide a FPGA interface circuit of self-adaptation level standard.

Background

The FPGA chip is widely applied to the fields of communication, images and the like, and some general purpose input and output GPIOs are usually reserved in the early design of the FPGA board card so as to facilitate later-stage function expansion. Conventionally, the reserved level standards supported by these GPIOs have been determined during design, and can only be adapted to some specific external boards at a later stage, which reduces the flexibility of the FPGA board interface.

Disclosure of Invention

The utility model discloses a to the not enough of above-mentioned prior art, provide a FPGA interface circuit of self-adaptation level standard that reasonable in design, simple structure, safe in utilization, flexibility ratio are high.

The utility model provides a technical scheme that its technical problem adopted is:

an FPGA interface circuit adaptive to level standard comprises an FPGA board card and an external board card,

the FPGA integrated circuit board is characterized in that a main control unit, a programmable power supply and an FPGA circuit are arranged on the FPGA integrated circuit board, the main control unit, the programmable power supply and the FPGA circuit are sequentially connected, the main control unit on the FPGA integrated circuit board is connected with an external integrated circuit board to perform insertion detection of the external integrated circuit board, the external integrated circuit board is used for reading the level standard of the external integrated circuit board, and the programmable power supply acquires the configuration of the level standard through the main control unit.

Furthermore, a storage unit, a resistance module and a function module are arranged on the external board card, the storage unit and the resistance module are connected with the main control unit, and the function module is connected with the FPGA circuit.

Furthermore, the main control unit is connected with the storage unit through an SCL line and an SDA line, and the FPGA is connected with the functional module through a GPIO line.

Further, an I2C interface of the main control unit is connected to the programmable power supply, and an output terminal VCCIO of the programmable power supply is connected to the FPGA circuit.

Further, the master control unit is connected with the programmable power supply through an SCL line and an SDA line.

Preferably, the main control unit adopts an MSP430 singlechip, the programmable power supply adopts MAX15301, and the FPGA circuit adopts an FPGA chip.

Preferably, the memory unit is an EEPROM, the resistance module is RL0603FR-070R1L, and the function module is ADV 7511.

The utility model discloses a FPGA interface circuit of self-adaptation level standard compares with prior art, has following outstanding beneficial effect:

(1) the utility model discloses a design has realized FPGA interface level self-adaptation for the FPGA integrated circuit board can compatible different level standard's external integrated circuit board, has improved the interface flexibility of FPGA integrated circuit board, has reduced product development cycle and cost, has extensive application prospect.

(2) The utility model has the advantages of reasonable design, simple structure, easy processing, convenient use, high flexibility and the like.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an FPGA interface circuit of an adaptive level standard.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to limit the present invention.

In the present invention, unless otherwise specified, the use of directional terms such as "upper, lower, left, and right" generally means upper, lower, left, and right as illustrated with reference to the accompanying drawings; "inner and outer" refer to the inner and outer relative to the profile of the components themselves.

A preferred embodiment is given below:

as shown in fig. 1, the FPGA interface circuit according to the adaptive level standard in this embodiment includes an FPGA board and an external board, where the FPGA board is provided with a main control unit, a programmable power supply, and an FPGA circuit. The main control unit, the programmable power supply and the FPGA circuit are sequentially connected, the main control unit on the FPGA board card is connected with the external board card to perform insertion detection on the external board card and read the level standard of the external board card, and the programmable power supply acquires the configuration of the level standard through the main control unit.

The external board card is provided with a storage unit, a resistance module and a functional module, the storage unit and the resistance module are both connected with the main control unit, and the functional module is connected with the FPGA circuit.

In this embodiment, the main control unit in the FPGA board card adopts an MSP430 single chip microcomputer, the programmable power supply adopts an MAX15301, and the FPGA circuit adopts an FPGA chip.

The storage unit in the external board card adopts EEPROM, the resistance module adopts RL0603FR-070R1L, and the function module adopts ADV 7511.

The MSP430 singlechip is connected with the EEPROM through an SCL line and an SDA line, and the FPGA chip is connected with the ADV7511 through a GPIO line.

An I2C interface of the MSP430 singlechip is connected with the MAX15301, and an output end VCCIO of the MAX15301 is connected with the FPGA chip. The MSP430 singlechip is connected with the MAX15301 through an SCL line and an SDA line.

The utility model discloses a self-adaptation level standard's FPGA interface circuit is when using, and the MSP430 singlechip makes its output accord with the voltage of external integrated circuit board level standard through I2C interface configuration MAX 15301. The voltage output by the programmable power supply MAX15301 is accessed to the general input/output GPIO reference voltage input end VCCIO of the FPGA chip, the voltage determines the level standard supported by the general input/output GPIO, and the self-adaption of the FPGA interface level and an external board card is realized.

After electrification, the MSP430 single chip microcomputer detects whether an external board card exists through the resistance module, if the external board card exists, the level standard supported in the EEPROM is read, the programmable power supply MAX15301 is configured, the FPGA chip is normally started, interaction with the external board card ADV7511 is carried out, and the function of the external board card is achieved.

After electrification, if the MSP430 singlechip does not detect the existence of an external board card, the programmable power supply MAX15301 is configured to output 0V, so that specific general purpose input/output GPIO of the FPGA circuit is not enabled, and the power consumption of the system is reduced.

The FPGA board card can be compatible with external board cards with different level standards, so that the interface flexibility of the FPGA board card is improved, the product development period and the cost are reduced, and the FPGA board card has a wide application prospect.

The above-mentioned embodiments are only one of the preferred embodiments of the present invention, and the general changes and substitutions performed by those skilled in the art within the technical scope of the present invention should be included in the protection scope of the present invention.

Claims

1. An FPGA interface circuit adaptive to level standard is characterized by comprising an FPGA board card and an external board card,

the FPGA board card is provided with a main control unit, a programmable power supply and an FPGA circuit, the main control unit, the programmable power supply and the FPGA circuit are sequentially connected, the main control unit on the FPGA board card is connected with an external board card to perform insertion detection of the external board card and is used for reading the level standard of the external board card, and the programmable power supply acquires the configuration of the level standard through the main control unit.

2. The FPGA interface circuit according to claim 1, wherein a storage unit, a resistor module and a function module are arranged on the external board card, the storage unit and the resistor module are both connected with the main control unit, and the function module is connected with the FPGA circuit.

3. The adaptive level standard FPGA interface circuit of claim 2, wherein the master control unit is connected to the storage unit via an SCL line and an SDA line, and the FPGA circuit is connected to the functional module via a GPIO line.

4. The adaptive level standard FPGA interface circuit of claim 2 or 3, wherein the I2C interface of the main control unit is connected to the programmable power supply, and an output terminal VCCIO of the programmable power supply is connected to the FPGA circuit.

5. The adaptive level standard FPGA interface circuit of claim 4, wherein the master control unit is connected to the programmable power supply via an SCL line and an SDA line.

6. The adaptive level standard FPGA interface circuit of claim 1, wherein the master control unit is an MSP430 single chip microcomputer, the programmable power supply is MAX15301, and the FPGA circuit is an FPGA chip.

7. The FPGA interface circuit of claim 2, wherein the memory unit is an EEPROM, the resistor module is RL0603FR-070R1L, and the function module is ADV 7511.