CN217085090U - Positive and negative voltage sampling circuit - Google Patents

Positive and negative voltage sampling circuit Download PDF

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Publication number
CN217085090U
CN217085090U CN202221587542.XU CN202221587542U CN217085090U CN 217085090 U CN217085090 U CN 217085090U CN 202221587542 U CN202221587542 U CN 202221587542U CN 217085090 U CN217085090 U CN 217085090U
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positive
resistor
pin
negative voltage
diode
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张昆
陶兴强
哈锦成
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Chengdu Jingrong Lianchuang Technology Co ltd
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Chengdu Jingrong Lianchuang Technology Co ltd
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Abstract

The utility model discloses a positive negative voltage sampling circuit, including resistance R1, ground resistance R2, resistance R3, resistance R4, ground capacitance C1, diode D1, diode D2, operational amplifier U1 and singlechip chip U2. The positive and negative voltage sampling circuit can sample positive voltage and negative voltage simultaneously, and the sampling amplitude is set to be-DC 30V- + DC30V, which covers most of small amplitude sampling requirements. The circuit has the characteristics of simple structure, few components, reverse connection prevention, reverse current flow prevention and the like, is favorable for improving the productivity, and solves the problem that only positive voltage or negative voltage can be singly sampled in the past for voltage signal acquisition, thereby improving the application range of the signal acquisition device.

Description

Positive and negative voltage sampling circuit
Technical Field
The utility model belongs to the technical field of the sampling circuit, concretely relates to positive negative voltage sampling circuit.
Background
In the field of wind power generation, a large amount of equipment needs to be monitored, monitoring output signals of various kinds of equipment are various, and the levels are inconsistent, so that signal acquisition monitoring equipment is various and even repeated; although some devices have multiple sampling interfaces, the interface sampling function is single, and often only positive voltage sampling or only negative voltage sampling is provided, because of the diversity of target sampling signals, many interfaces cannot be used, and resources are wasted.
For direct current low voltage sampling, the prior art often utilizes the resistance voltage division mode, sets up the target voltage in microcontroller's index scope, utilizes microcontroller's analog-to-digital sampling function to sample, and this kind of mode leads to the target sampling scope can only be the positive voltage, can't sample the negative voltage to the poor stability of sampling, the ripple and the burr of target sampling lead to the output value of sampling very easily to have very big fluctuation.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a solve above-mentioned problem, provided a positive negative voltage sampling circuit.
The technical scheme of the utility model is that: a positive and negative voltage sampling circuit comprises a resistor R1, a grounding resistor R2, a resistor R3, a resistor R4, a grounding capacitor C1, a diode D1, a diode D2, an operational amplifier U1 and a singlechip chip U2;
one end of the resistor R1 is used as the input end of the positive and negative voltage sampling circuit, and the other end is respectively connected with the cathode of the diode D1, the cathode of the diode D2, the grounding resistor R2 and the non-inverting input end of the operational amplifier U1; the anode of the diode D1 is connected with one end of the resistor R4; the other end of the resistor R4 is connected with a voltage bias VDC 1; the anode of the diode D2 is grounded; the inverting input end of the operational amplifier U1 is respectively connected with the output end of the operational amplifier U1 and one end of the resistor R3; the positive power supply end of the operational amplifier U1 is connected with an external power supply VCC; the negative power supply end of the operational amplifier U1 is grounded; a Vin pin of the singlechip chip U2 is respectively connected with the other end of the resistor R3 and the grounding capacitor C1; the Vref + pin and the Vref-pin of the single chip U2 are both grounded; the pin D0 of the single chip U2 is used as the output end of the positive and negative voltage sampling circuit and is respectively connected with the pin D1, the pin D2, the pin D3, the pin D4, the pin D5, the pin D6 and the pin D7.
Further, the operational amplifier U1 is model OPA340 NA.
Further, the model of the singlechip chip U2 is ADC108S022 CIMTX.
The utility model has the advantages that:
(1) the positive and negative voltage sampling circuit can sample positive voltage and negative voltage simultaneously, and the sampling amplitude is set to be-DC 30V- + DC30V, which covers most of small amplitude sampling requirements. The circuit has simple structure and few components, has the characteristics of reverse connection prevention, reverse current backflow prevention and the like, is beneficial to improving the productivity, solves the problem that the voltage signal acquisition can only sample positive voltage or negative voltage singly in the prior art, and further improves the application range of the signal acquisition device;
(2) the positive and negative voltage sampling circuit can be applied to various devices needing to sample voltage, such as wind power, hydropower, thermal power generation and the like, and particularly can be used as a conditioning circuit of a voltage sampling input port to finish sampling of positive and negative voltage.
Drawings
FIG. 1 is a circuit diagram of a positive and negative voltage sampling circuit;
fig. 2 is a schematic diagram of a logic control sequence of the positive and negative voltage sampling circuits.
Detailed Description
The embodiments of the present invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, the utility model provides a positive and negative voltage sampling circuit, including resistance R1, ground resistance R2, resistance R3, resistance R4, ground capacitance C1, diode D1, diode D2, operational amplifier U1 and singlechip chip U2;
one end of the resistor R1 is used as the input end of the positive and negative voltage sampling circuit, and the other end is respectively connected with the cathode of the diode D1, the cathode of the diode D2, the grounding resistor R2 and the non-inverting input end of the operational amplifier U1; the anode of the diode D1 is connected with one end of the resistor R4; the other end of the resistor R4 is connected with a voltage bias VDC 1; the anode of the diode D2 is grounded; the inverting input end of the operational amplifier U1 is respectively connected with the output end of the operational amplifier U1 and one end of the resistor R3; the positive power supply end of the operational amplifier U1 is connected with an external power supply VCC; the negative power supply end of the operational amplifier U1 is grounded; a Vin pin of the singlechip chip U2 is respectively connected with the other end of the resistor R3 and the grounding capacitor C1; the Vref + pin and the Vref-pin of the single chip U2 are both grounded; the pin D0 of the single chip U2 is used as the output end of the positive and negative voltage sampling circuit and is respectively connected with the pin D1, the pin D2, the pin D3, the pin D4, the pin D5, the pin D6 and the pin D7.
In the embodiment of the present invention, the model of the operational amplifier U1 is OPA340 NA.
In the embodiment of the present invention, the model of the single chip microcomputer chip U2 is ADC108S022 CIMTX.
In the embodiment of the present invention, Vin is set as the input end of the signal to be sampled, and is connected to the external signal to be collected, and the input amplitude is-DC 30V- + DC 30V. The signal of waiting to gather is connected to resistance R1 after the circuit is input to from Vin, and resistance R1 resistance value sets up to 20K omega, and the encapsulation sets up to 0805, prevents that the too big burning out of electric current sampling circuit. The signal is sent to junction a of diode D1 and diode D2, diode D1 and diode D2 are the same type (model 1N5819 RLG), the positive terminal is connected to resistor R4, the negative terminal is connected to a, resistor R4 is set to 20K Ω, the package is 0805, the positive terminal of diode D2 is connected to ground, and the negative terminal is connected to a. The voltage calculation relation of the point A is as follows: (V DC1 -V B )/R 4 -V D1 =(V A -V in )/R 1 +(V A -V C )/R 2V DC1 In order to be a bias voltage, the bias voltage,V B is the voltage at the point B and is,V D1 is the voltage over the diode D1 and,V A the voltage at the point a is used as the voltage,V C is the voltage of the point C, and the voltage of the point C,V in the voltage to be collected is the input signal.V DC1 Is set to be + DC30V,V C set to 0V, the above equation reduces to: (30-V B )/R 4 -V D1 =(V A -V in )/R 1 +V A /R 2 So that it is possible to push out:V in = V A +( R 1 / R 2 )* V A - R 1 *(30- V B )/ R 4 + R 1 * V D1V A ={[ V in + R 1 *(30- V B )/ R 4 - R 1 * V D1 ]* R 1 }/( R 1 + R 2 ). When in useV in When the input is changed, the user can select the input,V A with the output changing, the changing relation is linear, becauseV DC1 Is set to be + DC30V,V in is limited to-DC 30V to + DC 30V.
To obtain a wider sampling range, adjustments may be madeV DC1 By a value ofV A ={[ V in + R 1 *(30- V B )/ R 4 -R 1 * V D1 ]* R 1 }/( R 1 + R 2 ) Calculate outV A Range of (1), controlV A 0 to DC 5V.
In the embodiment of the present invention, as shown in fig. 2, the logic control sequence of the circuit is: an input signal is input from S1, the anti-reverse diode S6 prevents the reverse current from flowing in, the input signal passes through the current limiting resistor S5, and the input current of the current limiting resistor S5 to the limiting signal is within the collectable range. The bias voltage S2 is connected to the voltage-dividing resistor S3 to provide voltage bias for the sampling path, and the voltage-dividing resistor S3 is connected to the anti-reverse diode S4 to prevent the input sampling signal from being too high and damaging the system. The anti-reverse diode S4, the current-limiting resistor S5 and the voltage-dividing resistor S7 are connected to the voltage follower S9, and the voltage follower S9 is responsible for stabilizing the voltage to a certain amplitude, improving the driving capability and ensuring that the filtering S10 and the AD sampling S11 obtain stable sampling voltage. The filtering S10 is a filtering circuit formed by a resistor R3 and a grounding capacitor C1, noise waves on the acquisition circuit are filtered, and the acquired signals are clean and free of noise waves. The AD sampling S11 is responsible for collecting signals and performing data conversion.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention, and it is to be understood that the scope of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations without departing from the spirit of the invention, which fall within the scope of the claims.

Claims (3)

1. A positive and negative voltage sampling circuit is characterized by comprising a resistor R1, a grounding resistor R2, a resistor R3, a resistor R4, a grounding capacitor C1, a diode D1, a diode D2, an operational amplifier U1 and a single chip microcomputer chip U2;
one end of the resistor R1 is used as the input end of the positive and negative voltage sampling circuit, and the other end of the resistor R1 is respectively connected with the cathode of the diode D1, the cathode of the diode D2, the grounding resistor R2 and the non-inverting input end of the operational amplifier U1; the anode of the diode D1 is connected with one end of a resistor R4; the other end of the resistor R4 is connected with a voltage bias VDC 1; the anode of the diode D2 is grounded; the inverting input end of the operational amplifier U1 is respectively connected with the output end of the operational amplifier U1 and one end of the resistor R3; the positive power supply end of the operational amplifier U1 is connected with an external power supply VCC; the negative power supply end of the operational amplifier U1 is grounded; a Vin pin of the singlechip chip U2 is respectively connected with the other end of the resistor R3 and the grounding capacitor C1; the Vref + pin and the Vref-pin of the single chip U2 are both grounded; and a pin D0 of the singlechip chip U2 is used as an output end of the positive and negative voltage sampling circuit and is respectively connected with a pin D1, a pin D2, a pin D3, a pin D4, a pin D5, a pin D6 and a pin D7.
2. The positive-negative voltage sampling circuit of claim 1, wherein the operational amplifier U1 is model OPA340 NA.
3. The positive-negative voltage sampling circuit according to claim 1, wherein the model of the monolithic chip U2 is ADC108S022 CIMTX.
CN202221587542.XU 2022-06-24 2022-06-24 Positive and negative voltage sampling circuit Active CN217085090U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202221587542.XU CN217085090U (en) 2022-06-24 2022-06-24 Positive and negative voltage sampling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202221587542.XU CN217085090U (en) 2022-06-24 2022-06-24 Positive and negative voltage sampling circuit

Publications (1)

Publication Number Publication Date
CN217085090U true CN217085090U (en) 2022-07-29

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Application Number Title Priority Date Filing Date
CN202221587542.XU Active CN217085090U (en) 2022-06-24 2022-06-24 Positive and negative voltage sampling circuit

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CN (1) CN217085090U (en)

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