CN216388083U

CN216388083U - DPU device based on FPGA

Info

Publication number: CN216388083U
Application number: CN202122964619.2U
Authority: CN
Inventors: 严和平
Original assignee: Shanghai Xinpu Information Technology Co ltd
Current assignee: Shanghai Xinpu Information Technology Co ltd
Priority date: 2021-11-29
Filing date: 2021-11-29
Publication date: 2022-04-26
Anticipated expiration: 2031-11-29

Abstract

The new model discloses an FPGA-based DPU device, comprising: an FPGA module: receiving external data of an interface module for operation and sending the operation result to an external device through the interface module; RISC module: receiving a memory management signal when the FPGA module operates To the memory management module; the memory management module: manages the data transmission channel between the memory module and the FPGA module; the memory module: includes a plurality of memory groups, used to store the temporary data when the FPGA module performs operations; the interface module: used to provide the device with Data interaction interface of external devices: timing module: used to generate the clock signal required for the FPGA module to work; power module: to provide the required operating voltage for the entire DPU device, effectively control the memory bank and the FPGA module for data exchange, and improve the The data processing efficiency of the FPGA module ensures the safety and stability of the overflow data when the calculation load of the FPGA module is too large, and can provide the multi-project calculation of the FPGA with the guarantee of multiple calculation channels.

Description

DPU device based on FPGA

Technical Field

The application relates to the field of embedded technology, in particular to a DPU device based on an FPGA.

Background

The DPU is an artificial intelligence big data analysis system project. It consists of a series of pipeline algorithms, from sorting, indexing, grouping and optimization to processing and analyzing matrix and tensor large data. The sort and index pipeline arranges the data in order, providing a descriptive basis for better understanding of the order of things that occur in all dimensions. Packet pipelines place data in proportion or range, generating a diagnostic basis for better signal detection, finding useful structures, defining logical or salient features. The scale is inherent to the data structure, and the range is a choice of human preference. Optimizing the pipeline ultimately makes the data valuable, extracting intelligent information from the data and building predictive models from which we can infer what will happen in the future. In the process, a large amount of data calculation processing is required, and the requirements on processing speed and stability of data in the memory are high. The traditional memory architecture of the DPU device generally needs a plurality of clocks to finish quick access to uncleaned data and derivative arrays, and the data processing speed of the DPU is seriously influenced.

Accordingly, a solution is desired to solve or at least mitigate the above-mentioned deficiencies of the prior art.

SUMMERY OF THE UTILITY MODEL

The present invention is directed to a DPU device based on an FPGA to solve at least one of the above problems.

An FPGA-based DPU device, comprising: an FPGA module: receiving external data of the interface module, performing operation and sending an operation result to external equipment through the interface module; RISC module: receiving a memory management signal when the FPGA module operates, and sending the memory management signal to a memory management module; a memory management module: the system comprises at least two triggers, wherein the triggers respectively receive memory control signals of a RISC module and an FPGA module and manage a data transmission channel between the memory module and the FPGA module; a memory module: the FPGA module comprises a plurality of memory groups and a plurality of storage modules, wherein the memory groups are used for storing temporary data when the FPGA module performs operation; an interface module: the data interaction interface for providing the device and the external equipment comprises: a time sequence module: the FPGA module comprises at least two counters and a clock signal generator, wherein the counters are used for generating clock signals required by the operation of the FPGA module; a power supply module: providing the required operating voltage for the entire DPU device.

Further, the memory management module specifically includes: the circuit comprises a first trigger U3 and a second trigger U4, wherein the enable end of the first trigger U3 is connected with the memory control end of the RISC module, the input pins of the first trigger U3 are respectively connected with the pins of the memory selection signal end of the RISC module, and the output pins of the first trigger U are grounded through a forward diode and a resistor; the enabling end of the second trigger U4 is connected with the memory control end of the FPGA module, the input end of the second trigger U4 is connected with the reference voltage, and the output end of the second trigger U4 is connected with the control end of each memory group through a forward diode; the anodes of the diodes of the first flip-flop U3 are connected to the anodes of the corresponding diodes of the second flip-flop U4.

Further, the timing module specifically includes: the circuit comprises a crystal oscillator Y1, wherein two ends of the crystal oscillator Y1 are grounded through a capacitor C1 and a capacitor C2 respectively, and a resistor R1 is connected between two ends of the crystal oscillator Y1; one end of the crystal oscillator Y1 is connected with the RST pin of the first counter U1, and the other end of the crystal oscillator Y1 is connected with the PI pin of U1; the output pin Q8 of the first counter U1 is connected to the clkb pin of the second counter U2, and the qa pin of the second technician outputs the clock signal.

Further, the power module comprises a transformer and a rectifier which are connected in sequence, and external alternating current is rectified and transformed and then is transmitted to the first power module, the second power module and the third power module.

Further, the first power module includes a chip U5, an input terminal of which is grounded through a forward polarity capacitor C3, an output terminal of which is grounded through a capacitor C7, a capacitor C8 and a forward polarity capacitor C5, respectively, an output terminal of which outputs a first operating voltage through an inductor L1, and an output terminal of which is grounded through a capacitor C4 and a forward polarity capacitor C6, respectively.

Further, the second power module includes a chip U6, an input terminal of which is grounded through a forward polarity capacitor C9, a ground terminal of which is grounded through a resistor R11, a resistor R10 is connected between an output terminal of which and the ground terminal, an output terminal of which outputs a second operating voltage, and output terminals of which are grounded through a capacitor C11, a capacitor C12 and a forward polarity capacitor C10, respectively; the negative terminal of the polar capacitor C10 is connected to the digital block ground AGND via the inductor L2.

Further, the third power module includes a chip U7, an output terminal of which is grounded through a forward polarity capacitor C13, a ground terminal of which is grounded through a resistor R14, a resistor R12 is connected between the output terminal and the ground terminal, the output terminal of which outputs a third operating voltage, and the output terminals of which are grounded through a resistor R13, a capacitor C15, a capacitor C16, and a forward polarity capacitor C14, respectively.

Further, the interface module includes: PCIe interface, QSFP interface, SSD interface, USB interface, SSD interface, GigE interface and GPIO interface.

Furthermore, the FPGA module and the RISC module are also connected with a safety module.

Furthermore, the FPGA module is also connected with a JTAG module.

Advantageous effects

When the application is used for actually carrying out data operation, the internal memory trigger signal and the control signal which are provided by the FPGA module during operation are processed by the internal instruction set of the RISC module to generate the internal memory selection signal, and then the internal memory group in the internal memory module is controlled by the internal memory management module to carry out data interaction with the FPGA module, so that the data processing efficiency of the FPGA module is effectively improved, the safety and the stability of overflowing data are ensured when the calculation load of the FPGA module is overlarge, and the normal operation of multi-project calculation which is ensured by a multi-path calculation channel can be provided for the FPGA.

The application also provides a plurality of external data interfaces to meet the requirements of various data working environments, and normal use of each internal module is ensured through multi-stage power output.

Drawings

Fig. 1 is a schematic diagram of the present application.

Fig. 2 is a schematic circuit diagram of a memory management module according to an embodiment of the present application.

Fig. 3 is a schematic circuit diagram of a sequential module according to an embodiment of the present application.

Fig. 4 is a circuit schematic diagram of a first power module according to an embodiment of the present application.

Fig. 5 is a circuit schematic diagram of a second power module according to an embodiment of the present application.

Fig. 6 is a circuit schematic diagram of a third power module according to an embodiment of the present application.

Detailed Description

In order to make the implementation objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below with reference to the drawings in the embodiments of the present application. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are a subset of the embodiments in the present application and not all embodiments in the present application. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

As shown in fig. 1, an FPGA-based DPU apparatus includes: an FPGA module: receiving external data of the interface module, performing operation and sending an operation result to external equipment through the interface module; RISC module: receiving a memory management signal when the FPGA module operates, and sending the memory management signal to a memory management module; a memory management module: the system comprises at least two triggers, wherein the triggers respectively receive memory control signals of a RISC module and an FPGA module and manage a data transmission channel between the memory module and the FPGA module; a memory module: the FPGA module comprises a plurality of memory groups and a plurality of storage modules, wherein the memory groups are used for storing temporary data when the FPGA module performs operation; an interface module: the data interaction interface for providing the device and the external equipment comprises: a time sequence module: the FPGA module comprises at least two counters and a clock signal generator, wherein the counters are used for generating clock signals required by the operation of the FPGA module; a power supply module: the power supply device provides required working voltage for the whole DPU device, comprises a transformer and a rectifier which are connected in sequence, and transmits external alternating current to a first power module, a second power module and a third power module after rectifying and transforming the external alternating current. The FPGA module and the RISC module are also connected with a safety module. The FPGA module is also connected with a JTAG module. And the safety module is used for detecting the working states of the FPGA module and the RISC module and timely informing the device of emergency treatment when the working states are abnormal. The JTAG module is used for presetting working states for the FPGA module so as to meet different calculation requirements.

As shown in fig. 2, the memory management module includes a first flip-flop U3 and a second flip-flop U4, an enable terminal of the first flip-flop U3 is connected to a memory control terminal of the RISC module, input pins of the first flip-flop U3 are respectively connected to pins of a memory selection signal terminal of the RISC module, and pins of an output terminal of the first flip-flop U are grounded through a forward diode and a resistor; the enabling end of the second trigger U4 is connected with the memory control end of the FPGA module, the input end of the second trigger U4 is connected with the reference voltage, and the output end of the second trigger U4 is connected with the control end of each memory group through a forward diode; the anodes of the diodes of the first flip-flop U3 are connected to the anodes of the corresponding diodes of the second flip-flop U4. The first flip-flop U3 and the second flip-flop U4 both use eight flip-flops, that is, the number of memory banks in the corresponding memory module is eight. The memory group adopts DDR4/QDDR + specification.

As shown in fig. 3, the timing module includes a crystal oscillator Y1, two ends of which are grounded through a capacitor C1 and a capacitor C2, respectively, and a resistor R1 is connected between the two ends of the crystal oscillator Y1; one end of the crystal oscillator Y1 is connected with the RST pin of the first counter U1, and the other end of the crystal oscillator Y1 is connected with the PI pin of U1; the output pin Q8 of the first counter U1 is connected to the clkb pin of the second counter U2, and the qa pin of the second technician outputs the clock signal. The two counters form a frequency division circuit to process the original pulse signal of the crystal oscillator Y1 so as to meet the working requirement of the FPGA module. When necessary, a plurality of groups of frequency division circuits can be arranged to generate a plurality of groups of time sequence signals, and the application environment of the FPGA module is further improved by controlling the required time sequence signals through the multiplexer.

As shown in fig. 4, the first power module includes a chip U5, an input terminal of which is grounded through a forward polarity capacitor C3, an output terminal of which is grounded through a capacitor C7, a capacitor C8 and a forward polarity capacitor C5, respectively, an output terminal of which outputs a first operating voltage through an inductor L1, and an output terminal of which is grounded through a capacitor C4 and a forward polarity capacitor C6, respectively. The polar capacitors C3, C5 and C6 are all 10 muF, the capacitor C7 is 0.01 muF, the capacitor C8 and the capacitor C4 are 0.1 muF, and the output first working voltage is 1.2V.

As shown in fig. 5, the second power module includes a chip U6, an input terminal of which is grounded through a forward polarity capacitor C9, a ground terminal of which is grounded through a resistor R11, a resistor R10 connected between an output terminal of which and the ground terminal, an output terminal of which outputs the second operating voltage, and output terminals of which are grounded through a capacitor C11, a capacitor C12 and a forward polarity capacitor C10, respectively; the negative terminal of the polar capacitor C10 is connected to the digital block ground AGND via the inductor L2. The polar capacitors C9 and C10 are 10 muF, the capacitor C11 is 0.01 muF, the capacitor C12 is 0.1 muF, the resistor R11 and the resistor R10 are 100 omega, and the output second working voltage is 2.5V.

As shown in fig. 6, the third power module includes a chip U7, an output terminal of which is grounded through a forward polarity capacitor C13, a ground terminal of which is grounded through a resistor R14, a resistor R12 connected between the output terminal and the ground terminal of which outputs a third operating voltage, and output terminals of which are grounded through a resistor R13, a capacitor C15, a capacitor C16, and a forward polarity capacitor C14, respectively. The polar capacitors C13 and C14 are 10 muF, the capacitor C15 is 0.01 muF, the capacitor C16 is 0.1 muF, the resistor R14 is 162 omega, the resistor R12 is 100 omega, and the output third working voltage is 3.3V. In the embodiment, the chips U5, U6 and U7 all adopt LT 1084.

Claims

1. An FPGA-based DPU apparatus, comprising:

an FPGA module: receiving external data of the interface module, performing operation and sending an operation result to external equipment through the interface module;

RISC module: receiving a memory management signal when the FPGA module operates, and sending the memory management signal to a memory management module;

a memory management module: the system comprises at least two triggers, wherein the triggers respectively receive memory control signals of a RISC module and an FPGA module and manage a data transmission channel between the memory module and the FPGA module;

a memory module: the FPGA module comprises a plurality of memory groups and a plurality of storage modules, wherein the memory groups are used for storing temporary data when the FPGA module performs operation;

an interface module: the data interaction interface for providing the device and the external equipment comprises:

a time sequence module: the FPGA module comprises at least two counters and a clock signal generator, wherein the counters are used for generating clock signals required by the operation of the FPGA module;

a power supply module: providing the required operating voltage for the entire DPU device.

2. The FPGA-based DPU device of claim 1, wherein the memory management module is specifically: the circuit comprises a first trigger U3 and a second trigger U4, wherein the enable end of the first trigger U3 is connected with the memory control end of the RISC module, the input pins of the first trigger U3 are respectively connected with the pins of the memory selection signal end of the RISC module, and the output pins of the first trigger U are grounded through a forward diode and a resistor; the enabling end of the second trigger U4 is connected with the memory control end of the FPGA module, the input end of the second trigger U4 is connected with the reference voltage, and the output end of the second trigger U4 is connected with the control end of each memory group through a forward diode; the anodes of the diodes of the first flip-flop U3 are connected to the anodes of the corresponding diodes of the second flip-flop U4.

3. The FPGA-based DPU device of claim 1, wherein the timing module is specifically to: the circuit comprises a crystal oscillator Y1, wherein two ends of the crystal oscillator Y1 are grounded through a capacitor C1 and a capacitor C2 respectively, and a resistor R1 is connected between two ends of the crystal oscillator Y1; one end of the crystal oscillator Y1 is connected with the RST pin of the first counter U1, and the other end of the crystal oscillator Y1 is connected with the PI pin of U1; the output pin Q8 of the first counter U1 is connected to the clkb pin of the second counter U2, and the qa pin of the second technician outputs the clock signal.

4. The FPGA-based DPU device of claim 1, wherein the power module comprises a transformer and a rectifier connected in sequence, and the transformer and the rectifier rectify and transform external alternating current and transmit the rectified alternating current to the first power module, the second power module and the third power module.

5. The FPGA-based DPU device of claim 4, wherein the first power module comprises a chip U5 having an input terminal coupled to ground through a forward polarity capacitor C3, an output terminal coupled to ground through a capacitor C7, a capacitor C8 and a forward polarity capacitor C5, respectively, an output terminal coupled to the first operating voltage through an inductor L1, and an output terminal coupled to ground through a capacitor C4 and a forward polarity capacitor C6, respectively.

6. The FPGA-based DPU device of claim 4, wherein the second power module comprises a chip U6, an input terminal of which is grounded through a forward polarity capacitor C9, a ground terminal of which is grounded through a resistor R11, a resistor R10 is connected between an output terminal of which and the ground terminal, an output terminal of which outputs the second operating voltage, and output terminals of which are grounded through a capacitor C11, a capacitor C12 and a forward polarity capacitor C10, respectively; the negative terminal of the polar capacitor C10 is connected to the digital block ground AGND via the inductor L2.

7. The FPGA-based DPU device of claim 4, wherein the third power module comprises a chip U7, an output terminal of which is grounded through a forward polarity capacitor C13, a ground terminal of which is grounded through a resistor R14, a resistor R12 is connected between the output terminal and the ground terminal, an output terminal of which outputs the third operating voltage, and output terminals of which are grounded through a resistor R13, a capacitor C15, a capacitor C16 and a forward polarity capacitor C14, respectively.

8. The FPGA-based DPU device of claim 1, wherein the interface module comprises: PCIe interface, QSFP interface, SSD interface, USB interface, SSD interface, GigE interface and GPIO interface.

9. The FPGA-based DPU device of claim 1, wherein the security module is further coupled to the FPGA module and the RISC module.

10. The FPGA-based DPU device of claim 1, wherein the FPGA module is further coupled to a JTAG module.