CN216351051U

CN216351051U - Verification circuit of serial port chip test system

Info

Publication number: CN216351051U
Application number: CN202120920643.3U
Authority: CN
Inventors: 张大伟; 屈粮富; 宋晓荣; 马慧娟
Original assignee: Tianjin Puzhixin Network Measurement And Control Technology Co ltd
Current assignee: Tianjin Puzhixin Network Measurement And Control Technology Co ltd
Priority date: 2021-04-29
Filing date: 2021-04-29
Publication date: 2022-04-19
Anticipated expiration: 2031-04-29

Abstract

A verification circuit of a serial port chip test system comprises a test circuit, wherein the test circuit comprises a test chip, a switch circuit and a standard chip; the test chip is connected with the input end of the switch circuit, the output end of the switch circuit is connected with the standard chip, the test chip and the standard chip are set to be in a one-transmitting-one-receiving state, the performance of the test chip is judged by comparing the data of the test chip with the data of the standard chip, and the working state of the test circuit is controlled by the switch circuit; the test circuit comprises a first filter circuit and a second filter circuit; the test chip is connected with the first filter circuit, the standard chip is connected with the second filter circuit, and the first filter circuit and the second filter circuit are used for filtering the test chip and the standard chip respectively so as to improve the accuracy of test parameters.

Description

Verification circuit of serial port chip test system

Technical Field

The utility model relates to the technical field of serial port chip testing, in particular to a verification circuit of a serial port chip testing system.

Background

The serial port chip is a device which can convert parallel data characters received from the CPU into continuous serial data streams and send the serial data streams out, and can convert the received serial data streams into parallel data characters and supply the parallel data characters to the CPU; with the development of the electronic industry, the performance requirements of the serial port chip are higher and higher, and the direct current parameters, the time parameters and other parameters of the serial port chip need to be tested; however, the test chip has no standard chip contrast during testing, the tested parameters are not accurate, and the test parameters are affected by the fact that the test chip and the standard chip have no filter circuit during transceiving.

SUMMERY OF THE UTILITY MODEL

The utility model aims to overcome the defects of the prior art and provides a verification circuit of a serial port chip test system.

The technical problem to be solved by the utility model is realized by adopting the following technical scheme:

a verification circuit of a serial port chip test system comprises a test circuit, wherein the test circuit comprises a test chip, a switch circuit and a standard chip; the test chip is connected with the input end of the switch circuit, the output end of the switch circuit is connected with the standard chip, the test chip and the standard chip are set to be in a one-transmitting-one-receiving state, the performance of the test chip is judged by comparing with the data of the standard chip, and the working state of the test circuit is controlled by the switch circuit.

Preferably, the switching circuit includes a switching relay PRLY21B and a switching relay PRLY 22B.

Preferably, the test circuit further comprises a control circuit connected to the test circuit for controlling the test circuit.

Preferably, the chip model of the control circuit is PXIe _ 6571.

Preferably, the test circuit comprises a first filter circuit and a second filter circuit; the test chip is connected with the first filter circuit, and the standard chip is connected with the second filter circuit.

Preferably, the test circuit also comprises an oscilloscope and a source test instrument, wherein the oscilloscope and the source test instrument are connected with the test circuit.

Preferably, the load circuit is used for controlling and adjusting the load, and comprises a plurality of jumper circuits with the same structure.

Preferably, the standard chip model is MAX 3232; the test chip is of model CJ 3232.

Preferably, the test circuit further comprises a power control circuit; the power supply control circuit is connected with the standard chip.

Preferably, the test circuit further comprises a switching circuit connected to the test circuit for switching data channels.

The utility model has the advantages and positive effects that:

1. the utility model relates to a verification circuit of a serial port chip test system, which comprises a test circuit, wherein the test circuit comprises a test chip, a switch circuit and a standard chip; the test chip is connected with the input end of the switch circuit, the output end of the switch circuit is connected with the standard chip, the test chip and the standard chip are set to be in a one-transmitting-one-receiving state, the performance of the test chip is judged by comparing with the data of the standard chip, and the working state of the test circuit is controlled by the switch circuit.

2. The test circuit comprises a first filter circuit and a second filter circuit; the test chip is connected with the first filter circuit, the standard chip is connected with the second filter circuit, and the first filter circuit and the second filter circuit are used for filtering the test chip and the standard chip respectively so as to improve the accuracy of test parameters.

Drawings

FIG. 1 is a block diagram of the circuit connections of the present invention;

FIG. 2 is a test circuit connection diagram of the present invention;

FIG. 3 is a control circuit connection diagram of the present invention;

FIG. 4 is a load circuit connection diagram of the present invention;

fig. 5 is a switching circuit connection diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, the verification circuit of a serial chip test system according to the present invention includes a test circuit, where the test circuit includes a test chip, a switch circuit, and a standard chip; the test chip is connected with the input end of the switch circuit, the output end of the switch circuit is connected with the standard chip, the test chip and the standard chip are set to be in a one-transmitting-one-receiving state, the performance of the test chip is judged by comparing with the data of the standard chip, and the working state of the test circuit is controlled by the switch circuit.

Specifically, the standard chip model is MAX 3232; the model of the test chip is CJ 3232; the switching circuit comprises a switching relay PRLY21B and a switching relay PRLY 22B; the test chip is connected with the standard chip through the switch circuit, the test chip can be set to be in a data sending mode and the standard chip can be set to be in a data receiving mode, and whether the performance of the test chip is good or not is judged by comparing the data sent by the test chip with the data received by the standard chip; the test chip can be set to a data receiving mode and the standard chip can be set to a data sending mode, whether the performance of the test chip is good or not is judged by comparing the data received by the test chip with the data sent by the standard chip, and the switch circuit controls the working state of the test circuit.

Further, as shown in fig. 2, the test circuit includes a first filter circuit and a second filter circuit; the test chip is connected with the first filter circuit, and the standard chip is connected with the second filter circuit; specifically, the first filter circuit includes a capacitor C1 and a capacitor C2; the second filter circuit includes a capacitor C9 and a capacitor C10.

Further, the test circuit further comprises a power supply control circuit; the power supply control circuit is connected with the standard chip.

Specifically, the power supply control circuit comprises a switch relay PRLY23B and a jumper switch J3; the switch relay PRLY23B and the jumper switch J3 are connected with a VCC pin of the standard chip.

Further, as shown in fig. 3, the testing apparatus further includes a control circuit connected to the testing circuit, for controlling the testing circuit; specifically, the chip model of the control circuit is PXIe _ 6571; the S0_ DIO pins of the control circuit are respectively and correspondingly connected with the S0_ DIO pins of the test circuit.

The testing circuit further comprises an oscilloscope and a source testing instrument, wherein the oscilloscope and the source testing instrument are connected with the testing circuit; specifically, the S0_ DIO1 pin, the S0_ DIO3 pin, the S0_ DIO5 pin and the S0_ DIO7 pin of the test chip are connected to the oscilloscope; the S0_ DIO23 pin, the S0_ DIO25 pin, the S0_ DIO27 pin and the S0_ DIO29 pin of the test chip are connected with the source test instrument.

Further, as shown in fig. 4, the load circuit is further included for controlling and adjusting the load, and the load circuit includes a plurality of jumper circuits with the same structure; specifically, the jumper circuit comprises a jumper switch J1, a capacitor C1 and a resistor R1; the S0_ TOU1 pin and the S0_ TOU2 pin of the load circuit are correspondingly connected to the S0_ TOU1 pin and the S0_ TOU2 pin of the test circuit, respectively.

Further, as shown in fig. 5, the testing apparatus further includes a switching circuit connected to the testing circuit, for switching the data channel; specifically, the S0_ DIO pin, the S0_ TOU pin, and the PMV pin of the switching circuit are respectively and correspondingly connected to the S0_ DIO pin, the S0_ TOU pin, and the PMV pin of the test circuit.

The working principle is as follows:

1. the test chip is connected with the input end of the switch circuit, the output end of the switch circuit is connected with the standard chip, the test chip and the standard chip are set to be in a transmitting-receiving state, and the performance of the test chip is judged by comparing the data of the test chip and the data of the standard chip;

2. controlling the working state of the test circuit through the switch circuit;

3. and filtering the test chip and the standard chip respectively through the first filter circuit and the second filter circuit to improve the accuracy of test parameters.

The utility model relates to a verification circuit of a serial port chip test system, which comprises a test circuit, wherein the test circuit comprises a test chip, a switch circuit and a standard chip; the test chip is connected with the input end of the switch circuit, the output end of the switch circuit is connected with the standard chip, the test chip and the standard chip are set to be in a one-transmitting-one-receiving state, the performance of the test chip is judged by comparing the data of the test chip with the data of the standard chip, and the working state of the test circuit is controlled by the switch circuit; the test circuit comprises a first filter circuit and a second filter circuit; the test chip is connected with the first filter circuit, the standard chip is connected with the second filter circuit, and the first filter circuit and the second filter circuit are used for filtering the test chip and the standard chip respectively so as to improve the accuracy of test parameters.

The above description is intended to describe in detail the preferred embodiments of the present invention, but the embodiments are not intended to limit the scope of the claims of the present invention, and all equivalent changes and modifications made within the technical spirit of the present invention should fall within the scope of the claims of the present invention.

Claims

1. The utility model provides a serial ports chip test system's verification circuit which characterized in that: the test circuit comprises a test chip, a switch circuit and a standard chip; the test chip is connected with the input end of the switch circuit, the output end of the switch circuit is connected with the standard chip, the test chip and the standard chip are set to be in a one-transmitting-one-receiving state, the performance of the test chip is judged by comparing with the data of the standard chip, and the working state of the test circuit is controlled by the switch circuit.

2. The verification circuit of the serial port chip test system according to claim 1, wherein: the switching circuit includes a switching relay PRLY21B and a switching relay PRLY 22B.

3. The verification circuit of the serial port chip test system according to claim 1, wherein: the test circuit also comprises a control circuit connected with the test circuit and used for controlling the test circuit.

4. The verification circuit of the serial port chip test system according to claim 3, wherein: the chip model of the control circuit is PXIe _ 6571.

5. The verification circuit of the serial port chip test system according to claim 1, wherein: the test circuit comprises a first filter circuit and a second filter circuit; the test chip is connected with the first filter circuit, and the standard chip is connected with the second filter circuit.

6. The verification circuit of the serial port chip test system according to claim 1, wherein: the testing circuit also comprises an oscilloscope and a source testing instrument, wherein the oscilloscope and the source testing instrument are connected with the testing circuit.

7. The verification circuit of the serial port chip test system according to claim 1, wherein: the load circuit is used for controlling and adjusting the load and comprises a plurality of jumper circuits with the same structure.

8. The verification circuit of the serial port chip test system according to claim 1, wherein: the model of the standard chip is MAX 3232; the test chip is of model CJ 3232.

9. The verification circuit of the serial port chip test system according to claim 1, wherein: the test circuit also comprises a power supply control circuit; the power supply control circuit is connected with the standard chip.

10. The verification circuit of the serial port chip test system according to claim 1, wherein: the test circuit also comprises a switching circuit connected with the test circuit and used for switching data channels.