CN2160157Y - Palladium grid field effect transistor - Google Patents
Palladium grid field effect transistor Download PDFInfo
- Publication number
- CN2160157Y CN2160157Y CN 93212942 CN93212942U CN2160157Y CN 2160157 Y CN2160157 Y CN 2160157Y CN 93212942 CN93212942 CN 93212942 CN 93212942 U CN93212942 U CN 93212942U CN 2160157 Y CN2160157 Y CN 2160157Y
- Authority
- CN
- China
- Prior art keywords
- palladium
- layer
- grid
- insulating barrier
- tack coat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model discloses structure of a palladium grid MOS device. An isolating layer which is arranged between a metallic electrode and a grid area in the two drain-source areas of the device is glued to an adhesive layer which can be firmly glued to the isolating layer and a palladium layer. The edge of a metallic grid palladium layer extends to the adhesive layer to make a grid periphery with a firmly adhesive structure which means the palladium layer-the adhesive layer-the isolating layer. Thus, the palladium layer is prevented from desquamating from the grid area, and the reliability of the device is enhanced.
Description
The utility model relates to a kind of structure of palladium grate MOS device.
The quick palladium layer of hydrogen of existing palladium grate MOS device is topped metal gates on the oxide layer of grid region, because the adhesion of palladium layer and oxide layer is firm inadequately, tends to come off from the grid region, causes component failure.
The purpose of this utility model is for overcoming the defective of above-mentioned prior art, avoid the palladium grid to come off, improving the reliability of device.
The utility model palladium grate MOS device structure is characterised in that, leakage, source two district's metal electrodes (1 at device, 2) and the insulating barrier (4) between grid region (3) go up to adhere to a kind of tack coat (5) that all can firmly adhere with insulating barrier and palladium layer, and the border extended that makes metal gate palladium layer (6) forms the secure bond structure of palladium layer one tack coat one insulating barrier so far on the tack coat in the grid outer edge.
Because the whole bonding of the edge of palladium grid and device firmly, just can avoid coming off of palladium grid.Compared with prior art, the utlity model has the more good effect of high reliability.
Description of drawings
Accompanying drawing is the generalized section of an embodiment of the utility model palladium grate MOS device structure.Wherein 1 is the drain region metal electrode, and 2 is the source region metal electrode, and 3 is the grid region, and 4 is SiO
2Layer, 5 is polysilicon layer, 6 is metal gate palladium layer.
The cross-section structure of an embodiment of the utility model palladium grate MOS device is illustrated in accompanying drawing.The insulating barrier of this embodiment between the leakage of device, source two district's metal electrodes (1,2) and grid region (3) is SiO
2Layer (4) is with polysilicon layer (5) conduct and SiO
2The tack coat that layer and palladium layer all can firmly be adhered.
Claims (2)
1, a kind of structure of palladium grate MOS device, it is characterized in that, on the insulating barrier between leakage, source two district's metal electrodes and the grid region of device, adhere to a kind of tack coat that all can firmly adhere with insulating barrier and palladium floor, and the border extended that makes metal gate palladium layer forms the secure bond structure of palladium layer one tack coat one insulating barrier so far on the tack coat at the grid outward flange.
According to the structure of the described palladium grate MOS device of claim 1, it is characterized in that 2, the insulating barrier between described leakage at device, source two district's metal electrodes and the grid region is SiO
2Layer, the described a kind of tack coat that all can firmly adhere with insulating barrier and palladium layer is a polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 93212942 CN2160157Y (en) | 1993-05-21 | 1993-05-21 | Palladium grid field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 93212942 CN2160157Y (en) | 1993-05-21 | 1993-05-21 | Palladium grid field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2160157Y true CN2160157Y (en) | 1994-03-30 |
Family
ID=33794150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 93212942 Expired - Fee Related CN2160157Y (en) | 1993-05-21 | 1993-05-21 | Palladium grid field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2160157Y (en) |
-
1993
- 1993-05-21 CN CN 93212942 patent/CN2160157Y/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |